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Wed, 04 Feb 2026 10:06:36 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Thomas Gleixner Cc: Biju Das , linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 4/9] irqchip/renesas-rzg2l: Drop IRQC_NUM_IRQ macro Date: Wed, 4 Feb 2026 18:06:20 +0000 Message-ID: <20260204180632.249139-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260204180632.249139-1-biju.das.jz@bp.renesas.com> References: <20260204180632.249139-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The total number of IRQs in RZ/G2L and RZ/G3L SoC are different. Introduce struct rzg2l_hw_info to handle the hardware differences and replace the macro IRQC_NUM_IRQ with num_irq variable in struct rzg2l_hw_info. Signed-off-by: Biju Das --- v1->v2: * No change --- drivers/irqchip/irq-renesas-rzg2l.c | 46 ++++++++++++++++++++--------- 1 file changed, 32 insertions(+), 14 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index 20e2b1c4587b..cd9909a85280 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -24,7 +24,6 @@ #define IRQC_IRQ_COUNT 8 #define IRQC_TINT_START (IRQC_IRQ_START + IRQC_IRQ_COUNT) #define IRQC_TINT_COUNT 32 -#define IRQC_NUM_IRQ (IRQC_TINT_START + IRQC_TINT_COUNT) =20 #define ISCR 0x10 #define IITSR 0x14 @@ -68,12 +67,21 @@ struct rzg2l_irqc_reg_cache { u32 titsr[2]; }; =20 +/** + * struct rzg2l_hw_info - Interrupt Control Unit controller hardware info = structure. + * @num_irq: Total Number of interrupts + */ +struct rzg2l_hw_info { + u8 num_irq; +}; + /** * struct rzg2l_irqc_priv - IRQ controller private data structure * @base: Controller's base address * @irqchip: Pointer to struct irq_chip * @fwspec: IRQ firmware specific data * @lock: Lock to serialize access to hardware registers + * @info: Pointer to struct rzg2l_hw_info * @cache: Registers cache for suspend/resume */ static struct rzg2l_irqc_priv { @@ -81,6 +89,7 @@ static struct rzg2l_irqc_priv { const struct irq_chip *irqchip; struct irq_fwspec *fwspec; raw_spinlock_t lock; + const struct rzg2l_hw_info *info; struct rzg2l_irqc_reg_cache cache; } *rzg2l_irqc_data; =20 @@ -136,7 +145,7 @@ static void rzg2l_irqc_eoi(struct irq_data *d) raw_spin_lock(&priv->lock); if (hw_irq >=3D IRQC_IRQ_START && hw_irq <=3D IRQC_IRQ_COUNT) rzg2l_clear_irq_int(priv, hw_irq); - else if (hw_irq >=3D IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) + else if (hw_irq >=3D IRQC_TINT_START && hw_irq < priv->info->num_irq) rzg2l_clear_tint_int(priv, hw_irq); raw_spin_unlock(&priv->lock); irq_chip_eoi_parent(d); @@ -182,7 +191,7 @@ static void rzfive_irqc_mask(struct irq_data *d) raw_spin_lock(&priv->lock); if (hwirq >=3D IRQC_IRQ_START && hwirq <=3D IRQC_IRQ_COUNT) rzfive_irqc_mask_irq_interrupt(priv, hwirq); - else if (hwirq >=3D IRQC_TINT_START && hwirq < IRQC_NUM_IRQ) + else if (hwirq >=3D IRQC_TINT_START && hwirq < priv->info->num_irq) rzfive_irqc_mask_tint_interrupt(priv, hwirq); raw_spin_unlock(&priv->lock); irq_chip_mask_parent(d); @@ -196,7 +205,7 @@ static void rzfive_irqc_unmask(struct irq_data *d) raw_spin_lock(&priv->lock); if (hwirq >=3D IRQC_IRQ_START && hwirq <=3D IRQC_IRQ_COUNT) rzfive_irqc_unmask_irq_interrupt(priv, hwirq); - else if (hwirq >=3D IRQC_TINT_START && hwirq < IRQC_NUM_IRQ) + else if (hwirq >=3D IRQC_TINT_START && hwirq < priv->info->num_irq) rzfive_irqc_unmask_tint_interrupt(priv, hwirq); raw_spin_unlock(&priv->lock); irq_chip_unmask_parent(d); @@ -207,7 +216,7 @@ static void rzfive_tint_irq_endisable(struct irq_data *= d, bool enable) struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hwirq =3D irqd_to_hwirq(d); =20 - if (hwirq >=3D IRQC_TINT_START && hwirq < IRQC_NUM_IRQ) { + if (hwirq >=3D IRQC_TINT_START && hwirq < priv->info->num_irq) { u32 offset =3D hwirq - IRQC_TINT_START; u32 tssr_offset =3D TSSR_OFFSET(offset); u8 tssr_index =3D TSSR_INDEX(offset); @@ -249,9 +258,10 @@ static void rzfive_irqc_irq_enable(struct irq_data *d) =20 static void rzg2l_tint_irq_endisable(struct irq_data *d, bool enable) { + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hw_irq =3D irqd_to_hwirq(d); =20 - if (hw_irq >=3D IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) { + if (hw_irq >=3D IRQC_TINT_START && hw_irq < priv->info->num_irq) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); u32 offset =3D hw_irq - IRQC_TINT_START; u32 tssr_offset =3D TSSR_OFFSET(offset); @@ -385,12 +395,13 @@ static int rzg2l_tint_set_edge(struct irq_data *d, un= signed int type) =20 static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type) { + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hw_irq =3D irqd_to_hwirq(d); int ret =3D -EINVAL; =20 if (hw_irq >=3D IRQC_IRQ_START && hw_irq <=3D IRQC_IRQ_COUNT) ret =3D rzg2l_irq_set_type(d, type); - else if (hw_irq >=3D IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) + else if (hw_irq >=3D IRQC_TINT_START && hw_irq < priv->info->num_irq) ret =3D rzg2l_tint_set_edge(d, type); if (ret) return ret; @@ -496,7 +507,7 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain, = unsigned int virq, return -EINVAL; } =20 - if (hwirq > (IRQC_NUM_IRQ - 1)) + if (hwirq > (priv->info->num_irq - 1)) return -EINVAL; =20 ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, priv->irqchip, @@ -520,7 +531,7 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irq= c_priv *priv, unsigned int i; int ret; =20 - for (i =3D 0; i < IRQC_NUM_IRQ; i++) { + for (i =3D 0; i < priv->info->num_irq; i++) { ret =3D of_irq_parse_one(np, i, &map); if (ret) return ret; @@ -532,7 +543,8 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irq= c_priv *priv, } =20 static int rzg2l_irqc_common_probe(struct platform_device *pdev, struct de= vice_node *parent, - const struct irq_chip *irq_chip) + const struct irq_chip *irq_chip, + const struct rzg2l_hw_info *info) { struct irq_domain *irq_domain, *parent_domain; struct device_node *node =3D pdev->dev.of_node; @@ -554,7 +566,9 @@ static int rzg2l_irqc_common_probe(struct platform_devi= ce *pdev, struct device_n if (IS_ERR(rzg2l_irqc_data->base)) return PTR_ERR(rzg2l_irqc_data->base); =20 - rzg2l_irqc_data->fwspec =3D devm_kcalloc(&pdev->dev, IRQC_NUM_IRQ, + rzg2l_irqc_data->info =3D info; + + rzg2l_irqc_data->fwspec =3D devm_kcalloc(&pdev->dev, info->num_irq, sizeof(*rzg2l_irqc_data->fwspec), GFP_KERNEL); if (!rzg2l_irqc_data->fwspec) return -ENOMEM; @@ -579,7 +593,7 @@ static int rzg2l_irqc_common_probe(struct platform_devi= ce *pdev, struct device_n =20 raw_spin_lock_init(&rzg2l_irqc_data->lock); =20 - irq_domain =3D irq_domain_create_hierarchy(parent_domain, 0, IRQC_NUM_IRQ= , dev_fwnode(dev), + irq_domain =3D irq_domain_create_hierarchy(parent_domain, 0, info->num_ir= q, dev_fwnode(dev), &rzg2l_irqc_domain_ops, rzg2l_irqc_data); if (!irq_domain) { pm_runtime_put(dev); @@ -591,14 +605,18 @@ static int rzg2l_irqc_common_probe(struct platform_de= vice *pdev, struct device_n return 0; } =20 +static const struct rzg2l_hw_info rzg2l_hw_params =3D { + .num_irq =3D IRQC_IRQ_START + IRQC_IRQ_COUNT + IRQC_TINT_COUNT, +}; + static int rzg2l_irqc_probe(struct platform_device *pdev, struct device_no= de *parent) { - return rzg2l_irqc_common_probe(pdev, parent, &rzg2l_irqc_chip); + return rzg2l_irqc_common_probe(pdev, parent, &rzg2l_irqc_chip, &rzg2l_hw_= params); } =20 static int rzfive_irqc_probe(struct platform_device *pdev, struct device_n= ode *parent) { - return rzg2l_irqc_common_probe(pdev, parent, &rzfive_irqc_chip); + return rzg2l_irqc_common_probe(pdev, parent, &rzfive_irqc_chip, &rzg2l_hw= _params); } =20 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzg2l_irqc) --=20 2.43.0