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Wed, 04 Feb 2026 10:06:35 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Lad Prabhakar , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH v2 2/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3L SoC Date: Wed, 4 Feb 2026 18:06:18 +0000 Message-ID: <20260204180632.249139-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260204180632.249139-1-biju.das.jz@bp.renesas.com> References: <20260204180632.249139-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Document RZ/G3L (R9A08G046) IRQC bindings. The IRQC block on RZ/G3L SoC is almost identical to one found on the RZ/G3S SoC with the difference like it support more External IRQs, GPT Error Interrupts and also has additional registers for GPT/MTU IRQ selection, shared IRQ selection between external IRQ and TINT. Hence new generic compatible string "renesas,r9a08g046-irqc" is added for RZ/G3L SoC. Signed-off-by: Biju Das --- v1->v2: * Simplified the binding using pattern --- .../renesas,rzg2l-irqc.yaml | 42 +++++++++++++++---- 1 file changed, 35 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas= ,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/r= enesas,rzg2l-irqc.yaml index a0b57d808639..311741122b05 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-= irqc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-= irqc.yaml @@ -30,7 +30,10 @@ properties: - renesas,r9a08g045-irqc # RZ/G3S - const: renesas,rzg2l-irqc =20 - - const: renesas,r9a07g043f-irqc # RZ/Five + - items: + - enum: + - renesas,r9a07g043f-irqc # RZ/Five + - renesas,r9a08g046-irqc # RZ/G3L =20 '#interrupt-cells': description: The first cell should contain a macro RZG2L_{NMI,IRQX} in= cluded in the @@ -48,17 +51,17 @@ properties: =20 interrupts: minItems: 45 - maxItems: 48 + maxItems: 61 =20 interrupt-names: minItems: 45 - maxItems: 48 + maxItems: 61 items: oneOf: - description: NMI interrupt const: nmi - description: External IRQ interrupt - pattern: '^irq([0-7])$' + pattern: '^irq([0-9]|1[0-5])$' - description: GPIO interrupt pattern: '^tint([0-9]|1[0-9]|2[0-9]|3[0-1])$' - description: Bus error interrupt @@ -75,6 +78,8 @@ properties: const: ec7tie2-1 - description: ECCRAM1 error overflow interrupt const: ec7tiovf-1 + - description: Integrated GPT Error interrupt + pattern: '^ovfunf([0-7])$' =20 clocks: maxItems: 2 @@ -106,6 +111,22 @@ required: allOf: - $ref: /schemas/interrupt-controller.yaml# =20 + - if: + properties: + compatible: + contains: + enum: + - renesas,r9a07g043f-irqc + - renesas,r9a07g043u-irqc + - renesas,r9a07g044-irqc + - renesas,r9a07g054-irqc + then: + properties: + interrupts: + maxItems: 48 + interrupt-names: + maxItems: 48 + - if: properties: compatible: @@ -118,12 +139,19 @@ allOf: maxItems: 45 interrupt-names: maxItems: 45 - else: + + - if: + properties: + compatible: + contains: + enum: + - renesas,r9a08g046-irqc + then: properties: interrupts: - minItems: 48 + maxItems: 61 interrupt-names: - minItems: 48 + maxItems: 61 =20 unevaluatedProperties: false =20 --=20 2.43.0