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[188.152.100.94]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4830ec10011sm38044465e9.0.2026.02.04.09.05.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Feb 2026 09:05:31 -0800 (PST) From: Stefano Radaelli X-Google-Original-From: Stefano Radaelli To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: kernel@pengutronix.de, festevam@gmail.com, alexander.stein@ew.tq-group.com, dario.binacchi@amarulasolutions.com, primoz.fiser@norik.com, Markus.Niebel@tq-group.com, y.moog@phytec.de, josua@solid-run.com, francesco.dolcini@toradex.com, maudspierings@gocontroll.com, Stefano Radaelli Subject: [PATCH v1 1/3] dt-bindings: arm: fsl: add Variscite DART-MX91 Boards Date: Wed, 4 Feb 2026 18:03:54 +0100 Message-ID: <20260204170356.35169-2-stefano.r@variscite.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260204170356.35169-1-stefano.r@variscite.com> References: <20260204170356.35169-1-stefano.r@variscite.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Stefano Radaelli Add DT compatible strings for Variscite DART-MX91 SoM and Variscite development carrier Board. Signed-off-by: Stefano Radaelli Acked-by: Conor Dooley --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 336669e16d7a..4c200a67600e 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1524,6 +1524,12 @@ properties: - const: phytec,imx93-phycore-som # phyCORE-i.MX93 SoM - const: fsl,imx93 =20 + - description: Variscite DART-MX91 based boards + items: + - const: variscite,var-dart-mx91-sonata # Variscite DART-MX91 on= Sonata Development Board + - const: variscite,var-dart-mx91 # Variscite DART-MX91 SOM + - const: fsl,imx91 + - description: Variscite VAR-SOM-MX93 based boards items: - const: variscite,var-som-mx93-symphony --=20 2.47.3 From nobody Sun Feb 8 05:42:10 2026 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC81D349AED for ; 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[188.152.100.94]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4830ec10011sm38044465e9.0.2026.02.04.09.05.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Feb 2026 09:05:32 -0800 (PST) From: Stefano Radaelli X-Google-Original-From: Stefano Radaelli To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: kernel@pengutronix.de, festevam@gmail.com, alexander.stein@ew.tq-group.com, dario.binacchi@amarulasolutions.com, primoz.fiser@norik.com, Markus.Niebel@tq-group.com, y.moog@phytec.de, josua@solid-run.com, francesco.dolcini@toradex.com, maudspierings@gocontroll.com, Stefano Radaelli Subject: [PATCH v1 2/3] arm64: dts: freescale: Add support for Variscite DART-MX91 Date: Wed, 4 Feb 2026 18:03:55 +0100 Message-ID: <20260204170356.35169-3-stefano.r@variscite.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260204170356.35169-1-stefano.r@variscite.com> References: <20260204170356.35169-1-stefano.r@variscite.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Stefano Radaelli Add device tree support for the Variscite DART-MX91 system on module. This SOM is designed to be used with various carrier boards. The module includes: - NXP i.MX91 MPU processor - Up to 2GB of LPDDR4 memory - Up to 128GB of eMMC storage memory - Integrated 10/100/1000 Mbps Ethernet Transceiver - Codec audio WM8904 - WIFI6 dual-band 802.11ax/ac/a/b/g/n with optional 802.15.4 and Bluetooth Only SOM-specific peripherals are enabled by default. Carrier board specific interfaces are left disabled to be enabled in the respective carrier board device trees. Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-91/dart-mx91/ Signed-off-by: Stefano Radaelli --- .../boot/dts/freescale/imx91-var-dart.dtsi | 468 ++++++++++++++++++ 1 file changed, 468 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx91-var-dart.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx91-var-dart.dtsi b/arch/arm64= /boot/dts/freescale/imx91-var-dart.dtsi new file mode 100644 index 000000000000..b10425b3198d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-var-dart.dtsi @@ -0,0 +1,468 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Common dtsi for Variscite DART-MX91 + * + * Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-91/dart-mx= 91/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include +#include +#include "imx91.dtsi" + +/ { + model =3D "Variscite DART-MX91 Module"; + compatible =3D "variscite,var-dart-mx91", "fsl,imx91"; + + sound-wm8904 { + compatible =3D "simple-audio-card"; + simple-audio-card,bitclock-master =3D <&codec_dai>; + simple-audio-card,format =3D "i2s"; + simple-audio-card,frame-master =3D <&codec_dai>; + simple-audio-card,mclk-fs =3D <256>; + simple-audio-card,name =3D "wm8904-audio"; + simple-audio-card,routing =3D + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack"; + simple-audio-card,widgets =3D + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai =3D <&wm8904>; + }; + + simple-audio-card,cpu { + sound-dai =3D <&sai1>; + }; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + post-power-on-delay-ms =3D <100>; + power-off-delay-us =3D <10000>; + reset-gpios =3D <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ + <&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ + }; +}; + +&eqos { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&pinctrl_eqos>; + pinctrl-1 =3D <&pinctrl_eqos_sleep>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode =3D "rgmii"; + phy-handle =3D <ðphy0>; + snps,clk-csr =3D <5>; + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy0: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0>; + reset-gpios =3D <&gpio1 7 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <15000>; + reset-deassert-us =3D <100000>; + + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + led@0 { + reg =3D <0>; + color =3D ; + function =3D LED_FUNCTION_LAN; + linux,default-trigger =3D "netdev"; + }; + + led@1 { + reg =3D <1>; + color =3D ; + function =3D LED_FUNCTION_LAN; + linux,default-trigger =3D "netdev"; + }; + }; + }; + }; +}; + +&lpi2c3 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default", "sleep", "gpio"; + pinctrl-0 =3D <&pinctrl_lpi2c3>; + pinctrl-1 =3D <&pinctrl_lpi2c3_gpio>; + pinctrl-2 =3D <&pinctrl_lpi2c3_gpio>; + scl-gpios =3D <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios =3D <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status =3D "okay"; + + pmic@25 { + compatible =3D "nxp,pca9451a"; + reg =3D <0x25>; + + regulators { + buck1: BUCK1 { + regulator-name =3D "BUCK1"; + regulator-min-microvolt =3D <650000>; + regulator-max-microvolt =3D <2237500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <3125>; + }; + + buck2: BUCK2 { + regulator-name =3D "BUCK2"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <3125>; + }; + + buck4: BUCK4{ + regulator-name =3D "BUCK4"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name =3D "BUCK5"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name =3D "BUCK6"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name =3D "LDO1"; + regulator-min-microvolt =3D <1600000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name =3D "LDO4"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name =3D "LDO5"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + wm8904: audio-codec@1a { + compatible =3D "wlf,wm8904"; + reg =3D <0x1a>; + #sound-dai-cells =3D <0>; + clocks =3D <&clk IMX93_CLK_SAI1_GATE>; + clock-names =3D "mclk"; + AVDD-supply =3D <&buck5>; + CPVDD-supply =3D <&buck5>; + DBVDD-supply =3D <&buck4>; + DCVDD-supply =3D <&buck5>; + MICVDD-supply =3D <&buck5>; + wlf,drc-cfg-names =3D "default", "peaklimiter", "tradition", + "soft", "music"; + /* + * Config registers per name, respectively: + * KNEE_IP =3D 0, KNEE_OP =3D 0, HI_COMP =3D 1, LO_COMP =3D 1 + * KNEE_IP =3D -24, KNEE_OP =3D -6, HI_COMP =3D 1/4, LO_COMP =3D 1 + * KNEE_IP =3D -42, KNEE_OP =3D -3, HI_COMP =3D 0, LO_COMP =3D 1 + * KNEE_IP =3D -45, KNEE_OP =3D -9, HI_COMP =3D 1/8, LO_COMP =3D 1 + * KNEE_IP =3D -30, KNEE_OP =3D -10.5, HI_COMP =3D 1/4, LO_COMP =3D 1 + */ + wlf,drc-cfg-regs =3D /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, + /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, + /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, + /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; + /* GPIO1 =3D DMIC_CLK, don't touch others */ + wlf,gpio-cfg =3D <0x0018>, <0xffff>, <0xffff>, <0xffff>; + /* DMIC is connected to IN1L */ + wlf,in1l-as-dmicdat1; + }; +}; + +/* BT module */ +&lpuart5 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart5>, <&pinctrl_bt>; + uart-has-rtscts; + status =3D "okay"; + + bluetooth { + compatible =3D "nxp,88w8987-bt"; + }; +}; + +&sai1 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&pinctrl_sai1>; + pinctrl-1 =3D <&pinctrl_sai1_sleep>; + assigned-clocks =3D <&clk IMX93_CLK_SAI1>; + assigned-clock-parents =3D <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates =3D <12288000>; + #sound-dai-cells =3D <0>; + fsl,sai-mclk-direction-output; + status =3D "okay"; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc1>; + pinctrl-1 =3D <&pinctrl_usdhc1_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc1_200mhz>; + bus-width =3D <8>; + non-removable; + status =3D "okay"; +}; + +/* WiFi */ +&usdhc3 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 =3D <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>; + pinctrl-1 =3D <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>; + pinctrl-2 =3D <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>; + pinctrl-3 =3D <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>; + mmc-pwrseq =3D <&wifi_pwrseq>; + keep-power-in-suspend; + bus-width =3D <4>; + non-removable; + wakeup-source; + status =3D "okay"; +}; + +&wdog3 { + status =3D "okay"; +}; + +&iomuxc { + pinctrl_bt: btgrp { + fsl,pins =3D < + MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x51e + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins =3D < + MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e + MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe + MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e + MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe + MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + MX91_PAD_UART2_TXD__GPIO1_IO7 0x51e + >; + }; + + pinctrl_eqos_sleep: eqos-sleepgrp { + fsl,pins =3D < + MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e + MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e + MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e + MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e + MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e + MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e + MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e + MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e + MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e + MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e + MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e + MX91_PAD_ENET1_TD3__GPIO4_IO2 0x31e + MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e + MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins =3D < + MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c3_gpio: lpi2c3gpiogrp { + fsl,pins =3D < + MX91_PAD_GPIO_IO28__GPIO2_IO28 0x40000b9e + MX91_PAD_GPIO_IO29__GPIO2_IO29 0x40000b9e + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins =3D < + MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e + MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e + MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x31e + MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x31e + MX91_PAD_I2C2_SDA__SAI1_RX_BCLK 0x31e + MX91_PAD_I2C2_SCL__SAI1_RX_SYNC 0x31e + MX91_PAD_UART2_RXD__SAI1_MCLK 0x31e + >; + }; + + pinctrl_sai1_sleep: sai1-sleepgrp { + fsl,pins =3D < + MX91_PAD_SAI1_TXC__GPIO1_IO12 0x31e + MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x31e + MX91_PAD_SAI1_TXD0__GPIO1_IO13 0x31e + MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x31e + MX91_PAD_UART2_RXD__GPIO1_IO6 0x31e + MX91_PAD_I2C2_SDA__GPIO1_IO3 0x31e + MX91_PAD_I2C2_SCL__GPIO1_IO2 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins =3D < + MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX91_PAD_DAP_TDI__LPUART5_RX 0x31e + MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582 + MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382 + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382 + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382 + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382 + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382 + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382 + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382 + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382 + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382 + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins =3D < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e + MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins =3D < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins =3D < + MX91_PAD_SD3_CLK__USDHC3_CLK 0x1582 + MX91_PAD_SD3_CMD__USDHC3_CMD 0x1382 + MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x1382 + MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x1382 + MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x1382 + MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x1382 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins =3D < + MX91_PAD_SD3_CLK__USDHC3_CLK 0x158e + MX91_PAD_SD3_CMD__USDHC3_CMD 0x138e + MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins =3D < + MX91_PAD_SD3_CLK__USDHC3_CLK 0x15fe + MX91_PAD_SD3_CMD__USDHC3_CMD 0x13fe + MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe + MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe + MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe + MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe + >; + }; + + pinctrl_usdhc3_sleep: usdhc3-sleepgrp { + fsl,pins =3D < + MX91_PAD_SD3_CLK__GPIO3_IO20 0x31e + MX91_PAD_SD3_CMD__GPIO3_IO21 0x31e + MX91_PAD_SD3_DATA0__GPIO3_IO22 0x31e + MX91_PAD_SD3_DATA1__GPIO3_IO23 0x31e + MX91_PAD_SD3_DATA2__GPIO3_IO24 0x31e + MX91_PAD_SD3_DATA3__GPIO3_IO25 0x31e + >; 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[188.152.100.94]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4830ec10011sm38044465e9.0.2026.02.04.09.05.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Feb 2026 09:05:33 -0800 (PST) From: Stefano Radaelli X-Google-Original-From: Stefano Radaelli To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: kernel@pengutronix.de, festevam@gmail.com, alexander.stein@ew.tq-group.com, dario.binacchi@amarulasolutions.com, primoz.fiser@norik.com, Markus.Niebel@tq-group.com, y.moog@phytec.de, josua@solid-run.com, francesco.dolcini@toradex.com, maudspierings@gocontroll.com, Stefano Radaelli Subject: [PATCH v1 3/3] arm64: dts: imx91-var-dart: Add support for Variscite Sonata board Date: Wed, 4 Feb 2026 18:03:56 +0100 Message-ID: <20260204170356.35169-4-stefano.r@variscite.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260204170356.35169-1-stefano.r@variscite.com> References: <20260204170356.35169-1-stefano.r@variscite.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Stefano Radaelli Add device tree support for the Variscite Sonata carrier board with the DART-MX91 system on module. The Sonata board includes - uSD Card support - USB ports and OTG - Additional Gigabit Ethernet interface - Uart interfaces - GPIO Expanders - RTC module - TPM module Link: https://variscite.com/carrier-boards/sonata-board/ Signed-off-by: Stefano Radaelli --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx91-var-dart-sonata.dts | 498 ++++++++++++++++++ 2 files changed, 499 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index f30d3fd724d0..839d98bdd2a1 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -370,6 +370,7 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx91-11x11-evk.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx91-phyboard-segin.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx91-tqma9131-mba91xxca.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx91-var-dart-sonata.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-9x9-qsb.dtb =20 imx93-9x9-qsb-i3c-dtbs +=3D imx93-9x9-qsb.dtb imx93-9x9-qsb-i3c.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts b/arch= /arm64/boot/dts/freescale/imx91-var-dart-sonata.dts new file mode 100644 index 000000000000..8e4bcebfdda5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts @@ -0,0 +1,498 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Variscite Sonata carrier board for DART-MX91 + * + * Link: https://variscite.com/carrier-boards/sonata-board/ + * + * Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include "imx91-var-dart.dtsi" + +/ { + model =3D "Variscite DART-MX91 on Sonata-Board"; + compatible =3D "variscite,var-dart-mx91-sonata", + "variscite,var-dart-mx91", + "fsl,imx91"; + + aliases { + ethernet0 =3D &eqos; + ethernet1 =3D &fec; + gpio0 =3D &gpio1; + gpio1 =3D &gpio2; + gpio2 =3D &gpio3; + i2c0 =3D &lpi2c1; + i2c1 =3D &lpi2c2; + i2c2 =3D &lpi2c3; + mmc0 =3D &usdhc1; + mmc1 =3D &usdhc2; + serial0 =3D &lpuart1; + serial1 =3D &lpuart2; + serial2 =3D &lpuart3; + serial3 =3D &lpuart4; + serial4 =3D &lpuart5; + serial5 =3D &lpuart6; + }; + + chosen { + stdout-path =3D &lpuart1; + }; + + gpio-leds { + compatible =3D "gpio-leds"; + + led-emmc { + label =3D "eMMC"; + gpios =3D <&pca6408_2 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "mmc0"; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + button-back { + label =3D "Back"; + linux,code =3D ; + gpios =3D <&pca6408_1 7 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-up { + label =3D "Up"; + linux,code =3D ; + gpios =3D <&pca6408_1 5 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-home { + label =3D "Home"; + linux,code =3D ; + gpios =3D <&pca6408_1 4 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-down { + label =3D "Down"; + linux,code =3D ; + gpios =3D <&pca6408_1 6 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + reg_usdhc2_vmmc: regulator-vmmc-usdhc2 { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_usdhc2_vmmc>; + regulator-name =3D "VDD_SD2_3V3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&gpio4 28 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us =3D <20000>; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible =3D "regulator-fixed"; + regulator-name =3D "vref_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + reserved-memory { + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + + linux,cma { + compatible =3D "shared-dma-pool"; + alloc-ranges =3D <0 0x80000000 0 0x40000000>; + reusable; + size =3D <0 0x10000000>; + linux,cma-default; + }; + }; +}; + +&adc1 { + vref-supply =3D <®_vref_1v8>; + status =3D "okay"; +}; + +/* Use external instead of internal RTC */ +&bbnsm_rtc { + status =3D "disabled"; +}; + +&eqos { + mdio { + ethphy1: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + reset-gpios =3D <&pca6408_2 0 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <15000>; + reset-deassert-us =3D <100000>; + + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + led@0 { + reg =3D <0>; + color =3D ; + function =3D LED_FUNCTION_LAN; + linux,default-trigger =3D "netdev"; + }; + + led@1 { + reg =3D <1>; + color =3D ; + function =3D LED_FUNCTION_LAN; + linux,default-trigger =3D "netdev"; + }; + }; + }; + }; +}; + +&fec { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&pinctrl_fec>; + pinctrl-1 =3D <&pinctrl_fec_sleep>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode =3D "rgmii"; + phy-handle =3D <ðphy1>; + status =3D "okay"; +}; + +&flexcan1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan1>; + status =3D "okay"; +}; + +&lpi2c1 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default", "sleep", "gpio"; + pinctrl-0 =3D <&pinctrl_lpi2c1>; + pinctrl-1 =3D <&pinctrl_lpi2c1_gpio>; + pinctrl-2 =3D <&pinctrl_lpi2c1_gpio>; + scl-gpios =3D <&gpio1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios =3D <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status =3D "okay"; + + pca6408_1: gpio@20 { + compatible =3D "nxp,pcal6408"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <10 IRQ_TYPE_LEVEL_LOW>; + }; + + pca6408_2: gpio@21 { + compatible =3D "nxp,pcal6408"; + reg =3D <0x21>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <10 IRQ_TYPE_LEVEL_LOW>; + }; + + pca9534: gpio@22 { + compatible =3D "nxp,pca9534"; + reg =3D <0x22>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <10 IRQ_TYPE_LEVEL_LOW>; + }; + + st33ktpm2xi2c: tpm@2e { + compatible =3D "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; + reg =3D <0x2e>; + }; + + /* Capacitive touch controller */ + ft5x06_ts: touchscreen@38 { + compatible =3D "edt,edt-ft5206"; + reg =3D <0x38>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_captouch>; + reset-gpios =3D <&pca6408_2 4 GPIO_ACTIVE_LOW>; + interrupt-parent =3D <&gpio3>; + interrupts =3D <27 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x =3D <800>; + touchscreen-size-y =3D <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + wakeup-source; + }; + + /* USB Type-C Controller */ + typec@3d { + compatible =3D "nxp,ptn5150"; + reg =3D <0x3d>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_extcon>; + interrupt-parent =3D <&gpio4>; + interrupts =3D <29 IRQ_TYPE_LEVEL_HIGH>; + + port { + typec1_dr_sw: endpoint { + remote-endpoint =3D <&usb1_drd_sw>; + }; + }; + }; + + rtc@68 { + compatible =3D "dallas,ds1337"; + reg =3D <0x68>; + }; +}; + +/* Console (J10) */ +&lpuart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1>; + status =3D "okay"; +}; + +/* Header (J12.4, J12.6) */ +&lpuart6 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart6>; + status =3D "okay"; +}; + +&usbotg1 { + dr_mode =3D "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control =3D <3>; + samsung,picophy-dc-vol-level-adjust =3D <7>; + status =3D "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint =3D <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + disable-over-current; + dr_mode =3D "host"; + status =3D "okay"; +}; + +/* SD */ +&usdhc2 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 =3D <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 =3D <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 =3D <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; + cd-gpios =3D <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply =3D <®_usdhc2_vmmc>; + bus-width =3D <4>; + no-sdio; + no-mmc; + status =3D "okay"; +}; + +&iomuxc { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins =3D < + /* GPIO Expanders shared IRQ */ + MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e + >; + }; + + pinctrl_captouch: captouchgrp { + fsl,pins =3D < + MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x31e + >; + }; + + pinctrl_extcon: extcongrp { + fsl,pins =3D < + MX91_PAD_CCM_CLKO4__GPIO4_IO29 0x31e + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins =3D < + MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x57e + MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x57e + MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x57e + MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x37e + MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x5fe + MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x57e + MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x57e + MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x57e + MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x57e + MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x57e + MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x5fe + MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_fec_sleep: fecsleepgrp { + fsl,pins =3D < + MX91_PAD_ENET2_RD0__GPIO4_IO24 0x51e + MX91_PAD_ENET2_RD1__GPIO4_IO25 0x51e + MX91_PAD_ENET2_RD2__GPIO4_IO26 0x51e + MX91_PAD_ENET2_RD3__GPIO4_IO27 0x31e + MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e + MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e + MX91_PAD_ENET2_TD0__GPIO4_IO19 0x51e + MX91_PAD_ENET2_TD1__GPIO4_IO18 0x51e + MX91_PAD_ENET2_TD2__GPIO4_IO17 0x51e + MX91_PAD_ENET2_TD3__GPIO4_IO16 0x51e + MX91_PAD_ENET2_TXC__GPIO4_IO21 0x51e + MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins =3D < + MX91_PAD_PDM_CLK__CAN1_TX 0x139e + MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins =3D < + MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c1_gpio: lpi2c1-gpiogrp { + fsl,pins =3D < + MX91_PAD_I2C1_SCL__GPIO1_IO0 0x31e + MX91_PAD_I2C1_SDA__GPIO1_IO1 0x31e + >; + }; + + pinctrl_lpi2c7: lpi2c7grp { + fsl,pins =3D < + MX91_PAD_GPIO_IO07__LPI2C7_SCL 0x40000b9e + MX91_PAD_GPIO_IO06__LPI2C7_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c7_gpio: lpi2c7-gpiogrp { + fsl,pins =3D < + MX91_PAD_GPIO_IO07__GPIO2_IO7 0x31e + MX91_PAD_GPIO_IO06__GPIO2_IO6 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins =3D < + MX91_PAD_CCM_CLKO3__GPIO4_IO28 0x31e + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins =3D < + MX91_PAD_GPIO_IO02__GPIO2_IO2 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins =3D < + MX91_PAD_UART1_RXD__LPUART1_RX 0x31e + MX91_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins =3D < + MX91_PAD_GPIO_IO05__LPUART6_RX 0x31e + MX91_PAD_GPIO_IO04__LPUART6_TX 0x31e + >; + }; + + pinctrl_uart7: uart7grp { + fsl,pins =3D < + MX91_PAD_GPIO_IO09__LPUART7_RX 0x31e + MX91_PAD_GPIO_IO08__LPUART7_TX 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins =3D < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582 + MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382 + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382 + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382 + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382 + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382 + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins =3D < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins =3D < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_sleep: usdhc2sleepgrp { + fsl,pins =3D < + MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e + MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e + MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e + MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e + MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e + MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e + MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins =3D < + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e + >; + }; + + pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { + fsl,pins =3D < + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e + >; + }; +}; --=20 2.47.3