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Wed, 04 Feb 2026 03:56:56 -0800 (PST) From: Stanislav Zaikin To: devicetree@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-kernel@vger.kernel.org, Stanislav Zaikin Subject: [PATCH 1/2] dt-bindings: arm: qcom: Add SM7325 Xiaomi 12 Lite 5G (taoyao) Date: Wed, 4 Feb 2026 12:56:44 +0100 Message-ID: <20260204115645.1343750-2-zstaseg@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260204115645.1343750-1-zstaseg@gmail.com> References: <20260204115645.1343750-1-zstaseg@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Xiaomi 12 Lite 5G (xiaomi,taoyao) is a smartphone based on the SM7325 SoC. Signed-off-by: Stanislav Zaikin --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index d84bd3bca201..711cf3bba6e8 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -982,6 +982,7 @@ properties: - items: - enum: - nothing,spacewar + - xiaomi,taoyao - const: qcom,sm7325 =20 - items: --=20 2.51.0 From nobody Sat Feb 7 10:15:48 2026 Received: from mail-ej1-f51.google.com (mail-ej1-f51.google.com [209.85.218.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A7C8C3ECBE0 for ; Wed, 4 Feb 2026 11:56:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Wed, 04 Feb 2026 03:56:57 -0800 (PST) Received: from workstation.home ([178.228.161.30]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8e9feefffbsm116457666b.37.2026.02.04.03.56.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Feb 2026 03:56:57 -0800 (PST) From: Stanislav Zaikin To: devicetree@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-kernel@vger.kernel.org, Stanislav Zaikin Subject: [PATCH 2/2] arm64: dts: qcom: Add Xiaomi 12 Lite 5G (taoyao) DTS Date: Wed, 4 Feb 2026 12:56:45 +0100 Message-ID: <20260204115645.1343750-3-zstaseg@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260204115645.1343750-1-zstaseg@gmail.com> References: <20260204115645.1343750-1-zstaseg@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Xiaomi 12 Lite 5G is a handset released in 2022 This commit has the following features working: - Display (with simple fb) - Touchscreen - UFS - Power and volume buttons - Pinctrl - RPM Regulators - Remoteprocs - wifi, bluetooth - USB (Device Mode) Signed-off-by: Stanislav Zaikin --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sm7325-xiaomi-taoyao.dts | 866 ++++++++++++++++++ 2 files changed, 867 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm7325-xiaomi-taoyao.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 6f34d5ed331c..61618da3f68c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -280,6 +280,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D sm7125-xiaomi-curtana.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm7125-xiaomi-joyeuse.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm7225-fairphone-fp4.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm7325-nothing-spacewar.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sm7325-xiaomi-taoyao.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8150-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8150-microsoft-surface-duo.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8150-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/sm7325-xiaomi-taoyao.dts b/arch/arm64= /boot/dts/qcom/sm7325-xiaomi-taoyao.dts new file mode 100644 index 000000000000..b3d2c8d3022e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm7325-xiaomi-taoyao.dts @@ -0,0 +1,866 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2025, Stanislav Zaikin + */ + +/dts-v1/; + +/* PM7250B is configured to use SID8/9 */ +#define PM7250B_SID 8 +#define PM7250B_SID1 9 + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sm7325.dtsi" +#include "pm7325.dtsi" +#include "pm7250b.dtsi" /* PM7250B */ +#include "pm8350c.dtsi" /* PM7350C */ +#include "pmk8350.dtsi" /* PMK7325 */ + +/* The following reserved memory regions have different addresses or sizes= */ +/delete-node/ &adsp_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &rmtfs_mem; + +/ { + model =3D "Xiaomi 12 Lite 5G"; + compatible =3D "xiaomi,taoyao", "qcom,sm7325"; + chassis-type =3D "handset"; + + aliases { + serial0 =3D &uart5; + serial1 =3D &uart7; + }; + + chosen { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + framebuffer0: framebuffer@e1000000 { + compatible =3D "simple-framebuffer"; + reg =3D <0x0 0xe1000000 0x0 (1080 * 2400 * 4)>; + width =3D <1080>; + height =3D <2400>; + stride =3D <(1080 * 4)>; + format =3D "a8r8g8b8"; + + clocks =3D <&gcc GCC_DISP_HF_AXI_CLK>; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + pinctrl-0 =3D <&key_vol_up>; + pinctrl-names =3D "default"; + + key-volume-up { + label =3D "Volume Up"; + gpios =3D <&pm7325_gpios 6 GPIO_ACTIVE_LOW>; + linux,code =3D ; + }; + }; + + pmic-glink { + compatible =3D "qcom,sm7325-pmic-glink", + "qcom,qcm6490-pmic-glink", + "qcom,pmic-glink"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + orientation-gpios =3D <&tlmm 140 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible =3D "usb-c-connector"; + reg =3D <0>; + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint =3D <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg =3D <1>; + + pmic_glink_sbu: endpoint { + remote-endpoint =3D <&fsa4480_sbu_mux>; + }; + }; + }; + }; + }; + + vreg_oled_dvdd: regulator-oled-dvdd { + compatible =3D "regulator-fixed"; + regulator-name =3D "oled_dvdd"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + gpio =3D <&tlmm 46 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply =3D <&vreg_s1b_1p856>; + regulator-boot-on; + }; + + // S2B is really ebi.lvl but it's there for supply map completeness sake. + vreg_s2b_0p7: regulator-smpa3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg_s2b_0p7"; + + regulator-min-microvolt =3D <700000>; + regulator-max-microvolt =3D <700000>; + regulator-always-on; + vin-supply =3D <&vph_pwr>; + }; + + vph_pwr: regulator-vph-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + }; + + reserved-memory { + cdsp_secure_heap_mem: cdsp-secure-heap@81800000 { + reg =3D <0x0 0x81800000 0x0 0x1e00000>; + no-map; + }; + + camera_mem: camera@86200000 { + reg =3D <0x0 0x86200000 0x0 0x500000>; + no-map; + }; + + adsp_mem: adsp@86700000 { + reg =3D <0x0 0x86700000 0x0 0x4000000>; + no-map; + }; + + /* Mainline video_mem is downstream cvp_mem */ + real_video_mem: video@8ad00000 { + reg =3D <0x0 0x8ad00000 0x0 0x500000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi@8b710000 { + reg =3D <0x0 0x8b710000 0x0 0xa000>; + no-map; + }; + + cdsp_mem: cdsp@9c700000 { + reg =3D <0x0 0x9c700000 0x0 0x1e00000>; + no-map; + }; + + ramoops@a9000000 { + compatible =3D "ramoops"; + reg =3D <0x0 0xa9000000 0x0 0x200000>; + pmsg-size =3D <0x200000>; + mem-type =3D <0x02>; + }; + + removed_mem: removed@c0000000 { + reg =3D <0x0 0xc0000000 0x0 0x6800000>; + no-map; + }; + + pil_trustedvm_mem: pil-trustedvm-region@d0800000 { + reg =3D <0x0 0xd0800000 0x0 0x76f7000>; + no-map; + }; + + qrtr_shmem: qrtr-shmem@d7ef7000 { + reg =3D <0x0 0xd7ef7000 0x0 0x9000>; + no-map; + }; + + neuron_block_0_mem: neuron-block@d7f00000 { + reg =3D <0x0 0xd7f00000 0x0 0x80000>; + no-map; + }; + + neuron_block_1_mem: neuron-block@d7f80000 { + reg =3D <0x0 0xd7f80000 0x0 0x80000>; + no-map; + }; + + framebuffer@e1000000 { + reg =3D <0x0 0xe1000000 0x0 (1080 * 2400 * 4)>; + no-map; + }; + + rmtfs_mem: rmtfs@ef500000 { + compatible =3D "qcom,rmtfs-mem"; + reg =3D <0x0 0xe7d00000 0x0 0x280000>; + no-map; + + qcom,client-id =3D <1>; + qcom,vmid =3D , + ; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pm7325-rpmh-regulators"; + qcom,pmic-id =3D "b"; + + vdd-s1-supply =3D <&vph_pwr>; + vdd-s2-supply =3D <&vph_pwr>; + vdd-s7-supply =3D <&vph_pwr>; + vdd-s8-supply =3D <&vph_pwr>; + + vdd-l1-l4-l12-l15-supply =3D <&vreg_s7b_0p952>; + vdd-l2-l7-supply =3D <&vreg_bob>; + vdd-l3-supply =3D <&vreg_s2b_0p7>; + vdd-l5-supply =3D <&vreg_s2b_0p7>; + vdd-l6-l9-l10-supply =3D <&vreg_s8b_1p256>; + vdd-l8-supply =3D <&vreg_s7b_0p952>; + vdd-l11-l17-l18-l19-supply =3D <&vreg_s1b_1p856>; + vdd-l13-supply =3D <&vreg_s7b_0p952>; + vdd-l14-l16-supply =3D <&vreg_s8b_1p256>; + + /* + * S2, L4-L5 are ARCs: + * S2 - ebi.lvl, + * L4 - lmx.lvl, + * L5 - lcx.lvl. + * + * L10 are unused. + */ + + vreg_s1b_1p856: smps1 { + regulator-name =3D "vreg_s1b_1p856"; + regulator-min-microvolt =3D <1840000>; + regulator-max-microvolt =3D <2040000>; + }; + + vreg_s7b_0p952: smps7 { + regulator-name =3D "vreg_s7b_0p952"; + regulator-min-microvolt =3D <535000>; + regulator-max-microvolt =3D <1120000>; + }; + + vreg_s8b_1p256: smps8 { + regulator-name =3D "vreg_s8b_1p256"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1500000>; + regulator-initial-mode =3D ; + }; + + vreg_l1b_0p912: ldo1 { + regulator-name =3D "vreg_l1b_0p912"; + regulator-min-microvolt =3D <825000>; + regulator-max-microvolt =3D <925000>; + regulator-initial-mode =3D ; + }; + + vreg_l2b_3p072: ldo2 { + regulator-name =3D "vreg_l2b_3p072"; + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + }; + + vreg_l3b_0p6: ldo3 { + regulator-name =3D "vreg_l3b_0p6"; + regulator-min-microvolt =3D <312000>; + regulator-max-microvolt =3D <910000>; + regulator-initial-mode =3D ; + }; + + vreg_l6b_1p2: ldo6 { + regulator-name =3D "vreg_l6b_1p2"; + regulator-min-microvolt =3D <1140000>; + regulator-max-microvolt =3D <1260000>; + regulator-initial-mode =3D ; + regulator-allowed-modes =3D ; + }; + + vreg_l7b_2p96: ldo7 { + regulator-name =3D "vreg_l7b_2p96"; + /* Constrained for UFS VCC, at least until UFS driver scales voltage */ + regulator-min-microvolt =3D <2952000>; + regulator-max-microvolt =3D <2952000>; + regulator-initial-mode =3D ; + }; + + vreg_l8b_0p904: ldo8 { + regulator-name =3D "vreg_l8b_0p904"; + regulator-min-microvolt =3D <870000>; + regulator-max-microvolt =3D <970000>; + regulator-initial-mode =3D ; + }; + + vreg_l9b_1p2: ldo9 { + regulator-name =3D "vreg_l9b_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1304000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l11b_1p776: ldo11 { + regulator-name =3D "vreg_l11b_1p776"; + regulator-min-microvolt =3D <1504000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + + vreg_l12b_0p8: ldo12 { + regulator-name =3D "vreg_l12b_0p8"; + regulator-min-microvolt =3D <751000>; + regulator-max-microvolt =3D <824000>; + regulator-initial-mode =3D ; + }; + + vreg_l13b_0p8: ldo13 { + regulator-name =3D "vreg_l13b_0p8"; + regulator-min-microvolt =3D <530000>; + regulator-max-microvolt =3D <824000>; + regulator-initial-mode =3D ; + }; + + vreg_l14b_1p2: ldo14 { + regulator-name =3D "vreg_l14b_1p2"; + regulator-min-microvolt =3D <1080000>; + regulator-max-microvolt =3D <1304000>; + regulator-initial-mode =3D ; + }; + + vreg_l15b_0p88: ldo15 { + regulator-name =3D "vreg_l15b_0p88"; + regulator-min-microvolt =3D <765000>; + regulator-max-microvolt =3D <1020000>; + regulator-initial-mode =3D ; + }; + + vreg_l16b_1p2: ldo16 { + regulator-name =3D "vreg_l16b_1p2"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1300000>; + regulator-initial-mode =3D ; + }; + + vreg_l17b_1p8: ldo17 { + regulator-name =3D "vreg_l17b_1p8"; + regulator-min-microvolt =3D <1700000>; + regulator-max-microvolt =3D <1900000>; + regulator-initial-mode =3D ; + }; + + vreg_l18b_1p8: ldo18 { + regulator-name =3D "vreg_l18b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + + vreg_l19b_1p8: ldo19 { + regulator-name =3D "vreg_l19b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id =3D "c"; + + vdd-s1-supply =3D <&vph_pwr>; + vdd-s2-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + vdd-s7-supply =3D <&vph_pwr>; + vdd-s9-supply =3D <&vph_pwr>; + vdd-s10-supply =3D <&vph_pwr>; + + vdd-l1-l12-supply =3D <&vreg_s1b_1p856>; + vdd-l2-l8-supply =3D <&vreg_s1b_1p856>; + vdd-l3-l4-l5-l7-l13-supply =3D <&vreg_bob>; + vdd-l6-l9-l11-supply =3D <&vreg_bob>; + vdd-l10-supply =3D <&vreg_s7b_0p952>; + + vdd-bob-supply =3D <&vph_pwr>; + + /* + * S2, S5, S7, S10 are ARCs: + * S2 - cx.lvl, + * S5 - mss.lvl, + * S7 - gfx.lvl, + * S10 - mx.lvl. + */ + + vreg_s1c_2p2: smps1 { + regulator-name =3D "vreg_s1c_2p2"; + regulator-min-microvolt =3D <2190000>; + regulator-max-microvolt =3D <2210000>; + }; + + vreg_s9c_0p676: smps9 { + regulator-name =3D "vreg_s9c_0p676"; + regulator-min-microvolt =3D <1010000>; + regulator-max-microvolt =3D <1170000>; + }; + + vreg_l1c_1p8: ldo1 { + regulator-name =3D "vreg_l1c_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1980000>; + regulator-initial-mode =3D ; + }; + + vreg_l2c_1p8: ldo2 { + regulator-name =3D "vreg_l2c_1p8"; + regulator-min-microvolt =3D <1620000>; + regulator-max-microvolt =3D <1980000>; + regulator-initial-mode =3D ; + }; + + vreg_l3c_3p0: ldo3 { + regulator-name =3D "vreg_l3c_3p0"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <3540000>; + regulator-initial-mode =3D ; + }; + + vreg_l4c_1p8_3p0: ldo4 { + regulator-name =3D "vreg_l4c_1p8_3p0"; + regulator-min-microvolt =3D <1620000>; + regulator-max-microvolt =3D <3300000>; + regulator-initial-mode =3D ; + }; + + vreg_l5c_1p8_3p0: ldo5 { + regulator-name =3D "vreg_l5c_1p8_3p0"; + regulator-min-microvolt =3D <1620000>; + regulator-max-microvolt =3D <3300000>; + regulator-initial-mode =3D ; + }; + + vreg_l6c_2p96: ldo6 { + regulator-name =3D "vreg_l6c_2p96"; + regulator-min-microvolt =3D <1650000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-name =3D "vreg_l7c_3p0"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-name =3D "vreg_l8c_1p8"; + regulator-min-microvolt =3D <1620000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + + vreg_l9c_2p96: ldo9 { + regulator-name =3D "vreg_l9c_2p96"; + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + }; + + vreg_l10c_0p88: ldo10 { + regulator-name =3D "vreg_l10c_0p88"; + regulator-min-microvolt =3D <720000>; + regulator-max-microvolt =3D <1050000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l11c_2p8: ldo11 { + regulator-name =3D "vreg_l11c_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + }; + + vreg_l12c_1p8: ldo12 { + regulator-name =3D "vreg_l12c_1p8"; + regulator-min-microvolt =3D <1650000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + + vreg_l13c_3p0: ldo13 { + regulator-name =3D "vreg_l13c_3p0"; + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + }; + + vreg_bob: bob { + regulator-name =3D "vreg_bob"; + regulator-min-microvolt =3D <3008000>; + regulator-max-microvolt =3D <3960000>; + regulator-initial-mode =3D ; + }; + }; +}; + +&dispcc { + status =3D "disabled"; +}; + +&gcc { + protected-clocks =3D , + , + , + , + , + , + , + , + , + , + , + , + ; +}; + +&gpi_dma0 { + status =3D "okay"; +}; + +&gpi_dma1 { + status =3D "okay"; +}; + +&gpu { + status =3D "okay"; +}; + +&gpu_zap_shader { + firmware-name =3D "qcom/sm7325/xiaomi/taoyao/a660_zap.mbn"; +}; + +&i2c1 { + clock-frequency =3D <100000>; + + status =3D "okay"; + + typec-mux@42 { + compatible =3D "fcs,fsa4480"; + reg =3D <0x42>; + + vcc-supply =3D <&vreg_bob>; + + mode-switch; + orientation-switch; + + port { + fsa4480_sbu_mux: endpoint { + remote-endpoint =3D <&pmic_glink_sbu>; + }; + }; + }; +}; + +&ipa { + qcom,gsi-loader =3D "self"; + memory-region =3D <&ipa_fw_mem>; + firmware-name =3D "qcom/sm7325/xiaomi/taoyao/ipa_fws.mbn"; + + status =3D "okay"; +}; + +&lpass_audiocc { + compatible =3D "qcom,qcm6490-lpassaudiocc"; + /delete-property/ power-domains; +}; + +&pm7325_gpios { + key_vol_up: key-vol-up-n-state { + pins =3D "gpio6"; + function =3D PMIC_GPIO_FUNC_NORMAL; + power-source =3D <1>; + bias-pull-up; + input-enable; + }; +}; + +&pmk8350_rtc { + status =3D "okay"; +}; + +&pon_pwrkey { + status =3D "okay"; +}; + +&pon_resin { + linux,code =3D ; + + status =3D "okay"; +}; + +&qup_spi13_cs { + drive-strength =3D <6>; + bias-disable; +}; + +&qup_spi13_data_clk { + drive-strength =3D <6>; + bias-disable; +}; + +&qupv3_id_0 { + status =3D "okay"; +}; + +&qupv3_id_1 { + status =3D "okay"; +}; + +&remoteproc_adsp { + firmware-name =3D "qcom/sm7325/xiaomi/taoyao/adsp.mbn"; + + status =3D "okay"; +}; + +&remoteproc_cdsp { + firmware-name =3D "qcom/sm7325/xiaomi/taoyao/cdsp.mbn"; + + status =3D "okay"; +}; + +&remoteproc_mpss { + firmware-name =3D "qcom/sm7325/xiaomi/taoyao/modem.mbn"; + + status =3D "okay"; +}; + +&remoteproc_wpss { + firmware-name =3D "qcom/sm7325/xiaomi/taoyao/wpss.mbn"; + + status =3D "okay"; +}; + +&spi13 { + status =3D "okay"; + + touchscreen@0 { + compatible =3D "goodix,gt9916"; + reg =3D <0>; + + interrupts-extended =3D <&tlmm 81 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios =3D <&tlmm 105 GPIO_ACTIVE_LOW>; + + avdd-supply =3D <&vreg_l7c_3p0>; + vddio-supply =3D <&vreg_l2c_1p8>; + + spi-max-frequency =3D <5000000>; + + touchscreen-size-x =3D <10800>; + touchscreen-size-y =3D <24000>; + + pinctrl-0 =3D <&ts_irq>, <&ts_reset>; + pinctrl-names =3D "default"; + }; +}; + +&tlmm { + gpio-reserved-ranges =3D <32 2>, <48 4>, <56 4>; + + bt_uart_sleep_cts: bt-uart-sleep-cts-state { + pins =3D "gpio28"; + function =3D "gpio"; + bias-bus-hold; + }; + + bt_uart_sleep_rts: bt-uart-sleep-rts-state { + pins =3D "gpio29"; + function =3D "gpio"; + bias-pull-down; + }; + + bt_uart_sleep_txd: bt-uart-sleep-txd-state { + pins =3D "gpio30"; + function =3D "gpio"; + bias-pull-up; + }; + + bt_uart_sleep_rxd: bt-uart-sleep-rxd-state { + pins =3D "gpio31"; + function =3D "gpio"; + bias-pull-up; + }; + + sde_dsi_active: sde-dsi-active-state { + pins =3D "gpio44"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-disable; + }; + + sde_dsi_sleep: sde-dsi-sleep-state { + pins =3D "gpio44"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + sde_te_active_sleep: sde-te-active-state { + pins =3D "gpio80"; + function =3D "mdp_vsync"; + drive-strength =3D <2>; + bias-pull-down; + }; + + ts_irq: ts-irq-state { + pins =3D "gpio81"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-pull-up; + }; + + hst_bt_en: hst-bt-en-state { + pins =3D "gpio85"; + function =3D "gpio"; + output-low; + bias-disable; + }; + + hst_sw_ctrl: hst-sw-ctrl-state { + pins =3D "gpio86"; + function =3D "gpio"; + bias-pull-down; + }; + + ts_reset: ts-reset-state { + pins =3D "gpio105"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-pull-up; + }; +}; + +&uart5 { + status =3D "okay"; +}; + +&uart7 { + /delete-property/interrupts; + interrupts-extended =3D <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 31 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-1 =3D <&bt_uart_sleep_cts>, + <&bt_uart_sleep_rts>, + <&bt_uart_sleep_txd>, + <&bt_uart_sleep_rxd>; + pinctrl-names =3D "default", "sleep"; + + status =3D "okay"; + + bluetooth: bluetooth { + compatible =3D "qcom,wcn6750-bt"; + + pinctrl-0 =3D <&hst_bt_en>, + <&hst_sw_ctrl>; + pinctrl-names =3D "default"; + + enable-gpios =3D <&tlmm 85 GPIO_ACTIVE_HIGH>; + swctrl-gpios =3D <&tlmm 86 GPIO_ACTIVE_HIGH>; + + vddio-supply =3D <&vreg_l19b_1p8>; + vddaon-supply =3D <&vreg_s7b_0p952>; + vddbtcxmx-supply =3D <&vreg_s7b_0p952>; + vddrfacmn-supply =3D <&vreg_s7b_0p952>; + vddrfa0p8-supply =3D <&vreg_s7b_0p952>; + vddrfa1p7-supply =3D <&vreg_s1b_1p856>; + vddrfa1p2-supply =3D <&vreg_s8b_1p256>; + vddrfa2p2-supply =3D <&vreg_s1c_2p2>; + vddasd-supply =3D <&vreg_l11c_2p8>; + max-speed =3D <3200000>; + + qcom,local-bd-address-broken; + }; +}; + +&ufs_mem_hc { + reset-gpios =3D <&tlmm 175 GPIO_ACTIVE_LOW>; + + vcc-supply =3D <&vreg_l7b_2p96>; + vcc-max-microamp =3D <800000>; + /* + * Technically l9b enables an eLDO (supplied by s1b) which then powers + * VCCQ2 of the UFS. + */ + vccq-supply =3D <&vreg_l9b_1p2>; + vccq-max-microamp =3D <900000>; + + status =3D "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply =3D <&vreg_l10c_0p88>; + vdda-pll-supply =3D <&vreg_l6b_1p2>; + + status =3D "okay"; +}; + +&usb_1 { + /* USB 2.0 only */ + qcom,select-utmi-as-pipe-clk; + + dr_mode =3D "otg"; + usb-role-switch; + maximum-speed =3D "high-speed"; + /* Remove USB3 phy */ + phys =3D <&usb_1_hsphy>; + phy-names =3D "usb2-phy"; + + status =3D "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint =3D <&pmic_glink_hs_in>; +}; + +&usb_1_hsphy { + vdda-pll-supply =3D <&vreg_l10c_0p88>; + vdda18-supply =3D <&vreg_l1c_1p8>; + vdda33-supply =3D <&vreg_l2b_3p072>; + + status =3D "okay"; +}; + +&venus { + firmware-name =3D "qcom/sm7325/xiaomi/taoyao/vpu20_1v.mbn"; + + status =3D "okay"; +}; + +&wifi { + status =3D "okay"; +}; --=20 2.51.0