From nobody Sat Feb 7 11:30:49 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CA2F3E9F78; Wed, 4 Feb 2026 11:15:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770203724; cv=none; b=T0aV3fBI6PQPveoC5Oo9rPT7ROGktyARW6eTKT3rB8kTBRvdKZCX3IcGXWtIKNtzYC/NA5jjonFvgsYk9ThuZju2OJCTYHm8I/dVH1se3SNp+0f74QMfZWLajd1IuRv1nMP3cIRMet3KJQkCn5kWRX5axjbVDYlWD+c68DZ6m6M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770203724; c=relaxed/simple; bh=1LR0jNMOWOcTc3yDkCe9j2hyAXae4IGjcC2V8uLYor0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GBbUH9e4Ywk0K0tcZrLwCVuPhLkEPXZdADg13szinRygY/S23IgXL1f4jXACWWKat/ZDJOW2e0IXav5iL+5MIniewiwpy1Ha0iwOslmDE7XWrh5vL1giZnlU4/rds+nKBlP4AjRjmUeeLo96Zaua0FE91umL9p7+x2NC0diANC4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=NtbYC092; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="NtbYC092" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1770203724; x=1801739724; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1LR0jNMOWOcTc3yDkCe9j2hyAXae4IGjcC2V8uLYor0=; b=NtbYC092AZkkRE+X6Azqvj4zTVw21ChlEbjsCM+duAB2ojH7P4uuC+wY mGbCnl3ZGrj9qQ/5JdiaX6pY/QSVem+3cVr/g89N/QAgNKMjd9CdKHJkB ti1dueG30FVEAUVYnoKGm0oVMg0Ub+7DhcANafV5bciLgRBKU/rbeHkki 1a2psq47DSwuxY7uzEcJPyhabgMDPz70zeuM3uIaX6OMW/RKXsd9n35K6 SjnHE7+gXhbCOITSm02vMv8/+Zgw7Y4kAlB8PSg7252xQDv7XVJNKPrCH CjiZitRXK4HCSwClqQoZ4zcQwW9z5/2X1CBPhqdkEwzQA+plSdAW7DDvg Q==; X-CSE-ConnectionGUID: 1JdvMKxlTGuBetR7YZigPg== X-CSE-MsgGUID: XvVmiy0mTL2Ir9ojAHaLgg== X-IronPort-AV: E=McAfee;i="6800,10657,11691"; a="70406042" X-IronPort-AV: E=Sophos;i="6.21,272,1763452800"; d="scan'208";a="70406042" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2026 03:15:24 -0800 X-CSE-ConnectionGUID: hWsvumg5Tl+nyabMW8g7BA== X-CSE-MsgGUID: M+wjN3+cT0O6lELowOgrZQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,272,1763452800"; d="scan'208";a="209739274" Received: from cpetruta-mobl1.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.245.181]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2026 03:15:22 -0800 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, rafael@kernel.org, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH V2 1/6] i3c: mipi-i3c-hci-pci: Set d3hot_delay to 0 for Intel controllers Date: Wed, 4 Feb 2026 13:15:06 +0200 Message-ID: <20260204111511.78626-2-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260204111511.78626-1-adrian.hunter@intel.com> References: <20260204111511.78626-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Set d3hot_delay to 0 for Intel controllers because a delay is not needed. Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V2: Add Frank's Rev'd-by drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c b/drivers/i= 3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c index 0f05a15c14c7..bc83caad4197 100644 --- a/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c +++ b/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c @@ -164,6 +164,7 @@ static int intel_i3c_init(struct mipi_i3c_hci_pci *hci) dma_set_mask_and_coherent(&hci->pci->dev, DMA_BIT_MASK(64)); =20 hci->pci->d3cold_delay =3D 0; + hci->pci->d3hot_delay =3D 0; =20 hci->private =3D host; host->priv =3D priv; --=20 2.51.0 From nobody Sat Feb 7 11:30:49 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 541ED3DA7E3; Wed, 4 Feb 2026 11:15:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770203726; cv=none; b=MZqqaYHhw+RZQ9SXa+g8AdkVLtu2vUHw3L+ZEAYJ57ssnodNvTZiKSlfRz+58271qMOfSBK/Ozc1asQB4waz48ohyB8z9OCjF0tEvfzvLLZ7XYUKv8FkSzMCX07FUep6Glxfshppl0zOhgms4BHkuObmn3ZYc4+QwI2qdN+MqC8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770203726; c=relaxed/simple; bh=w4uBEMnFw6IU1yfNVWzXyJJ/IeAOyUbFqbRawZssQ2M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RT2Jzs2nGwVjemN0Ayh5ug9GdgU+QeFpHh5xhri+KVDMIyKD6yCuilbP6wdG1/oodhaTxXZbYun1N93PRwoyRHF0eHxS+bSPgAvU2JY59TGEbmpVVu+UTw3/sQZ7Z4LaQ3V7w7HNq5hKhcpA2Pajnt9JdmZVyGeLMXlO7frVzYw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=EOHqvE7f; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="EOHqvE7f" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1770203726; x=1801739726; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=w4uBEMnFw6IU1yfNVWzXyJJ/IeAOyUbFqbRawZssQ2M=; b=EOHqvE7fm/YR0EWID9rA8WUIw+yqFB5adbtHt8iQyXLMPenSFqfD5ZRG lHbHF0YzzNJ/JI3RTtdNFBZTEVltpa5T3EZfUL88bnTsLbJTK/7IEM6/R r63t1DfukU2OqWwv0mezZ5O4VbSgwHO3Xgc6wL4Cb0W7cJd2Euxkgq8yi R5BTD9zlEV7pv037EQn6ACIPppoKPYGhLLcxjGMFn9x7efEkFkZ0ZaRPL O8nKHBCq0GJpDHpApMw53/0gwmexYKDkHx9X9z+GbYKoihfVyGdqReVQ+ 20ZdlHAriqNw7FudP7iEWfK1PlVs1BPgXEyPWsLI+T3d+9uKTryLCn+Lm g==; X-CSE-ConnectionGUID: MINL0cSRQ+S2ulttXUU4XQ== X-CSE-MsgGUID: CtG8pCIlSQ+I1mAf1wKmPQ== X-IronPort-AV: E=McAfee;i="6800,10657,11691"; a="70406048" X-IronPort-AV: E=Sophos;i="6.21,272,1763452800"; d="scan'208";a="70406048" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2026 03:15:26 -0800 X-CSE-ConnectionGUID: JGyTMG6ERISRZye3oPZ/fQ== X-CSE-MsgGUID: jwXsVocsRmmwRB30PvlIIQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,272,1763452800"; d="scan'208";a="209739278" Received: from cpetruta-mobl1.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.245.181]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2026 03:15:24 -0800 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, rafael@kernel.org, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH V2 2/6] i3c: master: Mark last_busy on IBI when runtime PM is allowed Date: Wed, 4 Feb 2026 13:15:07 +0200 Message-ID: <20260204111511.78626-3-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260204111511.78626-1-adrian.hunter@intel.com> References: <20260204111511.78626-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When an IBI can be received after the controller is pm_runtime_put_autosuspend()'ed, the interrupt may occur just before the device is auto-suspended. In such cases, the runtime PM core may not see any recent activity and may suspend the device earlier than intended. Mark the controller as last busy whenever an IBI is queued (when rpm_ibi_allowed is set) so that the auto-suspend delay correctly reflects recent bus activity and avoids premature suspension. Signed-off-by: Adrian Hunter --- Changes in V2: Adjusted slightly for earlier changes drivers/i3c/master.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c index 49fb6e30a68e..48d1b1256290 100644 --- a/drivers/i3c/master.c +++ b/drivers/i3c/master.c @@ -2721,9 +2721,14 @@ static void i3c_master_unregister_i3c_devs(struct i3= c_master_controller *master) */ void i3c_master_queue_ibi(struct i3c_dev_desc *dev, struct i3c_ibi_slot *s= lot) { + struct i3c_master_controller *master =3D i3c_dev_get_master(dev); + if (!dev->ibi || !slot) return; =20 + if (master->rpm_ibi_allowed) + pm_runtime_mark_last_busy(master->dev.parent); + atomic_inc(&dev->ibi->pending_ibis); queue_work(dev->ibi->wq, &slot->work); } --=20 2.51.0 From nobody Sat Feb 7 11:30:49 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D2673E9F84; Wed, 4 Feb 2026 11:15:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770203728; cv=none; b=PR4bL/OJwi3JaG9pYIWcwyTfIikvYgPwQdP+zAtpGwLemANUSf7VcwyYN6x3mQPKcqNW3wmVxBkSl0jS0grVtxWSGsRx4sV1oThWR3BqsZ/lw6G88P+r+yYWXq9zf2fxDhkYbShBiKqRPAA2tjOMZhhBXAmnGx6wZZxlNxfvuu0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770203728; c=relaxed/simple; bh=KkNfCwrKCHp8Xe5+Jm3fYu//MNhdQMcABR/3080KeIU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ctzyeKwzBSONsbJ6+tsJX+WktOrXCXnFFmtJNaR+Yq7leRiOZmrknFbzM7Z1AXbY4S0zSPorAvc9x46oga9tcRe9g8bT1avQ8i210QV1JrKPPjuXuwkFZlw9MbbPGYiIJdWaNUvTDnHR5tcS3H3wueLQUmdWMwZ3T3ABDQDA/GY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=dOyrMRar; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="dOyrMRar" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1770203728; x=1801739728; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KkNfCwrKCHp8Xe5+Jm3fYu//MNhdQMcABR/3080KeIU=; b=dOyrMRar9XEWH8A1meCJL+xxitC7VPe7C4sNVMvFtkO/YvpOon2aoNlD NCgi9oUyKXjA/487L7ZncdUatjQ8fr211mhSE/HhQHYIvSIKcipQPFcYN i+UOGGZ9rYdCKF5f15DlAIaqXu2KMEECH+32kiWMsPHZSMfmcHoJ1PMtZ eXNQKEtxQJXKnGmakTXOsynwcc22IdL8ZGUmIfJuTwA0w+AdnGgZ1sqUr siXQCsmVGnJtilGVd4vmGgtLlZuBAeZSwG9SUoZc4HwGGFAGGAAl6tXO6 GIt5nFqF5ObsaxUNYU2t8JkzqmdgrT82hPbE47bRonTWPFLIYorwu0SHD w==; X-CSE-ConnectionGUID: yhQkeQsgRzKdcCKl/DhplQ== X-CSE-MsgGUID: nIXc7OLRQpq3dZBvvGNd+w== X-IronPort-AV: E=McAfee;i="6800,10657,11691"; a="70406055" X-IronPort-AV: E=Sophos;i="6.21,272,1763452800"; d="scan'208";a="70406055" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2026 03:15:28 -0800 X-CSE-ConnectionGUID: bs6xWYdhSHmZPP79Wh20nw== X-CSE-MsgGUID: 9IPRzyk6SrKOvlnnRRw6cg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,272,1763452800"; d="scan'208";a="209739281" Received: from cpetruta-mobl1.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.245.181]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2026 03:15:26 -0800 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, rafael@kernel.org, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH V2 3/6] i3c: mipi-i3c-hci: Add quirk to allow IBI while runtime suspended Date: Wed, 4 Feb 2026 13:15:08 +0200 Message-ID: <20260204111511.78626-4-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260204111511.78626-1-adrian.hunter@intel.com> References: <20260204111511.78626-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some I3C controllers can be automatically runtime-resumed in order to handle in-band interrupts (IBIs), meaning that runtime suspend does not need to be blocked when IBIs are enabled. For example, a PCI-attached controller in a low-power state may generate a Power Management Event (PME) when the SDA line is pulled low to signal the START condition of an IBI. The PCI subsystem will then runtime-resume the device, allowing the IBI to be received without requiring the controller to remain active. Introduce a new quirk, HCI_QUIRK_RPM_IBI_ALLOWED, so that drivers can opt-in to this capability via driver data. Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V2: None drivers/i3c/master/mipi-i3c-hci/core.c | 3 +++ drivers/i3c/master/mipi-i3c-hci/hci.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index e925584113d1..ec4dbe64c35e 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -959,6 +959,9 @@ static int i3c_hci_probe(struct platform_device *pdev) if (hci->quirks & HCI_QUIRK_RPM_ALLOWED) i3c_hci_rpm_enable(&pdev->dev); =20 + if (hci->quirks & HCI_QUIRK_RPM_IBI_ALLOWED) + hci->master.rpm_ibi_allowed =3D true; + return i3c_master_register(&hci->master, &pdev->dev, &i3c_hci_ops, false); } =20 diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mip= i-i3c-hci/hci.h index 6035f74212db..819328a85b84 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -146,6 +146,7 @@ struct i3c_hci_dev_data { #define HCI_QUIRK_OD_PP_TIMING BIT(3) /* Set OD and PP timings for AMD p= latforms */ #define HCI_QUIRK_RESP_BUF_THLD BIT(4) /* Set resp buf thld to 0 for AMD= platforms */ #define HCI_QUIRK_RPM_ALLOWED BIT(5) /* Runtime PM allowed */ +#define HCI_QUIRK_RPM_IBI_ALLOWED BIT(6) /* IBI and Hot-Join allowed whil= e runtime suspended */ =20 /* global functions */ void mipi_i3c_hci_resume(struct i3c_hci *hci); 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charset="utf-8" Some platforms implement the MIPI I3C HCI Multi-Bus Instance capability, where a single parent device hosts multiple I3C controller instances. In such designs, the parent - not the individual child instances - may need to coordinate runtime PM so that all controllers runtime PM callbacks are invoked in a controlled and synchronized manner. For example, if the parent enables IBI-wakeup when transitioning into a low-power state, every bus instance must remain able to receive IBIs up until that point. This requires deferring the individual controllers' runtime suspend callbacks (which disable bus activity) until the parent decides it is safe for all instances to suspend together. To support this usage model: * Export the low-level runtime PM suspend and resume helpers so that the parent can explicitly invoke them. * Add a new quirk, HCI_QUIRK_RPM_PARENT_MANAGED, allowing platforms to bypass per-instance runtime PM callbacks and delegate control to the parent device. * Move DEFAULT_AUTOSUSPEND_DELAY_MS into the header so it can be shared by parent-managed PM implementations. The new quirk allows platforms with multi-bus parent-managed PM infrastructure to correctly coordinate runtime PM across all I3C HCI instances. Signed-off-by: Adrian Hunter --- Changes in V2: For HCI_QUIRK_RPM_PARENT_MANAGED case, change from disabling runtime PM to instead causing the runtime PM callbacks to do nothing drivers/i3c/master/mipi-i3c-hci/core.c | 28 ++++++++++++++++++++++---- drivers/i3c/master/mipi-i3c-hci/hci.h | 6 ++++++ 2 files changed, 30 insertions(+), 4 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index ec4dbe64c35e..149b3fad34b5 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -733,7 +733,7 @@ static int i3c_hci_reset_and_init(struct i3c_hci *hci) return 0; } =20 -static int i3c_hci_runtime_suspend(struct device *dev) +int i3c_hci_rpm_suspend(struct device *dev) { struct i3c_hci *hci =3D dev_get_drvdata(dev); int ret; @@ -746,8 +746,9 @@ static int i3c_hci_runtime_suspend(struct device *dev) =20 return 0; } +EXPORT_SYMBOL_GPL(i3c_hci_rpm_suspend); =20 -static int i3c_hci_runtime_resume(struct device *dev) +int i3c_hci_rpm_resume(struct device *dev) { struct i3c_hci *hci =3D dev_get_drvdata(dev); int ret; @@ -768,6 +769,27 @@ static int i3c_hci_runtime_resume(struct device *dev) =20 return 0; } +EXPORT_SYMBOL_GPL(i3c_hci_rpm_resume); + +static int i3c_hci_runtime_suspend(struct device *dev) +{ + struct i3c_hci *hci =3D dev_get_drvdata(dev); + + if (hci->quirks & HCI_QUIRK_RPM_PARENT_MANAGED) + return 0; + + return i3c_hci_rpm_suspend(dev); +} + +static int i3c_hci_runtime_resume(struct device *dev) +{ + struct i3c_hci *hci =3D dev_get_drvdata(dev); + + if (hci->quirks & HCI_QUIRK_RPM_PARENT_MANAGED) + return 0; + + return i3c_hci_rpm_resume(dev); +} =20 static int i3c_hci_suspend(struct device *dev) { @@ -812,8 +834,6 @@ static int i3c_hci_restore(struct device *dev) return i3c_hci_resume_common(dev, true); } =20 -#define DEFAULT_AUTOSUSPEND_DELAY_MS 1000 - static void i3c_hci_rpm_enable(struct device *dev) { struct i3c_hci *hci =3D dev_get_drvdata(dev); diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mip= i-i3c-hci/hci.h index 819328a85b84..584ee632b634 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -147,6 +147,7 @@ struct i3c_hci_dev_data { #define HCI_QUIRK_RESP_BUF_THLD BIT(4) /* Set resp buf thld to 0 for AMD= platforms */ #define HCI_QUIRK_RPM_ALLOWED BIT(5) /* Runtime PM allowed */ #define HCI_QUIRK_RPM_IBI_ALLOWED BIT(6) /* IBI and Hot-Join allowed whil= e runtime suspended */ +#define HCI_QUIRK_RPM_PARENT_MANAGED BIT(7) /* Runtime PM managed by pare= nt device */ =20 /* global functions */ void mipi_i3c_hci_resume(struct i3c_hci *hci); @@ -156,4 +157,9 @@ void amd_set_od_pp_timing(struct i3c_hci *hci); void amd_set_resp_buf_thld(struct i3c_hci *hci); void i3c_hci_sync_irq_inactive(struct i3c_hci *hci); =20 +#define DEFAULT_AUTOSUSPEND_DELAY_MS 1000 + +int i3c_hci_rpm_suspend(struct device *dev); +int i3c_hci_rpm_resume(struct device *dev); + #endif --=20 2.51.0 From nobody Sat Feb 7 11:30:49 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADFC33E9F76; Wed, 4 Feb 2026 11:15:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770203733; cv=none; b=jhEgoUc8ltNwCpr4J5T4rZ0c4zau6tDVG7w6Stm3wojGhyaY0zdh5M/Xke8QB021PPHvtHYU5lXl4tgiyO3yN/SjRe//BzxVYD4llGPh66KdnD7jfX+D5RgKjmkFbv64NZTdfv5JIAFM3kr1TYOyohv5xaUb/z1iimCpMS8hwVk= ARC-Message-Signature: i=1; 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d="scan'208";a="209739288" Received: from cpetruta-mobl1.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.245.181]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2026 03:15:31 -0800 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, rafael@kernel.org, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH V2 5/6] i3c: mipi-i3c-hci-pci: Add optional ability to manage child runtime PM Date: Wed, 4 Feb 2026 13:15:10 +0200 Message-ID: <20260204111511.78626-6-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260204111511.78626-1-adrian.hunter@intel.com> References: <20260204111511.78626-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some platforms implement the MIPI I3C HCI Multi-Bus Instance capability, where a single parent device hosts multiple I3C controller instances. In such designs, the parent - not the individual child instances - may need to coordinate runtime PM so that all controllers runtime PM callbacks are invoked in a controlled and synchronized manner. For example, if the parent enables IBI-wakeup when transitioning into a low-power state, every bus instance must remain able to receive IBIs up until that point. This requires deferring the individual controllers' runtime suspend callbacks (which disable bus activity) until the parent decides it is safe for all instances to suspend together. To support this usage model: * Add runtime PM and system PM callbacks in the PCI driver to invoke the mipi-i3c-hci driver's runtime PM callbacks for each instance. * Introduce a driver-data flag, control_instance_pm, which opts into the new parent-managed PM behaviour. * Ensure the callbacks are only used when the corresponding instance is operational at suspend time. This is reliable because the operational state cannot change while the parent device is undergoing a PM transition, and PCI always performs a runtime resume before system suspend on current configurations, so that suspend and resume alternate irrespective of whether it is runtime or system PM. By that means, parent-managed runtime PM coordination for multi-instance MIPI I3C HCI PCI devices is provided without altering existing behaviour on platforms that do not require it. Signed-off-by: Adrian Hunter --- Changes in V2: Do not enable autosuspend. Callbacks for parent-managed invocation were renamed from i3c_hci_runtime_suspend to i3c_hci_rpm_suspend and from i3c_hci_runtime_resume to i3c_hci_rpm_resume. Amend commit message slightly. .../master/mipi-i3c-hci/mipi-i3c-hci-pci.c | 134 ++++++++++++++++++ 1 file changed, 134 insertions(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c b/drivers/i= 3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c index bc83caad4197..c562e666f29a 100644 --- a/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c +++ b/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -20,16 +21,24 @@ #include #include =20 +#include "hci.h" + /* * There can up to 15 instances, but implementations have at most 2 at this * time. */ #define INST_MAX 2 =20 +struct mipi_i3c_hci_pci_instance { + struct device *dev; + bool operational; +}; + struct mipi_i3c_hci_pci { struct pci_dev *pci; void __iomem *base; const struct mipi_i3c_hci_pci_info *info; + struct mipi_i3c_hci_pci_instance instance[INST_MAX]; void *private; }; =20 @@ -40,6 +49,7 @@ struct mipi_i3c_hci_pci_info { int id[INST_MAX]; u32 instance_offset[INST_MAX]; int instance_count; + bool control_instance_pm; }; =20 #define INTEL_PRIV_OFFSET 0x2b0 @@ -210,6 +220,128 @@ static const struct mipi_i3c_hci_pci_info intel_si_2_= info =3D { .instance_count =3D 1, }; =20 +static int mipi_i3c_hci_pci_find_instance(struct mipi_i3c_hci_pci *hci, st= ruct device *dev) +{ + for (int i =3D 0; i < INST_MAX; i++) { + if (!hci->instance[i].dev) + hci->instance[i].dev =3D dev; + if (hci->instance[i].dev =3D=3D dev) + return i; + } + + return -1; +} + +#define HC_CONTROL 0x04 +#define HC_CONTROL_BUS_ENABLE BIT(31) + +static bool __mipi_i3c_hci_pci_is_operational(struct device *dev) +{ + const struct mipi_i3c_hci_platform_data *pdata =3D dev->platform_data; + u32 hc_control =3D readl(pdata->base_regs + HC_CONTROL); + + return hc_control & HC_CONTROL_BUS_ENABLE; +} + +static bool mipi_i3c_hci_pci_is_operational(struct device *dev, bool updat= e) +{ + struct mipi_i3c_hci_pci *hci =3D dev_get_drvdata(dev->parent); + int pos =3D mipi_i3c_hci_pci_find_instance(hci, dev); + + if (pos < 0) { + dev_err(dev, "%s: I3C instance not found\n", __func__); + return false; + } + + if (update) + hci->instance[pos].operational =3D __mipi_i3c_hci_pci_is_operational(dev= ); + + return hci->instance[pos].operational; +} + +struct mipi_i3c_hci_pci_pm_data { + struct device *dev[INST_MAX]; + int dev_cnt; +}; + +static bool mipi_i3c_hci_pci_is_mfd(struct device *dev) +{ + return dev_is_platform(dev) && mfd_get_cell(to_platform_device(dev)); +} + +static int mipi_i3c_hci_pci_suspend_instance(struct device *dev, void *dat= a) +{ + struct mipi_i3c_hci_pci_pm_data *pm_data =3D data; + int ret; + + if (!mipi_i3c_hci_pci_is_mfd(dev) || + !mipi_i3c_hci_pci_is_operational(dev, true)) + return 0; + + ret =3D i3c_hci_rpm_suspend(dev); + if (ret) + return ret; + + pm_data->dev[pm_data->dev_cnt++] =3D dev; + + return 0; +} + +static int mipi_i3c_hci_pci_resume_instance(struct device *dev, void *data) +{ + struct mipi_i3c_hci_pci_pm_data *pm_data =3D data; + int ret; + + if (!mipi_i3c_hci_pci_is_mfd(dev) || + !mipi_i3c_hci_pci_is_operational(dev, false)) + return 0; + + ret =3D i3c_hci_rpm_resume(dev); + if (ret) + return ret; + + pm_data->dev[pm_data->dev_cnt++] =3D dev; + + return 0; +} + +static int mipi_i3c_hci_pci_suspend(struct device *dev) +{ + struct mipi_i3c_hci_pci *hci =3D dev_get_drvdata(dev); + struct mipi_i3c_hci_pci_pm_data pm_data =3D {}; + int ret; + + if (!hci->info->control_instance_pm) + return 0; + + ret =3D device_for_each_child_reverse(dev, &pm_data, mipi_i3c_hci_pci_sus= pend_instance); + if (ret) { + if (ret =3D=3D -EAGAIN || ret =3D=3D -EBUSY) + pm_runtime_mark_last_busy(&hci->pci->dev); + for (int i =3D 0; i < pm_data.dev_cnt; i++) + i3c_hci_rpm_resume(pm_data.dev[i]); + } + + return ret; +} + +static int mipi_i3c_hci_pci_resume(struct device *dev) +{ + struct mipi_i3c_hci_pci *hci =3D dev_get_drvdata(dev); + struct mipi_i3c_hci_pci_pm_data pm_data =3D {}; + int ret; + + if (!hci->info->control_instance_pm) + return 0; + + ret =3D device_for_each_child(dev, &pm_data, mipi_i3c_hci_pci_resume_inst= ance); + if (ret) + for (int i =3D 0; i < pm_data.dev_cnt; i++) + i3c_hci_rpm_suspend(pm_data.dev[i]); + + return ret; +} + static void mipi_i3c_hci_pci_rpm_allow(struct device *dev) { pm_runtime_put(dev); @@ -323,6 +455,8 @@ static void mipi_i3c_hci_pci_remove(struct pci_dev *pci) =20 /* PM ops must exist for PCI to put a device to a low power state */ static const struct dev_pm_ops mipi_i3c_hci_pci_pm_ops =3D { + RUNTIME_PM_OPS(mipi_i3c_hci_pci_suspend, mipi_i3c_hci_pci_resume, NULL) + SYSTEM_SLEEP_PM_OPS(mipi_i3c_hci_pci_suspend, mipi_i3c_hci_pci_resume) }; =20 static const struct pci_device_id mipi_i3c_hci_pci_devices[] =3D { --=20 2.51.0 From nobody Sat Feb 7 11:30:49 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC11D3ECBC4; Wed, 4 Feb 2026 11:15:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; 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04 Feb 2026 03:15:35 -0800 X-CSE-ConnectionGUID: WRl7Nv9dT4eYUi9DBOcG8Q== X-CSE-MsgGUID: OTM0MQiwQ+6X57JQAv4aYA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,272,1763452800"; d="scan'208";a="209739293" Received: from cpetruta-mobl1.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.245.181]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2026 03:15:33 -0800 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, rafael@kernel.org, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH V2 6/6] i3c: mipi-i3c-hci-pci: Enable IBI while runtime suspended for Intel controllers Date: Wed, 4 Feb 2026 13:15:11 +0200 Message-ID: <20260204111511.78626-7-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260204111511.78626-1-adrian.hunter@intel.com> References: <20260204111511.78626-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Intel LPSS I3C controllers can wake from runtime suspend to receive in-band interrupts (IBIs), and they also implement the MIPI I3C HCI Multi-Bus Instance capability. When multiple I3C bus instances share the same PCI wakeup, the PCI parent must coordinate runtime PM so that all instances suspend together and their mipi-i3c-hci runtime suspend callbacks are invoked in a consistent manner. Enable IBI-based wakeup by setting HCI_QUIRK_RPM_IBI_ALLOWED for the intel-lpss-i3c platform device. Also set HCI_QUIRK_RPM_PARENT_MANAGED so that the mipi-i3c-hci core driver expects runtime PM to be controlled by the PCI parent rather than by individual instances. For all Intel HCI PCI configurations, enable the corresponding control_instance_pm flag in the PCI driver. Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V2: Retain HCI_QUIRK_RPM_ALLOWED Amend commit message accordingly drivers/i3c/master/mipi-i3c-hci/core.c | 4 +++- drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c | 3 +++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index 149b3fad34b5..d19be1d276b5 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -1005,7 +1005,9 @@ static const struct acpi_device_id i3c_hci_acpi_match= [] =3D { MODULE_DEVICE_TABLE(acpi, i3c_hci_acpi_match); =20 static const struct platform_device_id i3c_hci_driver_ids[] =3D { - { .name =3D "intel-lpss-i3c", HCI_QUIRK_RPM_ALLOWED }, + { .name =3D "intel-lpss-i3c", HCI_QUIRK_RPM_ALLOWED | + HCI_QUIRK_RPM_IBI_ALLOWED | + HCI_QUIRK_RPM_PARENT_MANAGED }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(platform, i3c_hci_driver_ids); diff --git a/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c b/drivers/i= 3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c index c562e666f29a..58c4a025a29c 100644 --- a/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c +++ b/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c @@ -200,6 +200,7 @@ static const struct mipi_i3c_hci_pci_info intel_mi_1_in= fo =3D { .id =3D {0, 1}, .instance_offset =3D {0, 0x400}, .instance_count =3D 2, + .control_instance_pm =3D true, }; =20 static const struct mipi_i3c_hci_pci_info intel_mi_2_info =3D { @@ -209,6 +210,7 @@ static const struct mipi_i3c_hci_pci_info intel_mi_2_in= fo =3D { .id =3D {2, 3}, .instance_offset =3D {0, 0x400}, .instance_count =3D 2, + .control_instance_pm =3D true, }; =20 static const struct mipi_i3c_hci_pci_info intel_si_2_info =3D { @@ -218,6 +220,7 @@ static const struct mipi_i3c_hci_pci_info intel_si_2_in= fo =3D { .id =3D {2}, .instance_offset =3D {0}, .instance_count =3D 1, + .control_instance_pm =3D true, }; =20 static int mipi_i3c_hci_pci_find_instance(struct mipi_i3c_hci_pci *hci, st= ruct device *dev) --=20 2.51.0