From nobody Sat Feb 7 11:30:57 2026 Received: from CH5PR02CU005.outbound.protection.outlook.com (mail-northcentralusazon11012054.outbound.protection.outlook.com [40.107.200.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF5263D3CEA; Wed, 4 Feb 2026 10:49:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.200.54 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770202189; cv=fail; b=ckV9i3EO8Iqfe8aNdC9CNI6HIQkqmhpoNMtybIOBkyrA31wXWD56GqK5LMrUvN2VQSNRNchg8hc6eALUc18aQrtQox5F7n7CuiJmhU7ciZpAP8uHlb6RepdTFeLPY2K09PF95UUan5lH6GbkpkuhElZLjvta4wuTJ0jIOc7fixA= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770202189; c=relaxed/simple; bh=C9cm2iXuak+Aiim5hcLXZr0m8FOy1/ZJERS0j7b0uS8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QU4/i4MNlrgz2MPy+dbLsWkrNjVJswp9b23P608TPHLwFx7tYBrp5KoOWgtVrJHIkZ/ai8F4b1Y93Mp3oh7I1PJeVtq0xuzHiz/pSn0+tkb/qXD7WJvqmetmitGKlKS1ec8Esc6g43LylSSMXpzxxnjk7k76kROb4KEmboNcId8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=Je/PG6rW; arc=fail smtp.client-ip=40.107.200.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="Je/PG6rW" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=BL30/yMwr3nPmJcHZ3YqCbe1elBeqIbO7mMWNZOwgrkFZgF/O3nep7ymsbRG+lxm1jLTKtnR4AAWdz3JTkvyV0XnvRnaoisx1fkT7valdRFVVNAvnfzowqLv4FkI/2KrRpV/EKSo4Ee4IcWvByhVkFBQKKdnXW8iryAAngWQAGR2bCOvkf123K0mdB03o9I14GkQaCxRAvsdLUI5jMnK15tztQFsgP1+WO+qZXKYY3IXE1Fy+AnEO0/nsMDYWydevHSuEVTwZj7dNLREBvYrdVYlUJrE2N0TWP0gryUvFla/J2fRxdyzekGGjYZBOTAlK7RBSVDhMtLSJFAA3i1ezA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=7rPHK7Fy1oZvuFWiCpe6lxFZonKGxzvyYt3tnuKDna4=; b=jFVFrDFprXtTOd/Qr1C95p/EhIXWHuW+UWDcDv3Ro8ZKU3apo38/U3OXa2kJKkpp/eaNYXCwKjllTuFW4ZsZwbcqRXzfVmbour7kgCdBHfKkp3AUK2fW1o+alqrjUEfp2onP7Bo64VZ05q3lGbnXweshWlLOVGkCmUtnxMNxr5o9/NTF0Mtbm7pk7gBhN1TL82/Bc31ZfNFhyOQI96IcXVIdYddk1yoh0xO/tGgE435nLON2kNltb0hkn/0BG/9CjgQrbdfv8Xp/GLF3KRl8F+jGmEk9ZDf5EZGJZpQMhJlJMZ8/buoj4NU10Y9PBSRd0+VSAxKvf3S4VWnoNMlorw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=google.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=7rPHK7Fy1oZvuFWiCpe6lxFZonKGxzvyYt3tnuKDna4=; b=Je/PG6rWsk5zH9Z+4+CrCGkVSAshnsBV1ZSg0ITK0SOjcur1yH78bnXBExTFMNWBmqCmEIxdfVAsj6FURhuQ3hsauNHwQRmv/K7EDxL5VQ2pngz9gaYpjTcAqdu4bcfKHaXZzC/9mBFgQfZMGKOzGABaY50pfHACPztI88bxsOQ= Received: from BL1PR13CA0213.namprd13.prod.outlook.com (2603:10b6:208:2bf::8) by DM6PR12MB4354.namprd12.prod.outlook.com (2603:10b6:5:28f::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9587.13; Wed, 4 Feb 2026 10:49:44 +0000 Received: from BL6PEPF0001AB4A.namprd04.prod.outlook.com (2603:10b6:208:2bf:cafe::cb) by BL1PR13CA0213.outlook.office365.com (2603:10b6:208:2bf::8) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9587.13 via Frontend Transport; Wed, 4 Feb 2026 10:49:52 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BL6PEPF0001AB4A.mail.protection.outlook.com (10.167.242.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9587.10 via Frontend Transport; Wed, 4 Feb 2026 10:49:44 +0000 Received: from satlexmb07.amd.com (10.181.42.216) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Wed, 4 Feb 2026 04:49:43 -0600 Received: from xhdapps-pcie2.xilinx.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Wed, 4 Feb 2026 02:49:41 -0800 From: Devendra K Verma To: , , CC: , , , , Subject: [PATCH v10 1/2] dmaengine: dw-edma: Add AMD MDB Endpoint Support Date: Wed, 4 Feb 2026 16:19:32 +0530 Message-ID: <20260204104933.33179-2-devendra.verma@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260204104933.33179-1-devendra.verma@amd.com> References: <20260204104933.33179-1-devendra.verma@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4A:EE_|DM6PR12MB4354:EE_ X-MS-Office365-Filtering-Correlation-Id: bd7f7283-9da1-429e-8ea1-08de63db1b71 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?dfjzOnhqBHX550AHwpWSVjkHQrTsOWGGkDwpfaRKb2B/CTFBuBv8cYNG9RD4?= =?us-ascii?Q?HrDAFTaIY3iHLtk2iKqBW2w4IaMdkUvxoAbv8VwyAd6gVPCjF5GcxMukRKi8?= =?us-ascii?Q?Q4NXglSkkJrb5CTx3PbgsrvshUmH+LdwITU0RW1wbLqV02OqwYXB8lpA90RK?= =?us-ascii?Q?8Sx8Xo9if1iOBPhCMa808wf7v7zoVWjVJl74wA5tszq8j877RkNSEZgYoZ5Q?= =?us-ascii?Q?9Pgf8fXQ5nSbh0+qauja9Xjddi9ZGQ8iJRKlW0HEZHvIQuXLdCF6KLuM89UD?= =?us-ascii?Q?EKrw+nCZnrKEeQhRjA1LGnARVDRfK41mNiRIs53uyXG1Ovh6qbxKKd8BQSBJ?= =?us-ascii?Q?TIMTWi3vluCDGGb2piBdK/veZlcNirbP3/OjSSq3B0JoHplHBsfd1xKKJlD8?= =?us-ascii?Q?DGfXtNt/BSyxcw1v78LJZBoRV+zNXV6y2JzjnI6xcnVR0ntEUd7HsSxKCgnw?= =?us-ascii?Q?TmeynyfGQTuRqLfptUIeC0BUXX7LiXlgj/DyUe0zauA6AqL3dfeqdn+nVPhE?= =?us-ascii?Q?Hq8/zITH1C1q2uhLr6EZxc7PrFSvk1ukl6ZAQJxOv91XxQCKQ3WFG7udph0W?= =?us-ascii?Q?EKWuCTASXxgGBU9Wb0qEtO0lQ3docJTXNEL1m0DJOYtsRVdEULQMKHsWAWrv?= =?us-ascii?Q?KxyYH1RncAeuGbixAYYWp2B1d0FVT9zFOFSEKmk6UpF3qvoxKYMg/97OGxTt?= =?us-ascii?Q?Q9dWWqIr+KcKcvbrsTGjW4TZO2S+rQFYOi8B+e4rB7souROVPm0sE91HWHbT?= =?us-ascii?Q?YfjBwFo398SjfsO6zcKEWdZ2NiwssLXtyzy6oO1n3N5C58T7/GAi7bTe3RQn?= =?us-ascii?Q?coBmTV0kmri+P4mpLdI9whMxdwkHL82qnMArOkjT7ONANvTy62hAax1s8QUl?= =?us-ascii?Q?2TzHVYtnt1mJUCq88xFBK+VLhR8ALc1uzxw5CbGvkEKay/WP8kUoNn3QqA1F?= =?us-ascii?Q?Kl9OThoLN3Lz/gITemCSbNEohv8Mi0I8NKIcMXnU2QNzv2NR2v7t/i1ObIrT?= =?us-ascii?Q?MY3+hyc25WMXvDVaeZXRWnX2Q3C3o6/IR66Qad5G4lay5mpspDvulwCXcYEB?= =?us-ascii?Q?FUU8AeSRIcGUFc3+XMV1tgrsIjQLLYgjzFt7RYuCxOyyfUkb7SGojQiGk3cV?= =?us-ascii?Q?sNMT4S7t/ynmlI50/xV0+GY4kxevf1e07egi9wLttNpeuEcdB9AIBwJAeeI4?= =?us-ascii?Q?DNouHjnY8WnLz+BpU4q4bkDSKPmkFCC/NDvuayb2/aR8PFDx3EIp0x/m/unk?= =?us-ascii?Q?6UF1piVx139VGCnLtLatf8BLBQsPCHHv/CNBhryFacnNzirzLGXh10ApQVRC?= =?us-ascii?Q?ZADkLqMJlOjND36zIp9uqisuo2r/L3lQ/5HZtJk38FbeoOxAm18oFwIvTVk0?= =?us-ascii?Q?E4VK4XuecHpkDtjYFIDA+BgfyAWBsu4Hcrgepu45UYTqd7jbrIyaK0P3Ocub?= =?us-ascii?Q?GVZG7ZXlZgyvkXdmF1Pag09EeHE88k1hXACEy599pQbBpd6QBewtL0GDV9sH?= =?us-ascii?Q?Zc3cocpLYg1iZhtqOPsrstmZouT3ma90uVAXHeiLXCJ9tkvkRl69bb2W6dQu?= =?us-ascii?Q?lNl4AgZrdm4JPZsZULNiCRRQWT/KGHziFVggGi1RxhgQ36HVTyU4YbxjIrrb?= =?us-ascii?Q?ldyvgyhZeJF1OQioVaKzxK1V3n6jpdZDGXjk853pzh86zQ+mhEMd7LXIolOu?= =?us-ascii?Q?47Xdcg=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: dYuY9qFisP0Ld0TSw0Xa7YFJDDAYwi6rnWySFXK+J/92zGAKyX2XTdgxMZ81PMOcY1b6VcF9LaUPNk28bKPqFZtSXEmW724zByPtIYmpEAMkNTQiRrvACqGIBfVk9vwdGJkX0Exic5TWAg1mUj27lIVPUOG68jH1chTBk+S3Rng1GGk/TXFEG+9ujMwOTzHHHyPSqH+owiDN9M5l26jh1mQQLjaSDwfKFisfHsqgfZEFTCp+lNGuuvtMcreo3LDww2/zVndikXMwYMDhddhQ5qYkNGGyDcZQcwFe/i6jRTJ2pRY9cUr5M92HxAGJlLKt5HZA0+8KUsfZQTc2dAPhI1khAOlccaT5/JZTvLmg2ly+Quipy+8aMzd9WrFZGTR7S3QqUNU7vzUSfzst+ziHPRLKAS8E5EYWDjFGCHM07K+dtEdZ58PfC0Y/RDH+DaCv X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Feb 2026 10:49:44.2154 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bd7f7283-9da1-429e-8ea1-08de63db1b71 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4354 Content-Type: text/plain; charset="utf-8" AMD MDB PCIe endpoint support. For AMD specific support added the following - AMD supported PCIe Device IDs and Vendor ID (Xilinx). - AMD MDB specific driver data - AMD MDB specific VSEC capability to retrieve the device DDR base address. Signed-off-by: Devendra K Verma --- Changes in v10: For Xilinx VSEC function kept only HDMA map format as Xilinx only supports HDMA. Changes in v9: Moved Xilinx specific VSEC capability functions under the vendor ID condition. Changes in v8: Changed the contant names to includer product vendor. Moved the vendor specific code to vendor specific functions. Changes in v7: Introduced vendor specific functions to retrieve the vsec data. Changes in v6: Included "sizes.h" header and used the appropriate definitions instead of constants. Changes in v5: Added the definitions for Xilinx specific VSEC header id, revision, and register offsets. Corrected the error type when no physical offset found for device side memory. Corrected the order of variables. Changes in v4: Configured 8 read and 8 write channels for Xilinx vendor Added checks to validate vendor ID for vendor specific vsec id. Added Xilinx specific vendor id for vsec specific to Xilinx Added the LL and data region offsets, size as input params to function dw_edma_set_chan_region_offset(). Moved the LL and data region offsets assignment to function for Xilinx specific case. Corrected comments. Changes in v3: Corrected a typo when assigning AMD (Xilinx) vsec id macro and condition check. Changes in v2: Reverted the devmem_phys_off type to u64. Renamed the function appropriately to suit the functionality for setting the LL & data region offsets. Changes in v1: Removed the pci device id from pci_ids.h file. Added the vendor id macro as per the suggested method. Changed the type of the newly added devmem_phys_off variable. Added to logic to assign offsets for LL and data region blocks in case more number of channels are enabled than given in amd_mdb_data struct. --- drivers/dma/dw-edma/dw-edma-pcie.c | 190 ++++++++++++++++++++++++++--- 1 file changed, 176 insertions(+), 14 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-ed= ma-pcie.c index 3371e0a76d3c..3aefc48f8e0a 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -14,14 +14,35 @@ #include #include #include +#include =20 #include "dw-edma-core.h" =20 -#define DW_PCIE_VSEC_DMA_ID 0x6 -#define DW_PCIE_VSEC_DMA_BAR GENMASK(10, 8) -#define DW_PCIE_VSEC_DMA_MAP GENMASK(2, 0) -#define DW_PCIE_VSEC_DMA_WR_CH GENMASK(9, 0) -#define DW_PCIE_VSEC_DMA_RD_CH GENMASK(25, 16) +/* Synopsys */ +#define DW_PCIE_SYNOPSYS_VSEC_DMA_ID 0x6 +#define DW_PCIE_SYNOPSYS_VSEC_DMA_BAR GENMASK(10, 8) +#define DW_PCIE_SYNOPSYS_VSEC_DMA_MAP GENMASK(2, 0) +#define DW_PCIE_SYNOPSYS_VSEC_DMA_WR_CH GENMASK(9, 0) +#define DW_PCIE_SYNOPSYS_VSEC_DMA_RD_CH GENMASK(25, 16) + +/* AMD MDB (Xilinx) specific defines */ +#define PCI_DEVICE_ID_XILINX_B054 0xb054 + +#define DW_PCIE_XILINX_MDB_VSEC_DMA_ID 0x6 +#define DW_PCIE_XILINX_MDB_VSEC_ID 0x20 +#define DW_PCIE_XILINX_MDB_VSEC_DMA_BAR GENMASK(10, 8) +#define DW_PCIE_XILINX_MDB_VSEC_DMA_MAP GENMASK(2, 0) +#define DW_PCIE_XILINX_MDB_VSEC_DMA_WR_CH GENMASK(9, 0) +#define DW_PCIE_XILINX_MDB_VSEC_DMA_RD_CH GENMASK(25, 16) + +#define DW_PCIE_XILINX_MDB_DEVMEM_OFF_REG_HIGH 0xc +#define DW_PCIE_XILINX_MDB_DEVMEM_OFF_REG_LOW 0x8 +#define DW_PCIE_XILINX_MDB_INVALID_ADDR (~0ULL) + +#define DW_PCIE_XILINX_MDB_LL_OFF_GAP 0x200000 +#define DW_PCIE_XILINX_MDB_LL_SIZE 0x800 +#define DW_PCIE_XILINX_MDB_DT_OFF_GAP 0x100000 +#define DW_PCIE_XILINX_MDB_DT_SIZE 0x800 =20 #define DW_BLOCK(a, b, c) \ { \ @@ -50,6 +71,7 @@ struct dw_edma_pcie_data { u8 irqs; u16 wr_ch_cnt; u16 rd_ch_cnt; + u64 devmem_phys_off; }; =20 static const struct dw_edma_pcie_data snps_edda_data =3D { @@ -90,6 +112,64 @@ static const struct dw_edma_pcie_data snps_edda_data = =3D { .rd_ch_cnt =3D 2, }; =20 +static const struct dw_edma_pcie_data xilinx_mdb_data =3D { + /* MDB registers location */ + .rg.bar =3D BAR_0, + .rg.off =3D SZ_4K, /* 4 Kbytes */ + .rg.sz =3D SZ_8K, /* 8 Kbytes */ + + /* Other */ + .mf =3D EDMA_MF_HDMA_NATIVE, + .irqs =3D 1, + .wr_ch_cnt =3D 8, + .rd_ch_cnt =3D 8, +}; + +static void dw_edma_set_chan_region_offset(struct dw_edma_pcie_data *pdata, + enum pci_barno bar, off_t start_off, + off_t ll_off_gap, size_t ll_size, + off_t dt_off_gap, size_t dt_size) +{ + u16 wr_ch =3D pdata->wr_ch_cnt; + u16 rd_ch =3D pdata->rd_ch_cnt; + off_t off; + u16 i; + + off =3D start_off; + + /* Write channel LL region */ + for (i =3D 0; i < wr_ch; i++) { + pdata->ll_wr[i].bar =3D bar; + pdata->ll_wr[i].off =3D off; + pdata->ll_wr[i].sz =3D ll_size; + off +=3D ll_off_gap; + } + + /* Read channel LL region */ + for (i =3D 0; i < rd_ch; i++) { + pdata->ll_rd[i].bar =3D bar; + pdata->ll_rd[i].off =3D off; + pdata->ll_rd[i].sz =3D ll_size; + off +=3D ll_off_gap; + } + + /* Write channel data region */ + for (i =3D 0; i < wr_ch; i++) { + pdata->dt_wr[i].bar =3D bar; + pdata->dt_wr[i].off =3D off; + pdata->dt_wr[i].sz =3D dt_size; + off +=3D dt_off_gap; + } + + /* Read channel data region */ + for (i =3D 0; i < rd_ch; i++) { + pdata->dt_rd[i].bar =3D bar; + pdata->dt_rd[i].off =3D off; + pdata->dt_rd[i].sz =3D dt_size; + off +=3D dt_off_gap; + } +} + static int dw_edma_pcie_irq_vector(struct device *dev, unsigned int nr) { return pci_irq_vector(to_pci_dev(dev), nr); @@ -114,15 +194,15 @@ static const struct dw_edma_plat_ops dw_edma_pcie_pla= t_ops =3D { .pci_address =3D dw_edma_pcie_address, }; =20 -static void dw_edma_pcie_get_vsec_dma_data(struct pci_dev *pdev, - struct dw_edma_pcie_data *pdata) +static void dw_edma_pcie_get_synopsys_dma_data(struct pci_dev *pdev, + struct dw_edma_pcie_data *pdata) { u32 val, map; u16 vsec; u64 off; =20 vsec =3D pci_find_vsec_capability(pdev, PCI_VENDOR_ID_SYNOPSYS, - DW_PCIE_VSEC_DMA_ID); + DW_PCIE_SYNOPSYS_VSEC_DMA_ID); if (!vsec) return; =20 @@ -131,9 +211,9 @@ static void dw_edma_pcie_get_vsec_dma_data(struct pci_d= ev *pdev, PCI_VNDR_HEADER_LEN(val) !=3D 0x18) return; =20 - pci_dbg(pdev, "Detected PCIe Vendor-Specific Extended Capability DMA\n"); + pci_dbg(pdev, "Detected Synopsys PCIe Vendor-Specific Extended Capability= DMA\n"); pci_read_config_dword(pdev, vsec + 0x8, &val); - map =3D FIELD_GET(DW_PCIE_VSEC_DMA_MAP, val); + map =3D FIELD_GET(DW_PCIE_SYNOPSYS_VSEC_DMA_MAP, val); if (map !=3D EDMA_MF_EDMA_LEGACY && map !=3D EDMA_MF_EDMA_UNROLL && map !=3D EDMA_MF_HDMA_COMPAT && @@ -141,13 +221,13 @@ static void dw_edma_pcie_get_vsec_dma_data(struct pci= _dev *pdev, return; =20 pdata->mf =3D map; - pdata->rg.bar =3D FIELD_GET(DW_PCIE_VSEC_DMA_BAR, val); + pdata->rg.bar =3D FIELD_GET(DW_PCIE_SYNOPSYS_VSEC_DMA_BAR, val); =20 pci_read_config_dword(pdev, vsec + 0xc, &val); pdata->wr_ch_cnt =3D min_t(u16, pdata->wr_ch_cnt, - FIELD_GET(DW_PCIE_VSEC_DMA_WR_CH, val)); + FIELD_GET(DW_PCIE_SYNOPSYS_VSEC_DMA_WR_CH, val)); pdata->rd_ch_cnt =3D min_t(u16, pdata->rd_ch_cnt, - FIELD_GET(DW_PCIE_VSEC_DMA_RD_CH, val)); + FIELD_GET(DW_PCIE_SYNOPSYS_VSEC_DMA_RD_CH, val)); =20 pci_read_config_dword(pdev, vsec + 0x14, &val); off =3D val; @@ -157,6 +237,64 @@ static void dw_edma_pcie_get_vsec_dma_data(struct pci_= dev *pdev, pdata->rg.off =3D off; } =20 +static void dw_edma_pcie_get_xilinx_dma_data(struct pci_dev *pdev, + struct dw_edma_pcie_data *pdata) +{ + u32 val, map; + u16 vsec; + u64 off; + + pdata->devmem_phys_off =3D DW_PCIE_XILINX_MDB_INVALID_ADDR; + + vsec =3D pci_find_vsec_capability(pdev, PCI_VENDOR_ID_XILINX, + DW_PCIE_XILINX_MDB_VSEC_DMA_ID); + if (!vsec) + return; + + pci_read_config_dword(pdev, vsec + PCI_VNDR_HEADER, &val); + if (PCI_VNDR_HEADER_REV(val) !=3D 0x00 || + PCI_VNDR_HEADER_LEN(val) !=3D 0x18) + return; + + pci_dbg(pdev, "Detected Xilinx PCIe Vendor-Specific Extended Capability D= MA\n"); + pci_read_config_dword(pdev, vsec + 0x8, &val); + map =3D FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_MAP, val); + if (map !=3D EDMA_MF_HDMA_NATIVE) + return; + + pdata->mf =3D map; + pdata->rg.bar =3D FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_BAR, val); + + pci_read_config_dword(pdev, vsec + 0xc, &val); + pdata->wr_ch_cnt =3D min_t(u16, pdata->wr_ch_cnt, + FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_WR_CH, val)); + pdata->rd_ch_cnt =3D min_t(u16, pdata->rd_ch_cnt, + FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_RD_CH, val)); + + pci_read_config_dword(pdev, vsec + 0x14, &val); + off =3D val; + pci_read_config_dword(pdev, vsec + 0x10, &val); + off <<=3D 32; + off |=3D val; + pdata->rg.off =3D off; + + vsec =3D pci_find_vsec_capability(pdev, PCI_VENDOR_ID_XILINX, + DW_PCIE_XILINX_MDB_VSEC_ID); + if (!vsec) + return; + + pci_read_config_dword(pdev, + vsec + DW_PCIE_XILINX_MDB_DEVMEM_OFF_REG_HIGH, + &val); + off =3D val; + pci_read_config_dword(pdev, + vsec + DW_PCIE_XILINX_MDB_DEVMEM_OFF_REG_LOW, + &val); + off <<=3D 32; + off |=3D val; + pdata->devmem_phys_off =3D off; +} + static int dw_edma_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *pid) { @@ -184,7 +322,29 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, * Tries to find if exists a PCIe Vendor-Specific Extended Capability * for the DMA, if one exists, then reconfigures it. */ - dw_edma_pcie_get_vsec_dma_data(pdev, vsec_data); + dw_edma_pcie_get_synopsys_dma_data(pdev, vsec_data); + + if (pdev->vendor =3D=3D PCI_VENDOR_ID_XILINX) { + dw_edma_pcie_get_xilinx_dma_data(pdev, vsec_data); + + /* + * There is no valid address found for the LL memory + * space on the device side. + */ + if (vsec_data->devmem_phys_off =3D=3D DW_PCIE_XILINX_MDB_INVALID_ADDR) + return -ENOMEM; + + /* + * Configure the channel LL and data blocks if number of + * channels enabled in VSEC capability are more than the + * channels configured in xilinx_mdb_data. + */ + dw_edma_set_chan_region_offset(vsec_data, BAR_2, 0, + DW_PCIE_XILINX_MDB_LL_OFF_GAP, + DW_PCIE_XILINX_MDB_LL_SIZE, + DW_PCIE_XILINX_MDB_DT_OFF_GAP, + DW_PCIE_XILINX_MDB_DT_SIZE); + } =20 /* Mapping PCI BAR regions */ mask =3D BIT(vsec_data->rg.bar); @@ -367,6 +527,8 @@ static void dw_edma_pcie_remove(struct pci_dev *pdev) =20 static const struct pci_device_id dw_edma_pcie_id_table[] =3D { { PCI_DEVICE_DATA(SYNOPSYS, EDDA, &snps_edda_data) }, + { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_XILINX_B054), + (kernel_ulong_t)&xilinx_mdb_data }, { } }; MODULE_DEVICE_TABLE(pci, dw_edma_pcie_id_table); --=20 2.43.0 From nobody Sat Feb 7 11:30:57 2026 Received: from PH8PR06CU001.outbound.protection.outlook.com (mail-westus3azon11012023.outbound.protection.outlook.com [40.107.209.23]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4AF99396D38; Wed, 4 Feb 2026 10:49:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.209.23 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770202192; cv=fail; b=WQrkGxqwnyyWTH2nL08fCd5NKo5klAoEhn/s+iSu5zPU3duI+cmoxN8XDeBd1G8lbuVzX/5hkUVVZabrgGc/vt3qc0iPFwB+V0cB6ldzIB85rTkknbJZhGLQ5tmLNDuhZ8Z4yiqKmYTGpxEhLO+ees49ryr5+Ck/T2hpUIrgdyM= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770202192; c=relaxed/simple; bh=cVBy2T2l/CYFXcuiALH39gtIvId9XDuEfxcEAx/Nf4I=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=n61H0LHunyenC5MZx164/5QiMEaNGPtoxaczwPwnyJCqtMk5yZmpZLQysHlZZddTRvytnv8KaY1rJDiqKqgGm376cDyySA7h/QfOIaG/bmJ14P7sTR4jawCg9A8Jrc9Y9GADr/ike+sp+iFBDqa45BjSzz7fqR4r926MlqT7vAg= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=xL58ZYch; arc=fail smtp.client-ip=40.107.209.23 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="xL58ZYch" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=MGs//ES08PugqmLMrPN/ktna2bYmKATxMwjRVhk1K0T2OZzBGTE62jcFjkwjQrnhLwPLR9qme/qGRmYHu5Ou1GrMZBRcFqHTGR91pT2yBkG/+fwuYS/1UI+mysWV4mMRJezqzsy3NmbtnmDc1JuhweOJp9TpcrN8xKIAF6PE36kxtSk34c9QjlpqfH878oxTiFunTk6IsBuCsAPaHkEmXrbeSdFUF/dc9kkj2yMH2ZGcYKH3n6As6ALP++zGphBR5VKMyP9D5Hx0QfRe3h7q91g91aDTnOHLARot7DiB7iAxASxJ0Bz1r3G2Ow9TizYkulD38Avf7TmoPxAVtMCBZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=TAHifbdgUf11x7ADrBrBtfxXXcDrXcJ2MCbbaRQNO/g=; b=UaUN/nv3gmX70oiDCBQWAeiHnR7HXuWL+2TIoK/inFB56q2mPVKRSCMsuJV8sS79IKFw9SlMtELnZS7mHHXoNARpGBIjO/fbkNDX/AbrMVU8PG9vREcTHEizGkxmjIuqLtlswubG8ayl5qYGRtACOs4GVCXQCvkM8uqViRapc50Unky9Wk8Bw+ifX8D9AkoBuAHYRxq/w5NAwkvHKUO9VbHb86Fnq8QSx5qDNr0Lp1zB9ivu56GEi1FkBhtrTEzWbNfTVXlatLsY2InrLQaePNbJ8fi7zhRASZVOX7seYQyionmCWGksOYmiuWCUped0nrnOTXzSBUq820Hv3h2N+g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=google.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=TAHifbdgUf11x7ADrBrBtfxXXcDrXcJ2MCbbaRQNO/g=; b=xL58ZYchnN2RZHp2j87noehzDPvyW+qcwkdTilGHyMmzb4NYTCheZA1oeWhg8R9OeT4sP/ySmGULkzy1s8uDBzJx9wlfuZoQ2J8kXFXUV4CmUPJh8OlAt0gyDcCidio6u89tkZorY6JAlUi9ewK2dNUf6ynbZTnwHs8FkS8nYf8= Received: from SJ0PR05CA0164.namprd05.prod.outlook.com (2603:10b6:a03:339::19) by DM4PR12MB8524.namprd12.prod.outlook.com (2603:10b6:8:18d::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9587.12; Wed, 4 Feb 2026 10:49:47 +0000 Received: from CO1PEPF00012E7F.namprd03.prod.outlook.com (2603:10b6:a03:339:cafe::11) by SJ0PR05CA0164.outlook.office365.com (2603:10b6:a03:339::19) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9587.13 via Frontend Transport; Wed, 4 Feb 2026 10:49:51 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C Received: from satlexmb08.amd.com (165.204.84.17) by CO1PEPF00012E7F.mail.protection.outlook.com (10.167.249.54) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9587.10 via Frontend Transport; Wed, 4 Feb 2026 10:49:46 +0000 Received: from satlexmb07.amd.com (10.181.42.216) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Wed, 4 Feb 2026 04:49:46 -0600 Received: from xhdapps-pcie2.xilinx.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Wed, 4 Feb 2026 02:49:44 -0800 From: Devendra K Verma To: , , CC: , , , , Subject: [PATCH v10 2/2] dmaengine: dw-edma: Add non-LL mode Date: Wed, 4 Feb 2026 16:19:33 +0530 Message-ID: <20260204104933.33179-3-devendra.verma@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260204104933.33179-1-devendra.verma@amd.com> References: <20260204104933.33179-1-devendra.verma@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E7F:EE_|DM4PR12MB8524:EE_ X-MS-Office365-Filtering-Correlation-Id: f64d8e55-118a-4561-d1ad-08de63db1d1d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?AGpHU2K3XBgJZ05xWh21ZEK/NTcXZD8xD3LJee239/mk89NW+OyH4gO+kipY?= =?us-ascii?Q?oycexrG0eXeHfnuqXL29LcaG/bTGTUCbLM4ywqqutbmSG9MI2uUBsLRIwWn0?= =?us-ascii?Q?+MWTyANblp5YOgtn5g4agcXflXlH/7R8pqYuZ9Y1mXmHm9Tkpkn7pT4ig3So?= =?us-ascii?Q?Y3dx7ah8TLB+zdrXL1YflaBvXOyX/oFN6tCbEnzYAlahKOAebOKqxxAmeaIw?= =?us-ascii?Q?vKsGFIauY2gQc4GZiGRPmBiwyDd7+8XE5fNHUFOdkBuqQOQW/kqpkr7YclM1?= =?us-ascii?Q?sOOW721k2gHZ1NQhXoiHP3+mRjIXD6jVxRYEz1y28900/Q49EYElC9z0mqaP?= =?us-ascii?Q?cOJWMyaQivlCgDhIF1di+3lOJl6SIWcpfnCXTAMgSisEu9Dwokk9Qk3TCMkG?= =?us-ascii?Q?5/pPIBSN7uBiZ9llB4luoSe51Vz8HbaLyMHL9e4ZhVbrK8N15grdWBHJIoLT?= =?us-ascii?Q?6wWYkn0GIh1fiASY3MsabGnecp65saXeAqM4Jb8JCBvnn3N2tcceHXolcr59?= =?us-ascii?Q?ykWL8O2w7Y/RJ4W95AM0SUsxszSitTl8XPiNN/pEknZL4wgViGFOTrADo80F?= =?us-ascii?Q?ftwz/lCiKzQs5s0jWgKoWqTVAC8CqyXcN/egD1/KDKgEuu6TvAivwYR+PxVA?= =?us-ascii?Q?fkdNb4s5L8oHkNU1GFYkukQvsBnvIxhmCq5B7Jjr+adZRnyVF+U5hNyHZGuZ?= =?us-ascii?Q?jflevLQEVCR58RtiqDmuk5r2gdu0mSSCNd1++a3f1KaUkZIkf6NMAZGdLmK0?= =?us-ascii?Q?VKAo83M/nsy7MDFwk8G0cF8i+G0ptcQXtrfUpeafEAwStSvDXqoLebknZrPA?= =?us-ascii?Q?d7Na0OQAlVVTRxSiTbf+OKYtm5lrqeJHciRlcp3ew8hj0BgXOHseYzfDvSzQ?= =?us-ascii?Q?hXvV+XbU5TSROXMV2JBW6ll9gbKfzH+1voa3ZRp0KHeSuOIkVyK5sVtc0LNJ?= =?us-ascii?Q?IY03YSdOm1ZU+oYdLErb+R+12j/PFoQyQ/jDN2wYe6TpxA+Cysq9uygvqVzP?= =?us-ascii?Q?MDFH1GnfsuWDjSUuEZiY7McopbFGkfjU51+4eO2s7owZlIP1nl929jIc273G?= =?us-ascii?Q?wMuho3S0jAs7xlbVQcUGNtBVf/uXXyLPN3L85d1SMsVBZ/vq8xqFlw0rx2pv?= =?us-ascii?Q?rtasnAVBEiW2I2qv+Hl/UXmJ1F3f4XRjHpHpvMm9I9GF6FMfnKAxB5ZnOWhl?= =?us-ascii?Q?IocAYHMNRJyyZIi4sajymnvoaKOp/OlryLBrz2c45P41f/9q0BOqsPQQg7FC?= =?us-ascii?Q?mVePBnKuFx4TTPvH3xHIpHBZYFMQ74gLYoWyzoipKaZhqLFqJOu4PwPOYk0L?= =?us-ascii?Q?3PmUijs27Q54FfcluZI526gv2y7B0LSlX4ao2qeDevmDXkPJluXaJDxaDlR3?= =?us-ascii?Q?66uLpvd7CLGjk4MEIOh5zeqY2URBrE7lFRer6HDINdgqE4aPg315DQRhYJF1?= =?us-ascii?Q?FNNEXt+japSg80Xj9xMIsCTbOb5X9CJBkeBcF/ovRNfmaVi02VLEJGz2qgRm?= =?us-ascii?Q?o3yMogoJy9hMXi+yjhFvtPJ3wysMkOFXHpRSfCrHhuyXXN9nbbmrlMoXTGLs?= =?us-ascii?Q?T6/qUI+XG9Vne7Oi7AcQ8MVtbQ/lCS8hxi3Zlz+vWVq+1gOHoheS2OJfu8pJ?= =?us-ascii?Q?4PFYuShwOY1JwBwI/RbCAKkclvpUP02jd4TkJXb7S4dJTc+GDntXazRMxO21?= =?us-ascii?Q?V/SeXA=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: DF59NAsSw+y23ara2RP4d93w3vMCl2NMNf0j7iRJ1awuf/CfnOEcS+NjVMjAPT0QaqvonU8vXdNG/jfeXfABr+zo1ynBcNurhMH9DUJMuW3S8ccaXMREB/l/NohOyr3/pJBLwRL8h39C5EcIVHstG4+NwC8blCde9DI8c0uV3AS9B2PuEXVIAplDV3RvLSrjoeyGgjz4z4luZhJ1hrx+sBUDGmatiH0ei1r+4SAZjk/azskpruVQ5x35GMsgj7U8OsaCPwFv9a/+IqD9FworvCuE/mYkeqCBfFfIShw7uJoMSeqBKPiTxVAzD55wKXQisD+On/iiaq7GAtnAtF5Gwrt9fA2xrwXWXUAv6rxukZZ0jyPvMF6ITFX6upiNnRMs4oELxFs1g0YOTKzIee+UJyq5wMj569/oFzExgZ9cy+a4wlFK/XCNG/uuasHoiBcI X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Feb 2026 10:49:46.9886 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f64d8e55-118a-4561-d1ad-08de63db1d1d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E7F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB8524 Content-Type: text/plain; charset="utf-8" AMD MDB IP supports Linked List (LL) mode as well as non-LL mode. The current code does not have the mechanisms to enable the DMA transactions using the non-LL mode. The following two cases are added with this patch: - For the AMD (Xilinx) only, when a valid physical base address of the device side DDR is not configured, then the IP can still be used in non-LL mode. For all the channels DMA transactions will be using the non-LL mode only. This, the default non-LL mode, is not applicable for Synopsys IP with the current code addition. - If the default mode is LL-mode, for both AMD (Xilinx) and Synosys, and if user wants to use non-LL mode then user can do so via configuring the peripheral_config param of dma_slave_config. Signed-off-by: Devendra K Verma --- Changes in v10 Added the peripheral_config check only for HDMA IP in dw_edma_device_config(). Replaced the loop with single entry retrieval for non-LL mode. Addressed review comments and handled the burst allocation by defining 'bursts_max' as per suggestions. Changes in v9 Fixed compilation errors related to macro name mismatch. Changes in v8 Cosmetic change related to comment and code. Changes in v7 No change Changes in v6 Gave definition to bits used for channel configuration. Removed the comment related to doorbell. Changes in v5 Variable name 'nollp' changed to 'non_ll'. In the dw_edma_device_config() WARN_ON replaced with dev_err(). Comments follow the 80-column guideline. Changes in v4 No change Changes in v3 No change Changes in v2 Reverted the function return type to u64 for dw_edma_get_phys_addr(). Changes in v1 Changed the function return type for dw_edma_get_phys_addr(). Corrected the typo raised in review. --- drivers/dma/dw-edma/dw-edma-core.c | 35 ++++++++++++++- drivers/dma/dw-edma/dw-edma-core.h | 1 + drivers/dma/dw-edma/dw-edma-pcie.c | 44 ++++++++++++------ drivers/dma/dw-edma/dw-hdma-v0-core.c | 65 ++++++++++++++++++++++++++- drivers/dma/dw-edma/dw-hdma-v0-regs.h | 1 + include/linux/dma/edma.h | 1 + 6 files changed, 132 insertions(+), 15 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-ed= ma-core.c index b43255f914f3..ef3d79a9f88d 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -223,6 +223,31 @@ static int dw_edma_device_config(struct dma_chan *dcha= n, struct dma_slave_config *config) { struct dw_edma_chan *chan =3D dchan2dw_edma_chan(dchan); + int non_ll =3D 0; + + chan->non_ll =3D false; + if (chan->dw->chip->mf =3D=3D EDMA_MF_HDMA_NATIVE) { + if (config->peripheral_config && + config->peripheral_size !=3D sizeof(int)) { + dev_err(dchan->device->dev, + "config param peripheral size mismatch\n"); + return -EINVAL; + } + + /* + * When there is no valid LLP base address available then the + * default DMA ops will use the non-LL mode. + * + * Cases where LL mode is enabled and client wants to use the + * non-LL mode then also client can do so via providing the + * peripheral_config param. + */ + if (config->peripheral_config) + non_ll =3D *(int *)config->peripheral_config; + + if (chan->dw->chip->non_ll || (!chan->dw->chip->non_ll && non_ll)) + chan->non_ll =3D true; + } =20 memcpy(&chan->config, config, sizeof(*config)); chan->configured =3D true; @@ -358,6 +383,7 @@ dw_edma_device_transfer(struct dw_edma_transfer *xfer) struct dw_edma_desc *desc; u64 src_addr, dst_addr; size_t fsz =3D 0; + u32 bursts_max; u32 cnt =3D 0; int i; =20 @@ -415,6 +441,13 @@ dw_edma_device_transfer(struct dw_edma_transfer *xfer) return NULL; } =20 + /* + * For non-LL mode, only a single burst can be handled + * in a single chunk unlike LL mode where multiple bursts + * can be configured in a single chunk. + */ + bursts_max =3D chan->non_ll ? 1 : chan->ll_max; + desc =3D dw_edma_alloc_desc(chan); if (unlikely(!desc)) goto err_alloc; @@ -450,7 +483,7 @@ dw_edma_device_transfer(struct dw_edma_transfer *xfer) if (xfer->type =3D=3D EDMA_XFER_SCATTER_GATHER && !sg) break; =20 - if (chunk->bursts_alloc =3D=3D chan->ll_max) { + if (chunk->bursts_alloc =3D=3D bursts_max) { chunk =3D dw_edma_alloc_chunk(desc); if (unlikely(!chunk)) goto err_alloc; diff --git a/drivers/dma/dw-edma/dw-edma-core.h b/drivers/dma/dw-edma/dw-ed= ma-core.h index 71894b9e0b15..c8e3d196a549 100644 --- a/drivers/dma/dw-edma/dw-edma-core.h +++ b/drivers/dma/dw-edma/dw-edma-core.h @@ -86,6 +86,7 @@ struct dw_edma_chan { u8 configured; =20 struct dma_slave_config config; + bool non_ll; }; =20 struct dw_edma_irq { diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-ed= ma-pcie.c index 3aefc48f8e0a..94621b0f87df 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -295,6 +295,15 @@ static void dw_edma_pcie_get_xilinx_dma_data(struct pc= i_dev *pdev, pdata->devmem_phys_off =3D off; } =20 +static u64 dw_edma_get_phys_addr(struct pci_dev *pdev, + struct dw_edma_pcie_data *pdata, + enum pci_barno bar) +{ + if (pdev->vendor =3D=3D PCI_VENDOR_ID_XILINX) + return pdata->devmem_phys_off; + return pci_bus_address(pdev, bar); +} + static int dw_edma_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *pid) { @@ -304,6 +313,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, struct dw_edma_chip *chip; int err, nr_irqs; int i, mask; + bool non_ll =3D false; =20 vsec_data =3D kmalloc(sizeof(*vsec_data), GFP_KERNEL); if (!vsec_data) @@ -329,21 +339,24 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, =20 /* * There is no valid address found for the LL memory - * space on the device side. + * space on the device side. In the absence of LL base + * address use the non-LL mode or simple mode supported by + * the HDMA IP. */ if (vsec_data->devmem_phys_off =3D=3D DW_PCIE_XILINX_MDB_INVALID_ADDR) - return -ENOMEM; + non_ll =3D true; =20 /* * Configure the channel LL and data blocks if number of * channels enabled in VSEC capability are more than the * channels configured in xilinx_mdb_data. */ - dw_edma_set_chan_region_offset(vsec_data, BAR_2, 0, - DW_PCIE_XILINX_MDB_LL_OFF_GAP, - DW_PCIE_XILINX_MDB_LL_SIZE, - DW_PCIE_XILINX_MDB_DT_OFF_GAP, - DW_PCIE_XILINX_MDB_DT_SIZE); + if (!non_ll) + dw_edma_set_chan_region_offset(vsec_data, BAR_2, 0, + DW_PCIE_XILINX_MDB_LL_OFF_GAP, + DW_PCIE_XILINX_MDB_LL_SIZE, + DW_PCIE_XILINX_MDB_DT_OFF_GAP, + DW_PCIE_XILINX_MDB_DT_SIZE); } =20 /* Mapping PCI BAR regions */ @@ -391,6 +404,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, chip->mf =3D vsec_data->mf; chip->nr_irqs =3D nr_irqs; chip->ops =3D &dw_edma_pcie_plat_ops; + chip->non_ll =3D non_ll; =20 chip->ll_wr_cnt =3D vsec_data->wr_ch_cnt; chip->ll_rd_cnt =3D vsec_data->rd_ch_cnt; @@ -399,7 +413,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, if (!chip->reg_base) return -ENOMEM; =20 - for (i =3D 0; i < chip->ll_wr_cnt; i++) { + for (i =3D 0; i < chip->ll_wr_cnt && !non_ll; i++) { struct dw_edma_region *ll_region =3D &chip->ll_region_wr[i]; struct dw_edma_region *dt_region =3D &chip->dt_region_wr[i]; struct dw_edma_block *ll_block =3D &vsec_data->ll_wr[i]; @@ -410,7 +424,8 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, return -ENOMEM; =20 ll_region->vaddr.io +=3D ll_block->off; - ll_region->paddr =3D pci_bus_address(pdev, ll_block->bar); + ll_region->paddr =3D dw_edma_get_phys_addr(pdev, vsec_data, + ll_block->bar); ll_region->paddr +=3D ll_block->off; ll_region->sz =3D ll_block->sz; =20 @@ -419,12 +434,13 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, return -ENOMEM; =20 dt_region->vaddr.io +=3D dt_block->off; - dt_region->paddr =3D pci_bus_address(pdev, dt_block->bar); + dt_region->paddr =3D dw_edma_get_phys_addr(pdev, vsec_data, + dt_block->bar); dt_region->paddr +=3D dt_block->off; dt_region->sz =3D dt_block->sz; } =20 - for (i =3D 0; i < chip->ll_rd_cnt; i++) { + for (i =3D 0; i < chip->ll_rd_cnt && !non_ll; i++) { struct dw_edma_region *ll_region =3D &chip->ll_region_rd[i]; struct dw_edma_region *dt_region =3D &chip->dt_region_rd[i]; struct dw_edma_block *ll_block =3D &vsec_data->ll_rd[i]; @@ -435,7 +451,8 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, return -ENOMEM; =20 ll_region->vaddr.io +=3D ll_block->off; - ll_region->paddr =3D pci_bus_address(pdev, ll_block->bar); + ll_region->paddr =3D dw_edma_get_phys_addr(pdev, vsec_data, + ll_block->bar); ll_region->paddr +=3D ll_block->off; ll_region->sz =3D ll_block->sz; =20 @@ -444,7 +461,8 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, return -ENOMEM; =20 dt_region->vaddr.io +=3D dt_block->off; - dt_region->paddr =3D pci_bus_address(pdev, dt_block->bar); + dt_region->paddr =3D dw_edma_get_phys_addr(pdev, vsec_data, + dt_block->bar); dt_region->paddr +=3D dt_block->off; dt_region->sz =3D dt_block->sz; } diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw= -hdma-v0-core.c index e3f8db4fe909..a1b04fec6310 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c @@ -225,7 +225,7 @@ static void dw_hdma_v0_sync_ll_data(struct dw_edma_chun= k *chunk) readl(chunk->ll_region.vaddr.io); } =20 -static void dw_hdma_v0_core_start(struct dw_edma_chunk *chunk, bool first) +static void dw_hdma_v0_core_ll_start(struct dw_edma_chunk *chunk, bool fir= st) { struct dw_edma_chan *chan =3D chunk->chan; struct dw_edma *dw =3D chan->dw; @@ -263,6 +263,69 @@ static void dw_hdma_v0_core_start(struct dw_edma_chunk= *chunk, bool first) SET_CH_32(dw, chan->dir, chan->id, doorbell, HDMA_V0_DOORBELL_START); } =20 +static void dw_hdma_v0_core_non_ll_start(struct dw_edma_chunk *chunk) +{ + struct dw_edma_chan *chan =3D chunk->chan; + struct dw_edma *dw =3D chan->dw; + struct dw_edma_burst *child; + u32 val; + + child =3D list_first_entry_or_null(&chunk->burst->list, + struct dw_edma_burst, list); + if (!child) + return; + + SET_CH_32(dw, chan->dir, chan->id, ch_en, HDMA_V0_CH_EN); + + /* Source address */ + SET_CH_32(dw, chan->dir, chan->id, sar.lsb, + lower_32_bits(child->sar)); + SET_CH_32(dw, chan->dir, chan->id, sar.msb, + upper_32_bits(child->sar)); + + /* Destination address */ + SET_CH_32(dw, chan->dir, chan->id, dar.lsb, + lower_32_bits(child->dar)); + SET_CH_32(dw, chan->dir, chan->id, dar.msb, + upper_32_bits(child->dar)); + + /* Transfer size */ + SET_CH_32(dw, chan->dir, chan->id, transfer_size, child->sz); + + /* Interrupt setup */ + val =3D GET_CH_32(dw, chan->dir, chan->id, int_setup) | + HDMA_V0_STOP_INT_MASK | + HDMA_V0_ABORT_INT_MASK | + HDMA_V0_LOCAL_STOP_INT_EN | + HDMA_V0_LOCAL_ABORT_INT_EN; + + if (!(dw->chip->flags & DW_EDMA_CHIP_LOCAL)) { + val |=3D HDMA_V0_REMOTE_STOP_INT_EN | + HDMA_V0_REMOTE_ABORT_INT_EN; + } + + SET_CH_32(dw, chan->dir, chan->id, int_setup, val); + + /* Channel control setup */ + val =3D GET_CH_32(dw, chan->dir, chan->id, control1); + val &=3D ~HDMA_V0_LINKLIST_EN; + SET_CH_32(dw, chan->dir, chan->id, control1, val); + + SET_CH_32(dw, chan->dir, chan->id, doorbell, + HDMA_V0_DOORBELL_START); +=09 +} + +static void dw_hdma_v0_core_start(struct dw_edma_chunk *chunk, bool first) +{ + struct dw_edma_chan *chan =3D chunk->chan; + + if (chan->non_ll) + dw_hdma_v0_core_non_ll_start(chunk); + else + dw_hdma_v0_core_ll_start(chunk, first); +} + static void dw_hdma_v0_core_ch_config(struct dw_edma_chan *chan) { struct dw_edma *dw =3D chan->dw; diff --git a/drivers/dma/dw-edma/dw-hdma-v0-regs.h b/drivers/dma/dw-edma/dw= -hdma-v0-regs.h index eab5fd7177e5..7759ba9b4850 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-regs.h +++ b/drivers/dma/dw-edma/dw-hdma-v0-regs.h @@ -12,6 +12,7 @@ #include =20 #define HDMA_V0_MAX_NR_CH 8 +#define HDMA_V0_CH_EN BIT(0) #define HDMA_V0_LOCAL_ABORT_INT_EN BIT(6) #define HDMA_V0_REMOTE_ABORT_INT_EN BIT(5) #define HDMA_V0_LOCAL_STOP_INT_EN BIT(4) diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h index 3080747689f6..78ce31b049ae 100644 --- a/include/linux/dma/edma.h +++ b/include/linux/dma/edma.h @@ -99,6 +99,7 @@ struct dw_edma_chip { enum dw_edma_map_format mf; =20 struct dw_edma *dw; + bool non_ll; }; =20 /* Export to the platform drivers */ --=20 2.43.0