From nobody Sun Feb 8 03:27:23 2026 Received: from Atcsqr.andestech.com (exmail.andestech.com [60.248.187.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 326133A1A5B for ; Wed, 4 Feb 2026 09:20:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.187.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770196821; cv=none; b=Z0CWuxAHPOdwImQrbjlFBXAVW6wl/UOLAfek11O+hJi/8BkDvTzYkOEVNz5vFduo8pNVuxUn1RUnB4Q8NXftpWW/5HMNRzxt9ptQ2E6a1cemF8sk5lmaltu3zXTOSvGKZweN0ZEy8eWaFg2/U27HjzTBocsqfSVRph3hJ5iYJeg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770196821; c=relaxed/simple; bh=UMqqYwO7ZEPCcy0QNUQS5EGYse87ClZVTq5yRGDxTo8=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=eQBWIes0Wd1LiSYpKwqJWoL+6eB2U69h0s8IS8nQvXsu2/yF2XRlQFZBJCuxDf9uotmh96Jg8vq238WBdbSsurpadclu2McSLOUKq2A/sHOFgYbYQv5bNBbQrf7oYfyU1NfHtEv2545t+PBnHGc00XWon3NBPfMtPdeEMLy9Bxg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.187.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS34.andestech.com [10.0.1.134]) by Atcsqr.andestech.com with ESMTP id 6149JgsS096272; Wed, 4 Feb 2026 17:19:42 +0800 (+08) (envelope-from minachou@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS34.andestech.com (10.0.1.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 4 Feb 2026 17:19:42 +0800 From: Hui Min Mina Chou To: , , , CC: , , , , Charles Ci-Jyun Wu Subject: [PATCH] perf: andes: support ANDES_CUSTOM_PMU on ARCH_ANDES Date: Wed, 4 Feb 2026 17:18:37 +0800 Message-ID: <20260204091836.1713729-1-minachou@andestech.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: ATCPCS33.andestech.com (10.0.1.100) To ATCPCS34.andestech.com (10.0.1.134) X-DKIM-Results: atcpcs34.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 6149JgsS096272 Content-Type: text/plain; charset="utf-8" From: Charles Ci-Jyun Wu Modify ANDES_CUSTOM_PMU Kconfig dependency to include both ARCH_ANDES and ARCH_RENESAS platforms. Previously, it depended only on ARCH_RENESAS, which prevented PMU IRQ from being enabled correctly on Andes platforms Signed-off-by: Cynthia Huang Signed-off-by: Charles Ci-Jyun Wu --- drivers/perf/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig index 638321fc9800..39e174d36336 100644 --- a/drivers/perf/Kconfig +++ b/drivers/perf/Kconfig @@ -117,7 +117,7 @@ config STARFIVE_STARLINK_PMU =20 config ANDES_CUSTOM_PMU bool "Andes custom PMU support" - depends on ARCH_RENESAS && RISCV_ALTERNATIVE && RISCV_PMU_SBI + depends on (ARCH_ANDES || ARCH_RENESAS) && RISCV_ALTERNATIVE && RISCV_PMU= _SBI default y help The Andes cores implement the PMU overflow extension very --=20 2.34.1