From nobody Mon Feb 9 23:01:49 2026 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5EEBE3E8C67 for ; Wed, 4 Feb 2026 10:46:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770201995; cv=none; b=igpF/mnCvF8j4oJ87mfyud8iPycclWtaQgUSsNzHcI7Yk6qAKvYLmXAbTz/OQyMnY8lEXElitHenPlr7BHtEOKqJs3uubQUwdQgPTXu8lnNaItROiPwiG+ttZ3izjPg+3ekvMUcBTgrgdQoA0pYfkEfcIX7D+82oH1IDZ5Tnscg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770201995; c=relaxed/simple; bh=AwrZ7YchVUGyPsayvgx8rDE/q1Muq6y6xR4ixvM0rbw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=luMeSCy2VaRe4ENhvYETBuQhier4w375mq/Xn9ReTDGNqOCArwWhuT2yBVW/cjrKPEBVMB+2CPAL1WDx8OJw+jgpfPICXksS2mlh2CMIfRsElLpRGOTSB6lPoJPUpdEBU6T+GKLaRF+MZsWmMQ1mqd3rSdSM5f45hpNAx5C2ekQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=uJUA4iBW; arc=none smtp.client-ip=209.85.128.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="uJUA4iBW" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-47f5c2283b6so53618765e9.1 for ; Wed, 04 Feb 2026 02:46:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1770201994; x=1770806794; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=dHH1SSZ1LxnwJw8U4uy1VexmZu4MZlyD0SY5kYnp17U=; b=uJUA4iBWHNDDFmTcIDIVPLsNS3rLcLtKmXmOdG1zesJ39vbKPGsLYE5RVcVNwiBskV P2PnnitcZzqagrkJUatYqIsoAf46G2yDO1c7YWUME12nUYBsryitPOR1SVuVrX7DUp6w m5BU8hoQjxrOP0ateWRZq8JbpLmlwsG9O7xRB9jD0I5Fl+3gx6hVDC+KtsgFeZTFoUw9 Vvv6W912nO2tFwwOkrbT3GP+AMcFKjh7xUNogUlFespw5GA/jCE10t42tCkwerFMmVhr Lk2BSq+/Cwz52or8hKVK4UAqaz3bqFygblIvy+H2NeAKFGaT5bt0ocOg1yBx7KGTxCg2 dyNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770201994; x=1770806794; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=dHH1SSZ1LxnwJw8U4uy1VexmZu4MZlyD0SY5kYnp17U=; b=mGZwCfe9PyBo+Q7SQBUyCaYkl+12aUTOwcLo/Exj/4GAovUqyeSdxheAWqrLhv1z9j MLcWUSWDtm1/NVd2Bu36GKyKqZMeSmvQcOvRKuoRVhO+nIs0w5OL+iLHHBhP95ElT0IL OHb7RDm+8MyMO9a7Ev6fZg2jOy6iSfHwSA8a/do5NLERONhd1CvfY/V6E2RbG4KRtx5g uEUlZ6KOILjQ3PAuDclS8uLGgNugOaoH1oCkljD3hoRY4v1uqtPG7DvCQ14WajpdiP8h Yn9stD7ED1twIzhPM/NpcpkuyO+BdizhV66VuVY3jC1MXRRQimf6lG59obW8fmbxJf6a DPIw== X-Forwarded-Encrypted: i=1; AJvYcCXHd8fZDklL2pigipm3dEZHmX0z7Lg9ZbWp3WJVlRnA6AWLqLgyPf74IYVHYTapmq+eo5Mod0CjFctaj/w=@vger.kernel.org X-Gm-Message-State: AOJu0Yy+FytGSsrjAOxoNUfqzesg0+qISApn2E7tINUnQ32EX1wyZY/P gKgYEaPlBeayGouHdvj3EZnGWTkFXk6Jso50FQURTneofRwzwLmI7VkUq9ZpDlquJEg= X-Gm-Gg: AZuq6aJZNZ1qZpHOqVPljC1ywkylrIrpPEqYB83WxV8wLJvv3ZIDmZPN422QqTaljft AROewVrUNKYt6k7+vICBpg2gxe0sJS3JBU4zKX1XLvK1sAtpFFSZcDHLDxmZUX5uF2/3ax0I/w4 7FPfPu4yxVSuGhoBre4SGEgbqzeHbOAC2X+cM99tW/gBeGME9rZ3J2ivUU/dn7UCvmG6bIPSOAw zT69a8I0qHGqeiBgP8ulD2hLUxPp+lu1nyYLcNv3CeLfLaCSp02Z/iz11+RJsaPD8KxIakD1x8i wEIGIUtUhQJK77pKVkV/GJIANFsoTafeHdHPxuoqaUvg0WcF68TgDvpfjX7e8Q9i+qIh0U9eXB6 vLvhlGCFs/ajTtovzcH6op5kdOPjqFfxf25d45Zt1kkkHU+Qc5D7V1lZgPH9HYXNcfOS0UzCHFk te/jNLXyuw62szM4BFvQQ= X-Received: by 2002:a05:600c:5250:b0:480:3bba:1ca9 with SMTP id 5b1f17b1804b1-4830e922965mr30772945e9.4.1770201993681; Wed, 04 Feb 2026 02:46:33 -0800 (PST) Received: from localhost ([2001:4090:a244:872b:a354:65f3:92a0:8de7]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4830fe86a7bsm15115265e9.8.2026.02.04.02.46.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Feb 2026 02:46:33 -0800 (PST) From: "Markus Schneider-Pargmann (TI.com)" Date: Wed, 04 Feb 2026 11:45:50 +0100 Subject: [PATCH v3 3/3] clocksource/drivers/timer-ti-dm: Add clockevent support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260204-topic-ti-dm-clkevt-v6-16-v3-3-83e65d01f4ae@baylibre.com> References: <20260204-topic-ti-dm-clkevt-v6-16-v3-0-83e65d01f4ae@baylibre.com> In-Reply-To: <20260204-topic-ti-dm-clkevt-v6-16-v3-0-83e65d01f4ae@baylibre.com> To: Daniel Lezcano , Thomas Gleixner Cc: Vishal Mahaveer , Kevin Hilman , Dhruva Gole , Sebin Francis , Kendall Willis , Akashdeep Kaur , linux-kernel@vger.kernel.org, "Markus Schneider-Pargmann (TI.com)" X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6712; i=msp@baylibre.com; h=from:subject:message-id; bh=AwrZ7YchVUGyPsayvgx8rDE/q1Muq6y6xR4ixvM0rbw=; b=owGbwMvMwCXWejAsc4KoVzDjabUkhsxm5frz+szvZFf8ujs5uuha2cdAqcm/5uWm89xTcC+YH bXp78+sjlIWBjEuBlkxRZbOxNC0//I7jyUvWrYZZg4rE8gQBi5OAZjIMVFGht0NMaolUYuqMqcv PN7srRiZp2q5KmxP5q6AMhuOprt7rzL8r3jbJC3XzKvff/eGSvfPne/MNqk5y3M8n8ttMLf7a/A VVgA= X-Developer-Key: i=msp@baylibre.com; a=openpgp; fpr=BADD88DB889FDC3E8A3D5FE612FA6A01E0A45B41 Add support for using the TI Dual-Mode Timer for clockevents. The second always on device with the "ti,timer-alwon" property is selected to be used for clockevents. The first one is used as clocksource. This allows clockevents to be setup independently of the CPU. Signed-off-by: Markus Schneider-Pargmann (TI.com) --- drivers/clocksource/timer-ti-dm.c | 138 ++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 133 insertions(+), 5 deletions(-) diff --git a/drivers/clocksource/timer-ti-dm.c b/drivers/clocksource/timer-= ti-dm.c index 75f38394e2598d76c41dd2b250c0c42f9f48bbe0..cefed71ac243e86e951405e5080= 1239e35abe290 100644 --- a/drivers/clocksource/timer-ti-dm.c +++ b/drivers/clocksource/timer-ti-dm.c @@ -21,8 +21,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -157,7 +159,14 @@ struct dmtimer_clocksource { unsigned int loadval; }; =20 +struct omap_dm_timer_clockevent { + struct clock_event_device dev; + struct dmtimer *timer; + u32 period; +}; + static resource_size_t omap_dm_timer_clocksource_base; +static resource_size_t omap_dm_timer_clockevent_base; static void __iomem *omap_dm_timer_sched_clock_counter; =20 enum { @@ -1201,6 +1210,9 @@ static void omap_dm_timer_find_alwon(void) { struct device_node *np; =20 + if (omap_dm_timer_clocksource_base && omap_dm_timer_clockevent_base) + return; + for_each_matching_node(np, omap_timer_match) { struct resource res; =20 @@ -1213,13 +1225,22 @@ static void omap_dm_timer_find_alwon(void) if (of_address_to_resource(np, 0, &res)) continue; =20 - omap_dm_timer_clocksource_base =3D res.start; + if (!omap_dm_timer_clocksource_base) { + omap_dm_timer_clocksource_base =3D res.start; + continue; + } =20 - of_node_put(np); - return; + if (res.start !=3D omap_dm_timer_clocksource_base) { + omap_dm_timer_clockevent_base =3D res.start; + + of_node_put(np); + return; + } } =20 - omap_dm_timer_clocksource_base =3D RESOURCE_SIZE_MAX; + if (!omap_dm_timer_clocksource_base) + omap_dm_timer_clocksource_base =3D RESOURCE_SIZE_MAX; + omap_dm_timer_clockevent_base =3D RESOURCE_SIZE_MAX; } =20 static struct dmtimer_clocksource *omap_dm_timer_to_clocksource(struct clo= cksource *cs) @@ -1308,6 +1329,105 @@ static int omap_dm_timer_setup_clocksource(struct d= mtimer *timer) return 0; } =20 +static struct omap_dm_timer_clockevent *to_dm_timer_clockevent(struct cloc= k_event_device *evt) +{ + return container_of(evt, struct omap_dm_timer_clockevent, dev); +} + +static int omap_dm_timer_evt_set_next_event(unsigned long cycles, + struct clock_event_device *evt) +{ + struct omap_dm_timer_clockevent *clkevt =3D to_dm_timer_clockevent(evt); + struct dmtimer *timer =3D clkevt->timer; + + dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, 0xffffffff - cycles); + dmtimer_write(timer, OMAP_TIMER_CTRL_REG, OMAP_TIMER_CTRL_ST); + + return 0; +} + +static int omap_dm_timer_evt_shutdown(struct clock_event_device *evt) +{ + struct omap_dm_timer_clockevent *clkevt =3D to_dm_timer_clockevent(evt); + struct dmtimer *timer =3D clkevt->timer; + + __omap_dm_timer_stop(timer); + + return 0; +} + +static int omap_dm_timer_evt_set_periodic(struct clock_event_device *evt) +{ + struct omap_dm_timer_clockevent *clkevt =3D to_dm_timer_clockevent(evt); + struct dmtimer *timer =3D clkevt->timer; + + omap_dm_timer_evt_shutdown(evt); + + omap_dm_timer_set_load(&timer->cookie, clkevt->period); + dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, clkevt->period); + dmtimer_write(timer, OMAP_TIMER_CTRL_REG, + OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST); + + return 0; +} + +static irqreturn_t omap_dm_timer_evt_interrupt(int irq, void *dev_id) +{ + struct omap_dm_timer_clockevent *clkevt =3D dev_id; + struct dmtimer *timer =3D clkevt->timer; + + __omap_dm_timer_write_status(timer, OMAP_TIMER_INT_OVERFLOW); + + clkevt->dev.event_handler(&clkevt->dev); + + return IRQ_HANDLED; +} + +static int omap_dm_timer_setup_clockevent(struct dmtimer *timer) +{ + struct device *dev =3D &timer->pdev->dev; + struct omap_dm_timer_clockevent *clkevt; + int ret; + + clkevt =3D devm_kzalloc(dev, sizeof(*clkevt), GFP_KERNEL); + if (!clkevt) + return -ENOMEM; + + timer->reserved =3D 1; + clkevt->timer =3D timer; + + clkevt->dev.name =3D "omap_dm_timer"; + clkevt->dev.features =3D CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; + clkevt->dev.rating =3D 300; + clkevt->dev.set_next_event =3D omap_dm_timer_evt_set_next_event; + clkevt->dev.set_state_shutdown =3D omap_dm_timer_evt_shutdown; + clkevt->dev.set_state_periodic =3D omap_dm_timer_evt_set_periodic; + clkevt->dev.set_state_oneshot =3D omap_dm_timer_evt_shutdown; + clkevt->dev.set_state_oneshot_stopped =3D omap_dm_timer_evt_shutdown; + clkevt->dev.tick_resume =3D omap_dm_timer_evt_shutdown; + clkevt->dev.cpumask =3D cpu_possible_mask; + clkevt->period =3D 0xffffffff - DIV_ROUND_CLOSEST(timer->fclk_rate, HZ); + + __omap_dm_timer_init_regs(timer); + __omap_dm_timer_stop(timer); + __omap_dm_timer_enable_posted(timer); + + ret =3D devm_request_irq(dev, timer->irq, omap_dm_timer_evt_interrupt, + IRQF_TIMER, "omap_dm_timer_clockevent", clkevt); + if (ret) { + dev_err(dev, "Failed to request interrupt: %d\n", ret); + return ret; + } + + __omap_dm_timer_int_enable(timer, OMAP_TIMER_INT_OVERFLOW); + + clockevents_config_and_register(&clkevt->dev, timer->fclk_rate, + 3, + 0xffffffff); + + return 0; +} + /** * omap_dm_timer_probe - probe function called for every registered device * @pdev: pointer to current timer platform device @@ -1324,7 +1444,7 @@ static int omap_dm_timer_probe(struct platform_device= *pdev) struct resource *res; int ret; =20 - if (!omap_dm_timer_clocksource_base) + if (!omap_dm_timer_clocksource_base || !omap_dm_timer_clockevent_base) omap_dm_timer_find_alwon(); =20 pdata =3D of_device_get_match_data(dev); @@ -1401,6 +1521,14 @@ static int omap_dm_timer_probe(struct platform_devic= e *pdev) =20 res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); =20 + if (omap_dm_timer_clockevent_base && res && + res->start =3D=3D omap_dm_timer_clockevent_base && + !IS_ERR_OR_NULL(timer->fclk)) { + ret =3D omap_dm_timer_setup_clockevent(timer); + if (ret) + return ret; + } + if (omap_dm_timer_clocksource_base && res && res->start =3D=3D omap_dm_timer_clocksource_base && !IS_ERR_OR_NULL(timer->fclk)) { --=20 2.51.0