From nobody Mon Feb 9 09:23:13 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 148C63E9F8D; Wed, 4 Feb 2026 11:25:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770204314; cv=none; b=ID+dLhbg86Vn+alytSjJt6qbVWS+gnQboBBupAoVXSR11SiEF4VCWC4TkvFOfJaPAC1+XPjFCXT+3lJDvMT6oEu/0XAC18/DTOrgEvMYYuc6SMBTc4M3PrKDVH6s7/QAsmG7n/YdudP9KtI4yCYNXPD7USjaqeNxokCb020QomM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770204314; c=relaxed/simple; bh=fNS3C2NaCK+go2nQNBlkD9EyrNNHIb0CZcl2LNOQBmE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RFCX6/7rVL6Ng8mJ3Lrk81rI0DGwZkRDcI3fgwn3IGc9mWgQ0QOeix+I79jbSMZ7rvK2sePQYgfY/xx4FZGxUnBzEoAP/2VxXr0PhIsAjjc6VvRQImPAn9TRvwnT3dTF7KpYwPuHZ4R/rIhEgSO/kJSTSElL8TwLXAul3OPDt3k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=J26tiq+L; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="J26tiq+L" Received: by smtp.kernel.org (Postfix) with ESMTPS id ACD12C19422; Wed, 4 Feb 2026 11:25:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1770204313; bh=fNS3C2NaCK+go2nQNBlkD9EyrNNHIb0CZcl2LNOQBmE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=J26tiq+Ljb3AtXnNJB99YITZHZg9fjBDCPv3EQLSfedawieZD3XoHG1S2zHFcCyDM 2vSZdWg6p/0yABhN7OCv82gJtvecdRjOoU3PrUXhfEHC9cavMzrmKPXpDDTX5liiw/ Q9Os3AV+RfX/1M7/F3XGUX6jcQfpQpbFp1o0FP57Ukjsv3Ib4BFjLIkfd+YKuWHqyn 197W+RVZpv3u8IHt7fGhfFAMYwC4mCvdlOm2yyk/8KjX0O6bbcXpBtoJiwrmkxX6mW vyX94eTTxS2R0IKS4nyOWG+WJDIP3UL7g7sGWTQ20gxGF36FiM681OmtPKZvWxK3mT /bM9vGabtcd1Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9815CE95387; Wed, 4 Feb 2026 11:25:13 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 04 Feb 2026 15:25:07 +0400 Subject: [PATCH v20 1/6] dt-bindings: pwm: add IPQ6018 binding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260204-ipq-pwm-v20-1-91733011a3d1@outlook.com> References: <20260204-ipq-pwm-v20-0-91733011a3d1@outlook.com> In-Reply-To: <20260204-ipq-pwm-v20-0-91733011a3d1@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Devi Priya , Baruch Siach , Bjorn Andersson , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770204310; l=2042; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=8ayVJ9z0kZoRdShrug1dJ1pjUonk4k9SO1yJzG93fMg=; b=Xjogr+JBgSkj89dNR4lbs5wwt6nsNiNMDvn77RW9Yq0JwjKTIcdlGeTUm+BDrkRqR9AbDA8fu Kl+vV+XspZnDtLSaskiEusMKhlrcWkFb9Dp6t0Rq7/3x+E1nCRvaS/P X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: Devi Priya DT binding for the PWM block in Qualcomm IPQ6018 SoC. Reviewed-by: Bjorn Andersson Reviewed-by: Krzysztof Kozlowski Co-developed-by: Baruch Siach Signed-off-by: Baruch Siach Signed-off-by: Devi Priya Signed-off-by: George Moussalem --- .../devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml | 51 ++++++++++++++++++= ++++ 1 file changed, 51 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml b/= Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml new file mode 100644 index 0000000000000000000000000000000000000000..f9f1f652e7527bc8fb3d5fad51b= 0057ea53b3766 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/qcom,ipq6018-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ6018 PWM controller + +maintainers: + - George Moussalem + +properties: + compatible: + oneOf: + - items: + - enum: + - qcom,ipq5018-pwm + - qcom,ipq5332-pwm + - qcom,ipq9574-pwm + - const: qcom,ipq6018-pwm + - const: qcom,ipq6018-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#pwm-cells": + const: 3 + +required: + - compatible + - reg + - clocks + - "#pwm-cells" + +additionalProperties: false + +examples: + - | + #include + + pwm: pwm@1941010 { + compatible =3D "qcom,ipq6018-pwm"; + reg =3D <0x01941010 0x20>; + clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates =3D <100000000>; + #pwm-cells =3D <3>; + }; --=20 2.52.0 From nobody Mon Feb 9 09:23:13 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1653D3E9F8E; Wed, 4 Feb 2026 11:25:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770204314; cv=none; b=G3d0Ri0xw7F/u2rUoaF2eprL1ihrTvDSfCszkp2ciK2Y+UB3YSBt1K9D5nrbQw3bG1mHFZSO34nH/NZUQUoP97w8cJNILcVALgdGNfpM1vdDsKcRjomVZOvJi5sTvm2qnS4gIzL5DhybGv6UMOPcMrPM4TyZjpnvnJyWo9twGXE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770204314; c=relaxed/simple; bh=DlyTmDysGY1XB33v65FxlGZh2bVxvGJcWBwNBttMHy4=; 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Wed, 4 Feb 2026 11:25:13 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 04 Feb 2026 15:25:08 +0400 Subject: [PATCH v20 2/6] pwm: driver for qualcomm ipq6018 pwm block Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260204-ipq-pwm-v20-2-91733011a3d1@outlook.com> References: <20260204-ipq-pwm-v20-0-91733011a3d1@outlook.com> In-Reply-To: <20260204-ipq-pwm-v20-0-91733011a3d1@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Devi Priya , Baruch Siach X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770204310; l=9677; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=lqVC0W9FHdaTi1eT81frsdr/MvrSo0xMFV72k7YrO7I=; b=mcjrEkuzodOMpsOdLZkQ609EXbJZFxJ8sU8yRwppwYWMDGETj4y5NtRIMVLi7GxOiU0zqcWls CZHLZJaNDRaCaTzN1DMBfmpBhwkY/Hu+GKk+Nh9uBfpU2UxvCU4SSmG X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: Devi Priya Driver for the PWM block in Qualcomm IPQ6018 line of SoCs. Based on driver from downstream Codeaurora kernel tree. Removed support for older (V1) variants because I have no access to that hardware. Tested on IPQ5018 and IPQ6010 based hardware. Co-developed-by: Baruch Siach Signed-off-by: Baruch Siach Signed-off-by: Devi Priya Reviewed-by: Bjorn Andersson Signed-off-by: George Moussalem --- --- drivers/pwm/Kconfig | 12 +++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-ipq.c | 239 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 252 insertions(+) diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 6f3147518376a04b6e890c4bf31e06e1af04054e..e8886a9b64d9689d86920cc0d89= 7231a1cfc06cc 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -347,6 +347,18 @@ config PWM_INTEL_LGM To compile this driver as a module, choose M here: the module will be called pwm-intel-lgm. =20 +config PWM_IPQ + tristate "IPQ PWM support" + depends on ARCH_QCOM || COMPILE_TEST + depends on HAVE_CLK && HAS_IOMEM + help + Generic PWM framework driver for IPQ PWM block which supports + 4 pwm channels. Each of the these channels can be configured + independent of each other. + + To compile this driver as a module, choose M here: the module + will be called pwm-ipq. + config PWM_IQS620A tristate "Azoteq IQS620A PWM support" depends on MFD_IQS62X || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 0dc0d2b69025dbd27013285cd335d3cb1ca2ab3f..5630a521a7cffeb83ff8c8960e1= 5eb23ddb1c9f8 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_PWM_IMX1) +=3D pwm-imx1.o obj-$(CONFIG_PWM_IMX27) +=3D pwm-imx27.o obj-$(CONFIG_PWM_IMX_TPM) +=3D pwm-imx-tpm.o obj-$(CONFIG_PWM_INTEL_LGM) +=3D pwm-intel-lgm.o +obj-$(CONFIG_PWM_IPQ) +=3D pwm-ipq.o obj-$(CONFIG_PWM_IQS620A) +=3D pwm-iqs620a.o obj-$(CONFIG_PWM_JZ4740) +=3D pwm-jz4740.o obj-$(CONFIG_PWM_KEEMBAY) +=3D pwm-keembay.o diff --git a/drivers/pwm/pwm-ipq.c b/drivers/pwm/pwm-ipq.c new file mode 100644 index 0000000000000000000000000000000000000000..b944ecb456d59ecef1f59eb865c= c3cc90cd82244 --- /dev/null +++ b/drivers/pwm/pwm-ipq.c @@ -0,0 +1,239 @@ +// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 +/* + * Copyright (c) 2016-2017, 2020 The Linux Foundation. All rights reserved. + * + * Hardware notes / Limitations: + * - The PWM controller has no publicly available datasheet. + * - Each of the four channels is programmed via two 32-bit registers + * (REG0 and REG1 at 8-byte stride). + * - Period and duty-cycle reconfiguration is fully atomic: new divider, + * pre-divider, and high-duration values are latched by setting the + * UPDATE bit (bit 30 in REG1). The hardware applies the new settings + * at the beginning of the next period without disabling the output, + * so the currently running period is always completed. + * - On disable (clearing the ENABLE bit 31 in REG1), the hardware + * finishes the current period before stopping the output. The pin + * is then driven to the inactive (low) level. + * - Upon disabling, the hardware resets the pre-divider (PRE_DIV) and div= ider + * fields (PWM_DIV) in REG0 and REG1 to 0x0000 and 0x0001 respectively. + * - Only normal polarity is supported. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* The frequency range supported is 1 Hz to clock rate */ +#define IPQ_PWM_MAX_PERIOD_NS ((u64)NSEC_PER_SEC) + +/* + * Two 32-bit registers for each PWM: REG0, and REG1. + * Base offset for PWM #i is at 8 * #i. + */ +#define IPQ_PWM_REG0 0 +#define IPQ_PWM_REG0_PWM_DIV GENMASK(15, 0) +#define IPQ_PWM_REG0_HI_DURATION GENMASK(31, 16) + +#define IPQ_PWM_REG1 4 +#define IPQ_PWM_REG1_PRE_DIV GENMASK(15, 0) + +/* + * The max value specified for each field is based on the number of bits + * in the pwm control register for that field (16-bit) + */ +#define IPQ_PWM_MAX_DIV FIELD_MAX(IPQ_PWM_REG0_PWM_DIV) + +/* + * Enable bit is set to enable output toggling in pwm device. + * Update bit is set to trigger the change and is unset automatically + * to reflect the changed divider and high duration values in register. + */ +#define IPQ_PWM_REG1_UPDATE BIT(30) +#define IPQ_PWM_REG1_ENABLE BIT(31) + +struct ipq_pwm_chip { + void __iomem *mem; + unsigned long clk_rate; +}; + +static struct ipq_pwm_chip *ipq_pwm_from_chip(struct pwm_chip *chip) +{ + return pwmchip_get_drvdata(chip); +} + +static unsigned int ipq_pwm_reg_read(struct pwm_device *pwm, unsigned int = reg) +{ + struct ipq_pwm_chip *ipq_chip =3D ipq_pwm_from_chip(pwm->chip); + unsigned int off =3D 8 * pwm->hwpwm + reg; + + return readl(ipq_chip->mem + off); +} + +static void ipq_pwm_reg_write(struct pwm_device *pwm, unsigned int reg, + unsigned int val) +{ + struct ipq_pwm_chip *ipq_chip =3D ipq_pwm_from_chip(pwm->chip); + unsigned int off =3D 8 * pwm->hwpwm + reg; + + writel(val, ipq_chip->mem + off); +} + +static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct ipq_pwm_chip *ipq_chip =3D ipq_pwm_from_chip(chip); + unsigned int pre_div, pwm_div; + u64 period_ns, duty_ns; + unsigned long val =3D 0; + unsigned long hi_dur; + + if (state->polarity !=3D PWM_POLARITY_NORMAL) + return -EINVAL; + + if (!ipq_chip->clk_rate) + return -EINVAL; + + if (state->period < DIV64_U64_ROUND_UP(NSEC_PER_SEC, + ipq_chip->clk_rate)) + return -ERANGE; + + period_ns =3D min(state->period, IPQ_PWM_MAX_PERIOD_NS); + duty_ns =3D min(state->duty_cycle, period_ns); + + pwm_div =3D IPQ_PWM_MAX_DIV - 1; + pre_div =3D mul_u64_u64_div_u64(period_ns, ipq_chip->clk_rate, + (u64)NSEC_PER_SEC * (pwm_div + 1)); + pre_div =3D (pre_div > 0) ? pre_div - 1 : 0; + + if (pre_div > IPQ_PWM_MAX_DIV) + pre_div =3D IPQ_PWM_MAX_DIV; + + /* + * high duration =3D pwm duty * (pwm div + 1) + * pwm duty =3D duty_ns / period_ns + */ + hi_dur =3D mul_u64_u64_div_u64(duty_ns, ipq_chip->clk_rate, + (u64)(pre_div + 1) * NSEC_PER_SEC); + + val =3D FIELD_PREP(IPQ_PWM_REG0_HI_DURATION, hi_dur) | + FIELD_PREP(IPQ_PWM_REG0_PWM_DIV, pwm_div); + ipq_pwm_reg_write(pwm, IPQ_PWM_REG0, val); + + val =3D FIELD_PREP(IPQ_PWM_REG1_PRE_DIV, pre_div); + ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val); + + /* PWM enable toggle needs a separate write to REG1 */ + val |=3D IPQ_PWM_REG1_UPDATE; + if (state->enabled) + val |=3D IPQ_PWM_REG1_ENABLE; + ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val); + + return 0; +} + +static int ipq_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct ipq_pwm_chip *ipq_chip =3D ipq_pwm_from_chip(chip); + unsigned int pre_div, pwm_div, hi_dur; + u64 effective_div, hi_div; + u32 reg0, reg1; + + reg1 =3D ipq_pwm_reg_read(pwm, IPQ_PWM_REG1); + state->enabled =3D reg1 & IPQ_PWM_REG1_ENABLE; + + if (!state->enabled) + return 0; + + reg0 =3D ipq_pwm_reg_read(pwm, IPQ_PWM_REG0); + + state->polarity =3D PWM_POLARITY_NORMAL; + + pwm_div =3D FIELD_GET(IPQ_PWM_REG0_PWM_DIV, reg0); + hi_dur =3D FIELD_GET(IPQ_PWM_REG0_HI_DURATION, reg0); + pre_div =3D FIELD_GET(IPQ_PWM_REG1_PRE_DIV, reg1); + + effective_div =3D (u64)(pre_div + 1) * (pwm_div + 1); + state->period =3D DIV64_U64_ROUND_UP(effective_div * NSEC_PER_SEC, + ipq_chip->clk_rate); + + hi_div =3D hi_dur * (pre_div + 1); + state->duty_cycle =3D DIV64_U64_ROUND_UP(hi_div * NSEC_PER_SEC, + ipq_chip->clk_rate); + + /* + * ensure a valid config is passed back to PWM core in case duty_cycle + * is > period (>100%) + */ + state->duty_cycle =3D min(state->duty_cycle, state->period); + + return 0; +} + +static const struct pwm_ops ipq_pwm_ops =3D { + .apply =3D ipq_pwm_apply, + .get_state =3D ipq_pwm_get_state, +}; + +static int ipq_pwm_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct ipq_pwm_chip *pwm; + struct pwm_chip *chip; + struct clk *clk; + int ret; + + chip =3D devm_pwmchip_alloc(dev, 4, sizeof(*pwm)); + if (IS_ERR(chip)) + return PTR_ERR(chip); + pwm =3D ipq_pwm_from_chip(chip); + + pwm->mem =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pwm->mem)) + return dev_err_probe(dev, PTR_ERR(pwm->mem), + "Failed to acquire resource\n"); + + clk =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "Failed to get clock\n"); + + ret =3D devm_clk_rate_exclusive_get(dev, clk); + if (ret) + return dev_err_probe(dev, ret, "Failed to lock clock rate\n"); + + pwm->clk_rate =3D clk_get_rate(clk); + + chip->ops =3D &ipq_pwm_ops; + + ret =3D devm_pwmchip_add(dev, chip); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to add pwm chip\n"); + + return 0; +} + +static const struct of_device_id pwm_ipq_dt_match[] =3D { + { .compatible =3D "qcom,ipq6018-pwm", }, + {} +}; +MODULE_DEVICE_TABLE(of, pwm_ipq_dt_match); + +static struct platform_driver ipq_pwm_driver =3D { + .driver =3D { + .name =3D "ipq-pwm", + .of_match_table =3D pwm_ipq_dt_match, + }, + .probe =3D ipq_pwm_probe, +}; + +module_platform_driver(ipq_pwm_driver); + +MODULE_LICENSE("GPL"); --=20 2.52.0 From nobody Mon Feb 9 09:23:13 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29E453E9F95; Wed, 4 Feb 2026 11:25:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770204314; cv=none; b=FQrdkbPolPC9uaiM5fh29gNLQu3/qx9WqxVH9jxsIRIfM43UJXALVFUwK79rSRQcVoKtXKl+qfKxpy5BjP3nbwHq2saFYVZtiU29MvnY8fpJ9jgTmLEH840dmVa5sC89+pAXdCRf8hirt0beLYgTlVqZpHH5PqXFPHxQfD5IssU= ARC-Message-Signature: i=1; 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a=ed25519-sha256; t=1770204310; l=1391; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=P5CK/w1B6zAAyU8rGtps6nkSbcs6bEiQ8DwAdl5cL3U=; b=04A42mmVBJT3kjk2PUBEFzzqRlKBDsj8FXbDrfcY52Y0oM6+k/DeDobRm16ryGbr4W/H5M/oo WlY8lleqi2QD8C3Pd5nOynNCuQt2RHHWoWfL4QTyfI1l2QIL3MGcKrl X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: Devi Priya Describe the PWM block on IPQ6018. Although PWM is in the TCSR area, make pwm its own node as simple-mfd has been removed from the bindings and as such hardware components should have its own node. Reviewed-by: Krzysztof Kozlowski Co-developed-by: Baruch Siach Signed-off-by: Baruch Siach Signed-off-by: Devi Priya Signed-off-by: George Moussalem Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qc= om/ipq6018.dtsi index 40f1c262126eff3761430a47472b52d27f961040..7866844cc09fd2c2c2f512ce2c8= fa7826fabc7aa 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -413,6 +413,16 @@ tcsr: syscon@1937000 { reg =3D <0x0 0x01937000 0x0 0x21000>; }; =20 + pwm: pwm@1941010 { + compatible =3D "qcom,ipq6018-pwm"; + reg =3D <0x0 0x01941010 0x0 0x20>; + clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates =3D <100000000>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + usb2: usb@70f8800 { compatible =3D "qcom,ipq6018-dwc3", "qcom,dwc3"; reg =3D <0x0 0x070f8800 0x0 0x400>; --=20 2.52.0 From nobody Mon Feb 9 09:23:13 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B2583E9F96; Wed, 4 Feb 2026 11:25:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770204314; cv=none; b=R8K1lFrgH0ERmaruDZoq0xRAFofSLX0AF9w5PDcgkBJ8Qmmmj9ca+U1NALNAH4d1dxGSK0RbmScb6fqtdDrRi3uNHG45jfVXP8ArXFFkaexspDzt17FNmE3TgEHSBGk139SdrH+euwsVd5ScYSwAJcMesplKfb155Kka5P4Eqaw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770204314; c=relaxed/simple; bh=oorZD94bqknHwCONFePbJPyMlJ3U8ZRa2AuBHrvz210=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PRcp2j4iJzN1TucyeCzB6L69058KMD8t8Dx8EjhupRafVkWnZUISV7GRqxNB32pVQQtgmv5uZqSkAc10P67GbCVFfV8EaFgOnLAf36UCvM26CI9X06jaH6tfgMaOyehqmfmOsrj3Qc0BGIQ9TxXMTg6RsviMC3NyMK7EU3ct0YE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HJHrS7GF; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HJHrS7GF" Received: by smtp.kernel.org (Postfix) with ESMTPS id E965EC2BCB8; Wed, 4 Feb 2026 11:25:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1770204314; bh=oorZD94bqknHwCONFePbJPyMlJ3U8ZRa2AuBHrvz210=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=HJHrS7GFphrgbe7wIzINX825oBnpX0VqRhWsapz+CMsp9lgO2hk/uRZt639N/CjqI TxOdU+v4C2OtkHw5+46DgbiNQo6eE+q7zv1hjbxAqj8gGE9Y8TFIVz7jfzuTHKYMgK t7eCBISk/om6flC5ZKwEMEdbmeC6o1CagV0FTv6/EW5Z9BThqOAbuf0d5FczgxSEDB saBQ/kEaI5JAzZGpS6Rkec/Sc4+5abHHec+uP4bjLJV2SGCfGmJe3exRDX8Eebufz9 LP0nmfJF4xOIwVtH4OobGsbxBqCTDSEW+jDJdz3s4Vf9WH+J+Mb6u77SB+elJsq3HH MT2PeJCpgxC0A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8D19E9538B; Wed, 4 Feb 2026 11:25:13 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 04 Feb 2026 15:25:10 +0400 Subject: [PATCH v20 4/6] arm64: dts: qcom: ipq5018: add pwm node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260204-ipq-pwm-v20-4-91733011a3d1@outlook.com> References: <20260204-ipq-pwm-v20-0-91733011a3d1@outlook.com> In-Reply-To: <20260204-ipq-pwm-v20-0-91733011a3d1@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770204310; l=1233; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=lAsFviMxwPOw696EFWy7F3ZKtG5pnaKrLmo7lHkVZgA=; b=bhNa651tRCUk5fRuzDprxxQdFYwAIis/vCq5w1NFwaFRTpUO9mduSRLmEBn3qEKjuKLGXz7/9 ZR4aLA0lRcFC53TUPCTq6R0aIXUn+aaqymDRb5lebSOYg1aNDJDODNo X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Describe the PWM block on IPQ5018. Although PWM is in the TCSR area, make pwm its own node as simple-mfd has been removed from the bindings and as such hardware components should have its own node. Reviewed-by: Dmitry Baryshkov Signed-off-by: George Moussalem Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qc= om/ipq5018.dtsi index 6f8004a22a1ffdb6da0be410b772be5fe0473eef..edff89257468cc5535a68321123= c8a6cd0fb5adb 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -453,6 +453,16 @@ tcsr: syscon@1937000 { reg =3D <0x01937000 0x21000>; }; =20 + pwm: pwm@1941010 { + compatible =3D "qcom,ipq5018-pwm", "qcom,ipq6018-pwm"; + reg =3D <0x01941010 0x20>; + clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates =3D <100000000>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + sdhc_1: mmc@7804000 { compatible =3D "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x7804000 0x1000>; --=20 2.52.0 From nobody Mon Feb 9 09:23:13 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 350853E9F98; Wed, 4 Feb 2026 11:25:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770204314; cv=none; b=CaUHUchHnh+ACDIEwhsBFrt5sM7oj8tN+lAcNgDV/2fZ6A5jsWNcro1c5IGkyN0z2330WaiZVQTeIYZhDpvTpIgwitAG1AtRidBCb/fm8T97I+zO93u9yLxy+VsQeFIHeztSKaijpuItYEkcIIUCoIOcBdvmcUThJbSBu38dJ4Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770204314; c=relaxed/simple; bh=XQ4+jrCNUegmedw+kAaz44GruUsx1JtVMFlXfj8TCGg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=R5w1EDMyT5x3Lv7haWWTGUBPcxyxsx6Y/3EJOxj+xqX+w8UB6Cy6dDx5hasosqoQkEOoNRuSI+TaX1txUDyCqKO7MtXgUDGCYuMUxcocFuxKH0OZv2PG5MsYjiUzIDLV80gBCKqn3/UMAR9L2fcIDzU7VIlrqCFFHFZvjYfkFy4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qngL5+eY; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qngL5+eY" Received: by smtp.kernel.org (Postfix) with ESMTPS id 0B912C2BCB4; Wed, 4 Feb 2026 11:25:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1770204314; bh=XQ4+jrCNUegmedw+kAaz44GruUsx1JtVMFlXfj8TCGg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=qngL5+eYZ7M5l1nlZupedgtUgVkwaUc8xeH0tGprnKqGh40J0c+BOwDbDWL10ptrI YtYIrsNq8u9kmRBaVwBk7R1s5xrl9ZqkJ7c7xP6nKh4DZ5MpKomGDUoH4BWxCtY+Pn FWTXfmfKLrFOrw4AufMXRS7Mhw/a6h7sD3CfeqzF/Y3EUEsbmKjHIXRWP49As0uQIq HnAvvvqu5ib0UhzXziw3iASx6rJ4KD9yazNcC0ScHU9mr2dX0xEbjFMV8XDTMuU0Ir 9EGyDUxn2mKF35FZF+WWQfA+993HnKuZ313WRPhIUNqLEGp1UjYGbPvEugZKoiJYG3 ReMGfO3h6pGNw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE479E9538A; Wed, 4 Feb 2026 11:25:13 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 04 Feb 2026 15:25:11 +0400 Subject: [PATCH v20 5/6] arm64: dts: qcom: ipq5332: add pwm node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260204-ipq-pwm-v20-5-91733011a3d1@outlook.com> References: <20260204-ipq-pwm-v20-0-91733011a3d1@outlook.com> In-Reply-To: <20260204-ipq-pwm-v20-0-91733011a3d1@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770204310; l=1253; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=ZzpZ9Oc2KX6I6uglSgS8/bCLV/sm5oDSygkEKKOZMT4=; b=NR2Y2+NbvmXYL0QqoQVsbYuvUzMABg5L0qfdFJZ50QT10QYg36lJJ1gRZZnmoRsbbG0PoeTI1 f7Qvb5Phy7HAOuZHF0NZdsYmhH41F28edGTJsa0Ye+K7a6SaHkcEFZC X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Describe the PWM block on IPQ5332. Although PWM is in the TCSR area, make pwm its own node as simple-mfd has been removed from the bindings and as such hardware components should have its own node. Reviewed-by: Dmitry Baryshkov Signed-off-by: George Moussalem Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qc= om/ipq5332.dtsi index 45fc512a3bab221c0d99f819294abf63369987da..e58051f6c1c4fd8ef85cbcc9b98= 433f599377c7a 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -334,6 +334,16 @@ tcsr: syscon@1937000 { reg =3D <0x01937000 0x21000>; }; =20 + pwm: pwm@1941010 { + compatible =3D "qcom,ipq5332-pwm", "qcom,ipq6018-pwm"; + reg =3D <0x01941010 0x20>; + clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates =3D <100000000>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + sdhc: mmc@7804000 { compatible =3D "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x07804000 0x1000>, <0x07805000 0x1000>; --=20 2.52.0 From nobody Mon Feb 9 09:23:13 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 488673ECBC5; Wed, 4 Feb 2026 11:25:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770204314; cv=none; b=uwndTXZwjatScjw/qfG0MiKqSIzmIqMgv7TVXWmxKetvRuaAg31sb9ZhW77UPjPX/lMOditmtVgqxnruPV2O6MZjPnZYpu9HApUfhtwTIOzw3WjizZC/AgH49PFHOWCDPWcP9WGPKoDjEz3vupzf1ki1h0rXV4pbjkJtO2Dgfg8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770204314; c=relaxed/simple; bh=vE8UXlKfInB73S8Crc3gaHWqLQg+oOyoCtzeWharQS0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nr0qlzwFsS+ce2fu7iqjeCzNSpG8h2LgSxcLUcVXPjNCM2Ync4ajZxf9s+2yE/jV1FuPogUTSu/Npx6P4esNTjiZnUNQQGO/vqBBzhAUOsRZh5kDpfIZD4XNW94nSCFEnymaMZDVMojvZSF25aKaWLbrWAehNVPyQMhyGyXG2kg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=eBdXYFei; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="eBdXYFei" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1FBA8C16AAE; Wed, 4 Feb 2026 11:25:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1770204314; bh=vE8UXlKfInB73S8Crc3gaHWqLQg+oOyoCtzeWharQS0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=eBdXYFeiLIl+QGeTfz6IIUeYBuEEDl+b419qodE2EVomGdqaNo6884pycBeWBvZMh haX7oelDQSKnWGiF9sQjVUxz4Bay2BEZVQ1GmcghWtGQg7w+d4/fdfvByLW08F//at iN1OoKPRpYgIVaVKk7kEOMlXr20t38YcZLXpVfFG+fIWwnxTLMzJ8Gau5rLyluyr8P eM9GvY4qwgMgvdyujRQepS7Oi+ovHftu/43TRRxbdoIE8N8kI7jYvsCdHJ61HDu2ls NNNef1ZfWkcdGaVDLNWZmQ6VTGMTNKrX1uWcdOfsGts6/lMd7pc+dMVMn4md9rJWnb Ul0Go0aD9V1TQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DE25E95389; Wed, 4 Feb 2026 11:25:14 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 04 Feb 2026 15:25:12 +0400 Subject: [PATCH v20 6/6] arm64: dts: qcom: ipq9574: add pwm node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260204-ipq-pwm-v20-6-91733011a3d1@outlook.com> References: <20260204-ipq-pwm-v20-0-91733011a3d1@outlook.com> In-Reply-To: <20260204-ipq-pwm-v20-0-91733011a3d1@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770204310; l=1234; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=1ixhFwq2rEjXYJIhs5+j+ngAUcQh5KQa6+Qdzh8kp4o=; b=ky+nnCBbPuFce/HNZnz6s4ubdKccwoR4mGT7VVjp1Q+YR30lXS7xluR+rnmLy73TfU2J3/6kO 144Si65ChORDD0KZk1dvy+masC3Igfhy8O3qYSqMdoqSlttNJsS5eZR X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Describe the PWM block on IPQ9574. Although PWM is in the TCSR area, make pwm its own node as simple-mfd has been removed from the bindings and as such hardware components should have its own node. Reviewed-by: Dmitry Baryshkov Signed-off-by: George Moussalem Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qc= om/ipq9574.dtsi index d7278f2137ac58305cc4e82c1d6c26c08bc7a405..31f4bcc92c986e1c0b02ea56acd= f707af92b7f84 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -449,6 +449,16 @@ tcsr: syscon@1937000 { reg =3D <0x01937000 0x21000>; }; =20 + pwm: pwm@1941010 { + compatible =3D "qcom,ipq9574-pwm", "qcom,ipq6018-pwm"; + reg =3D <0x01941010 0x20>; + clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates =3D <100000000>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + sdhc_1: mmc@7804000 { compatible =3D "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x07804000 0x1000>, --=20 2.52.0