From nobody Tue Feb 10 01:31:00 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D970D3A1D13; Wed, 4 Feb 2026 11:30:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770204642; cv=none; b=I7GF53T6A55D7AWCwGYQNHHDOAvlpsScDczaGFjmhBdXeAE1dyeXQI8qaibw7gbE6uO7MyMiNjYE9c4PDGTLLPp8BenxNFlvte005HIqxIMlPqnEvWyGqYX/409/CizuGrrhVgOOqBqGzmqcrHgieTO4Nua1ZazgjqaasvyOarc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770204642; c=relaxed/simple; bh=EnIqsxpSsoYg3Tlb1q6O0ZisfQ1xrmLSOz0z0LZ3vlY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=S4FBV+MyeJczLOCn+STATdFWIyqw4XKNFpRGSqWDsFfKEu5BPVFuCsPyxfZsLUu1BdGMCf3hjsaWhsMk2juNd0787z0fnYJNVkCtbGF7hJHzHFmupluD/nPAZVgkWzFJ56b0x3Yd9lVOKUJ1Epygx4NZB+gMn+kkarhZjWW3GjY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CS5pkbRz; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CS5pkbRz" Received: by smtp.kernel.org (Postfix) with ESMTPS id 83827C19422; Wed, 4 Feb 2026 11:30:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1770204642; bh=EnIqsxpSsoYg3Tlb1q6O0ZisfQ1xrmLSOz0z0LZ3vlY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=CS5pkbRzbO3cxQa1gIC3rd3buZd2TCiDsshc+LdZjfZLnlXveu9IvGU1rQS7+pRZh NCpTgX3JMdEMEIV8re5+52mF1EYECnk/yd9R+m5z5XiqDJwVEVeg/HxXDZU8hWD9xL cQuhv5HR8w5yCvotCvDJsrXvNW4tkp1o0+7/hWFm0YgwFUikcQ6ZBU80s7Tux/GOmI 0d1aiV+m0Ij13HuHK40dUQDYfWG/DKeHHEm4ycXqA+QxoaSoI+IiVVVkddBcAgwH3T I0djFU+2HFIh8HFNqafb5YrtcrzuCtQkIZuh3nTG8/9eN1I2rFl0zQdHgnIbpF7rDh JwBEgnJidb+vA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 709F1E95389; Wed, 4 Feb 2026 11:30:42 +0000 (UTC) From: Ben Zong-You Xie via B4 Relay Date: Wed, 04 Feb 2026 19:30:41 +0800 Subject: [PATCH v4 1/3] dt-bindings: pwm: add support for AE350 PWM controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260204-andes-pwm-v4-1-67016bb13555@andestech.com> References: <20260204-andes-pwm-v4-0-67016bb13555@andestech.com> In-Reply-To: <20260204-andes-pwm-v4-0-67016bb13555@andestech.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ben Zong-You Xie X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770204641; l=2571; i=ben717@andestech.com; s=20260120; h=from:subject:message-id; bh=0bXlagODlL9Rn/hEL7/r3/Td8Wjq5W+Ods2FEtVZSXo=; b=ihvP0/54bNkepk8SWKpujW3hSXcb7C9ZTAkQFRKr54SXr1qrfkrJVAOG+KvNCh5PkmvUhckig h2pi6jRcFsdCsrZDfcs4m0ccoOQuVEuAGoAJvv7OknVw+Hrr9weDR5V X-Developer-Key: i=ben717@andestech.com; a=ed25519; pk=nb8L7zQKGJpYk0yvrYKjViOZ34A36g1ZIsCmCsP518s= X-Endpoint-Received: by B4 Relay for ben717@andestech.com/20260120 with auth_id=610 X-Original-From: Ben Zong-You Xie Reply-To: ben717@andestech.com From: Ben Zong-You Xie The ATCPIT100 is a set of compact multi-function timers, which can be used as pulse width modulators (PWM) as well as simple timers. ATCPIT100 supports up to 4 PIT channels, and each PIT channel may be configured as a simple timer or PWM, or a combination of the timer and the PWM. This IP block is a core component of the Andes AE350 platform, which serves as a reference architecture for SoC designs. The QiLai SoC also integrates this controller. The binding introduces the following compatible strings: - "andestech,qilai-pwm": For the implementation integrated into the Andes QiLai SoC. - "andestech,ae350-pwm": As a fallback compatible string representing the base IP design used across the AE350 platform architecture. Signed-off-by: Ben Zong-You Xie Reviewed-by: Rob Herring (Arm) --- .../bindings/pwm/andestech,ae350-pwm.yaml | 61 ++++++++++++++++++= ++++ 1 file changed, 61 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/andestech,ae350-pwm.yaml= b/Documentation/devicetree/bindings/pwm/andestech,ae350-pwm.yaml new file mode 100644 index 000000000000..287f3c62965f --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/andestech,ae350-pwm.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/andestech,ae350-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andes PWM controller on AE350 platform + +description: + This controller has 4 channels and two clock sources. Each channel can + switch the clock source by programming the corresponding register. + +maintainers: + - Ben Zong-You Xie + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - andestech,qilai-pwm + - const: andestech,ae350-pwm + - const: andestech,ae350-pwm + + reg: + maxItems: 1 + + "#pwm-cells": + const: 3 + + clocks: + items: + - description: APB bus clock + - description: External clock + + clock-names: + items: + - const: pclk + - const: extclk + +required: + - compatible + - reg + - "#pwm-cells" + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + pwm@f0400000 { + compatible =3D "andestech,ae350-pwm"; + reg =3D <0xf0400000 0x100000>; + #pwm-cells =3D <3>; + clocks =3D <&pclk>, <&extclk>; + clock-names =3D "pclk", "extclk"; + }; --=20 2.34.1