From nobody Mon Feb 9 01:01:25 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D970D3A1D13; Wed, 4 Feb 2026 11:30:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770204642; cv=none; b=I7GF53T6A55D7AWCwGYQNHHDOAvlpsScDczaGFjmhBdXeAE1dyeXQI8qaibw7gbE6uO7MyMiNjYE9c4PDGTLLPp8BenxNFlvte005HIqxIMlPqnEvWyGqYX/409/CizuGrrhVgOOqBqGzmqcrHgieTO4Nua1ZazgjqaasvyOarc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770204642; c=relaxed/simple; bh=EnIqsxpSsoYg3Tlb1q6O0ZisfQ1xrmLSOz0z0LZ3vlY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=S4FBV+MyeJczLOCn+STATdFWIyqw4XKNFpRGSqWDsFfKEu5BPVFuCsPyxfZsLUu1BdGMCf3hjsaWhsMk2juNd0787z0fnYJNVkCtbGF7hJHzHFmupluD/nPAZVgkWzFJ56b0x3Yd9lVOKUJ1Epygx4NZB+gMn+kkarhZjWW3GjY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CS5pkbRz; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CS5pkbRz" Received: by smtp.kernel.org (Postfix) with ESMTPS id 83827C19422; Wed, 4 Feb 2026 11:30:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1770204642; bh=EnIqsxpSsoYg3Tlb1q6O0ZisfQ1xrmLSOz0z0LZ3vlY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=CS5pkbRzbO3cxQa1gIC3rd3buZd2TCiDsshc+LdZjfZLnlXveu9IvGU1rQS7+pRZh NCpTgX3JMdEMEIV8re5+52mF1EYECnk/yd9R+m5z5XiqDJwVEVeg/HxXDZU8hWD9xL cQuhv5HR8w5yCvotCvDJsrXvNW4tkp1o0+7/hWFm0YgwFUikcQ6ZBU80s7Tux/GOmI 0d1aiV+m0Ij13HuHK40dUQDYfWG/DKeHHEm4ycXqA+QxoaSoI+IiVVVkddBcAgwH3T I0djFU+2HFIh8HFNqafb5YrtcrzuCtQkIZuh3nTG8/9eN1I2rFl0zQdHgnIbpF7rDh JwBEgnJidb+vA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 709F1E95389; Wed, 4 Feb 2026 11:30:42 +0000 (UTC) From: Ben Zong-You Xie via B4 Relay Date: Wed, 04 Feb 2026 19:30:41 +0800 Subject: [PATCH v4 1/3] dt-bindings: pwm: add support for AE350 PWM controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260204-andes-pwm-v4-1-67016bb13555@andestech.com> References: <20260204-andes-pwm-v4-0-67016bb13555@andestech.com> In-Reply-To: <20260204-andes-pwm-v4-0-67016bb13555@andestech.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ben Zong-You Xie X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770204641; l=2571; i=ben717@andestech.com; s=20260120; h=from:subject:message-id; bh=0bXlagODlL9Rn/hEL7/r3/Td8Wjq5W+Ods2FEtVZSXo=; b=ihvP0/54bNkepk8SWKpujW3hSXcb7C9ZTAkQFRKr54SXr1qrfkrJVAOG+KvNCh5PkmvUhckig h2pi6jRcFsdCsrZDfcs4m0ccoOQuVEuAGoAJvv7OknVw+Hrr9weDR5V X-Developer-Key: i=ben717@andestech.com; a=ed25519; pk=nb8L7zQKGJpYk0yvrYKjViOZ34A36g1ZIsCmCsP518s= X-Endpoint-Received: by B4 Relay for ben717@andestech.com/20260120 with auth_id=610 X-Original-From: Ben Zong-You Xie Reply-To: ben717@andestech.com From: Ben Zong-You Xie The ATCPIT100 is a set of compact multi-function timers, which can be used as pulse width modulators (PWM) as well as simple timers. ATCPIT100 supports up to 4 PIT channels, and each PIT channel may be configured as a simple timer or PWM, or a combination of the timer and the PWM. This IP block is a core component of the Andes AE350 platform, which serves as a reference architecture for SoC designs. The QiLai SoC also integrates this controller. The binding introduces the following compatible strings: - "andestech,qilai-pwm": For the implementation integrated into the Andes QiLai SoC. - "andestech,ae350-pwm": As a fallback compatible string representing the base IP design used across the AE350 platform architecture. Signed-off-by: Ben Zong-You Xie --- .../bindings/pwm/andestech,ae350-pwm.yaml | 61 ++++++++++++++++++= ++++ 1 file changed, 61 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/andestech,ae350-pwm.yaml= b/Documentation/devicetree/bindings/pwm/andestech,ae350-pwm.yaml new file mode 100644 index 000000000000..287f3c62965f --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/andestech,ae350-pwm.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/andestech,ae350-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andes PWM controller on AE350 platform + +description: + This controller has 4 channels and two clock sources. Each channel can + switch the clock source by programming the corresponding register. + +maintainers: + - Ben Zong-You Xie + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - andestech,qilai-pwm + - const: andestech,ae350-pwm + - const: andestech,ae350-pwm + + reg: + maxItems: 1 + + "#pwm-cells": + const: 3 + + clocks: + items: + - description: APB bus clock + - description: External clock + + clock-names: + items: + - const: pclk + - const: extclk + +required: + - compatible + - reg + - "#pwm-cells" + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + pwm@f0400000 { + compatible =3D "andestech,ae350-pwm"; + reg =3D <0xf0400000 0x100000>; + #pwm-cells =3D <3>; + clocks =3D <&pclk>, <&extclk>; + clock-names =3D "pclk", "extclk"; + }; --=20 2.34.1 From nobody Mon Feb 9 01:01:25 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D968336C0DF; Wed, 4 Feb 2026 11:30:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770204642; cv=none; b=Wjyn2KG4Syj51HBqaGL7x4xfxfdkNp5pN3nKBXbeglhGSvS7wmJfrPUpPwcG1Ap1ZxT0+Yy8dxeTvp4TLGdEKBgO1ivFbqmCLGQjRCH2i4oDgprf5ZRbTNnbR92alp71Q+j1wmNOE2sMgYmPXsJy2ni+smS53IFTlRUbISd8atU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770204642; c=relaxed/simple; bh=zkNZgqriee8oDE85/0hw9dbAFsHYZugU0z6sxnVbyhQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OAXXvZhqvhPH5iWCiaD/7p3QN+u4D7DCmQ/wW9CKszBbPhnDjU8l+WvtF8Lp36vrG2xFhSh8H0f5cF18oU1BZhay7J3IxHEDVa+kJ2b/roBY8v5Tc/ASxm4Mjiu0/710s92vFKsdLMhSO0+ihJUAs/PQ++sFxY8toP5pDdN/1gE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=oSC3beWJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="oSC3beWJ" Received: by smtp.kernel.org (Postfix) with ESMTPS id 91FFBC2BC9E; Wed, 4 Feb 2026 11:30:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1770204642; bh=zkNZgqriee8oDE85/0hw9dbAFsHYZugU0z6sxnVbyhQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=oSC3beWJhVmjH6YN8s2XCLrYjYW+lkl3y/DQPZwCskUi+By6cQkzgmqy5YFKDuIuf XIE6g8Yy2vSF/auvmffAlKDRB/ik3ZKhf8ra5HXGl+Z0pBgUlR0EyzH8jjKNK0uryY t98k0mq4f/YJc5Jm542X1kMiEZWUGrbuNrzktd5FyHUYIER5YkPog1GzX1lcboOkyH Iwmr4Waz7RgDc0X76WJ+zL919+ReDSglCI55GZfg1AryL5RcMjkZHE5MCtVOZHdBW3 n4x2/t/6aB2X1mxD+fb2fVwOUJ1jKorSk+8Zpflb0rgq8qABkjZvKms8pEqYzspNM5 0fYt7mQKuG0Gg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8418CE9538C; Wed, 4 Feb 2026 11:30:42 +0000 (UTC) From: Ben Zong-You Xie via B4 Relay Date: Wed, 04 Feb 2026 19:30:42 +0800 Subject: [PATCH v4 2/3] pwm: add Andes PWM driver support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260204-andes-pwm-v4-2-67016bb13555@andestech.com> References: <20260204-andes-pwm-v4-0-67016bb13555@andestech.com> In-Reply-To: <20260204-andes-pwm-v4-0-67016bb13555@andestech.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ben Zong-You Xie X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770204641; l=11929; i=ben717@andestech.com; s=20260120; h=from:subject:message-id; bh=GtWrGCOpQ0ivIMuJElmmZKWT7fHnuOYXiBw7/f54Xuo=; b=y42ZT1axy8q0U1GQXBPehnnEFbJleCnH5W3OZxuJtZq+mBvCPkEaASxJV97yqGmTnRDBjwRMf JcOSvhKu9u4AITfkk8sAEXxJzKyiA+hp/ScCWfy6Jta429O6NczRRiX X-Developer-Key: i=ben717@andestech.com; a=ed25519; pk=nb8L7zQKGJpYk0yvrYKjViOZ34A36g1ZIsCmCsP518s= X-Endpoint-Received: by B4 Relay for ben717@andestech.com/20260120 with auth_id=610 X-Original-From: Ben Zong-You Xie Reply-To: ben717@andestech.com From: Ben Zong-You Xie Add a driver for the PWM controller found in Andes AE350 platforms and QiLai SoCs. The Andes PWM controller features: - 4 independent channels. - Dual clock source support (APB clock and external clock) to provide a flexible range of frequencies. - Support for normal and inversed polarity. The driver implements the .apply() and .get_state() callbacks. Since the clock source of each channel can be selected by programming the register, clock selection logic is implemented to prioritize the external clock to maximize the supported period range, falling back to the APB clock for higher frequency requirements. Signed-off-by: Ben Zong-You Xie --- drivers/pwm/Kconfig | 10 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-andes.c | 306 ++++++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 317 insertions(+) diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 6f3147518376..b82f2c857ada 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -73,6 +73,16 @@ config PWM_AIROHA To compile this driver as a module, choose M here: the module will be called pwm-airoha. =20 +config PWM_ANDES + tristate "Andes PWM support" + depends on ARCH_ANDES || COMPILE_TEST + help + Generic PWM framework driver for Andes platform, such as QiLai SoC + and AE350 platform. + + To compile this driver as a module, choose M here: the module + will be called pwm-andes. + config PWM_APPLE tristate "Apple SoC PWM support" depends on ARCH_APPLE || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 0dc0d2b69025..858f225289cc 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_PWM) +=3D core.o obj-$(CONFIG_PWM_AB8500) +=3D pwm-ab8500.o obj-$(CONFIG_PWM_ADP5585) +=3D pwm-adp5585.o obj-$(CONFIG_PWM_AIROHA) +=3D pwm-airoha.o +obj-$(CONFIG_PWM_ANDES) +=3D pwm-andes.o obj-$(CONFIG_PWM_APPLE) +=3D pwm-apple.o obj-$(CONFIG_PWM_ARGON_FAN_HAT) +=3D pwm-argon-fan-hat.o obj-$(CONFIG_PWM_ATMEL) +=3D pwm-atmel.o diff --git a/drivers/pwm/pwm-andes.c b/drivers/pwm/pwm-andes.c new file mode 100644 index 000000000000..835c8db55987 --- /dev/null +++ b/drivers/pwm/pwm-andes.c @@ -0,0 +1,306 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for Andes PWM, used in Andes AE350 platform and QiLai SoC + * + * Copyright (C) 2026 Andes Technology Corporation. + * + * Limitations: + * - When disabling a channel, the current period will not be completed, a= nd the + * output will be constant zero. + * - The current period will be completed first if reconfiguring. + * - Further, if the reconfiguration changes the clock source, the output = will + * not be the old one nor the new one. And the output will be the new one + * until writing to the reload register. + * - The hardware can neither do a 0% nor a 100% relative duty cycle. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ANDES_PWM_CH_ENABLE 0x1C +#define ANDES_PWM_CH_ENABLE_PWM(ch) BIT(3 + (4 * (ch))) + +#define ANDES_PWM_CH_CTRL(ch) (0x20 + (0x10 * (ch))) +#define ANDES_PWM_CH_CTRL_MODE_PWM BIT(2) +#define ANDES_PWM_CH_CTRL_CLK BIT(3) +#define ANDES_PWM_CH_CTRL_PARK BIT(4) +#define ANDES_PWM_CH_CTRL_MASK GENMASK(4, 0) + +#define ANDES_PWM_CH_RELOAD(ch) (0x24 + (0x10 * (ch))) +#define ANDES_PWM_CH_RELOAD_HIGH GENMASK(31, 16) +#define ANDES_PWM_CH_RELOAD_LOW GENMASK(15, 0) + +#define ANDES_PWM_CH_COUNTER(ch) (0x28 + (0x10 * (ch))) + +#define ANDES_PWM_CH_MAX 4 +#define ANDES_PWM_CYCLE_MIN 1 +#define ANDES_PWM_CYCLE_MAX 0x10000 + +struct andes_pwm { + struct regmap *regmap; + struct clk *pclk; + struct clk *extclk; + unsigned int pclk_rate; + unsigned int extclk_rate; +}; + +static const struct regmap_config andes_pwm_regmap_config =3D { + .name =3D "andes_pwm", + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .pad_bits =3D 0, + .max_register =3D ANDES_PWM_CH_COUNTER(ANDES_PWM_CH_MAX - 1), + .cache_type =3D REGCACHE_NONE, +}; + +static inline struct andes_pwm *to_andes_pwm(struct pwm_chip *chip) +{ + return pwmchip_get_drvdata(chip); +} + +static int andes_pwm_enable(struct pwm_chip *chip, unsigned int channel, + bool enable) +{ + struct andes_pwm *ap =3D to_andes_pwm(chip); + + return regmap_assign_bits(ap->regmap, ANDES_PWM_CH_ENABLE, + ANDES_PWM_CH_ENABLE_PWM(channel), enable); +} + +static int andes_pwm_config(struct pwm_chip *chip, unsigned int channel, + const struct pwm_state *state) +{ + struct andes_pwm *ap =3D to_andes_pwm(chip); + unsigned int clk_rate =3D ap->extclk_rate; + unsigned int try =3D 2; + u64 high_ns =3D state->duty_cycle; + u64 low_ns =3D state->period - high_ns; + unsigned int ctrl =3D ANDES_PWM_CH_CTRL_MODE_PWM; + u64 high_cycles; + u64 low_cycles; + u32 reload; + + /* + * Reload register for PWM mode: + * + * 31 : 16 15 : 0 + * PWM16_Hi | PWM16_Lo + * + * The high duration is (PWM16_Hi + 1) cycles and the low duration is + * (PWM16_Lo + 1) cycles. For a duty cycle of 10 cycles and a total + * period of 30 cycles in normal polarity, PWM16_Hi is set to + * 9 (10 - 1) and PWM16_Lo to 19 (30 - 10 - 1). Also, PWM16_Hi is set to + * 19 and PWM16_Lo is set to 9 in inversed polarity. + * + * Because the register stores "cycles - 1", the valid range for + * each phase is 1 to 65536 (0x10000) cycles. This implies the hardware + * cannot achieve a true 0% or 100% duty cycle. + * + * The controller supports two clock sources: the APB clock and an + * external clock. The driver first attempts to use the external clock + * to widest possible range of supported periods. If the requests + * exceeds the valid range of the register, it falls back to the APB + * clock. The request is rejected if the timing cannot be met by either + * source. + */ + if (state->polarity =3D=3D PWM_POLARITY_INVERSED) + swap(high_ns, low_ns); + + while (try) { + high_cycles =3D mul_u64_u64_div_u64(clk_rate, high_ns, + NSEC_PER_SEC); + low_cycles =3D mul_u64_u64_div_u64(clk_rate, low_ns, + NSEC_PER_SEC); + if (high_cycles > ANDES_PWM_CYCLE_MAX) + high_cycles =3D ANDES_PWM_CYCLE_MAX; + + if (low_cycles > ANDES_PWM_CYCLE_MAX) + low_cycles =3D ANDES_PWM_CYCLE_MAX; + + if (high_cycles >=3D ANDES_PWM_CYCLE_MIN && + low_cycles >=3D ANDES_PWM_CYCLE_MIN) + break; + + try--; + clk_rate =3D ap->pclk_rate; + } + + /* + * try =3D=3D 0 : no clock is valid + * try =3D=3D 1 : use APB clock + * try =3D=3D 2 : use external clock + */ + if (!try) + return -EINVAL; + + /* + * If changing the clock source here, the output will not be the old one + * nor the new one. And the output will be the new one until writing to + * the reload register. + */ + ctrl |=3D (try =3D=3D 1) ? ANDES_PWM_CH_CTRL_CLK : 0; + ctrl |=3D (state->polarity =3D=3D PWM_POLARITY_INVERSED) ? + ANDES_PWM_CH_CTRL_PARK : 0; + regmap_update_bits(ap->regmap, ANDES_PWM_CH_CTRL(channel), + ANDES_PWM_CH_CTRL_MASK, ctrl); + reload =3D FIELD_PREP(ANDES_PWM_CH_RELOAD_HIGH, high_cycles - 1) | + FIELD_PREP(ANDES_PWM_CH_RELOAD_LOW, low_cycles - 1); + + return regmap_write(ap->regmap, ANDES_PWM_CH_RELOAD(channel), reload); +} + +static int andes_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + unsigned int channel =3D pwm->hwpwm; + int ret; + + if (!state->enabled) { + if (pwm->state.enabled) + andes_pwm_enable(chip, channel, false); + + return 0; + } + + ret =3D andes_pwm_config(chip, channel, state); + if (ret) + return ret; + + return andes_pwm_enable(chip, channel, true); +} + +static int andes_pwm_get_state(struct pwm_chip *chip, struct pwm_device *p= wm, + struct pwm_state *state) +{ + struct andes_pwm *ap =3D to_andes_pwm(chip); + unsigned int channel =3D pwm->hwpwm; + unsigned int ctrl; + unsigned int clk_rate; + unsigned int reload; + u64 high_cycles; + u64 low_cycles; + + regmap_read(ap->regmap, ANDES_PWM_CH_CTRL(channel), &ctrl); + clk_rate =3D FIELD_GET(ANDES_PWM_CH_CTRL_CLK, ctrl) ? ap->pclk_rate + : ap->extclk_rate; + state->enabled =3D regmap_test_bits(ap->regmap, ANDES_PWM_CH_ENABLE, + ANDES_PWM_CH_ENABLE_PWM(channel)); + state->polarity =3D regmap_test_bits(ap->regmap, + ANDES_PWM_CH_CTRL(channel), + ANDES_PWM_CH_CTRL_PARK); + regmap_read(ap->regmap, ANDES_PWM_CH_RELOAD(channel), &reload); + high_cycles =3D FIELD_GET(ANDES_PWM_CH_RELOAD_HIGH, reload) + 1; + low_cycles =3D FIELD_GET(ANDES_PWM_CH_RELOAD_LOW, reload) + 1; + + /* + * high_cycles and low_cycles are both 16 bits, and NSEC_PER_SEC is 30 + * bits. Thus, the multiplication is safe from overflow + */ + if (state->polarity =3D=3D PWM_POLARITY_NORMAL) { + state->duty_cycle =3D DIV_ROUND_UP_ULL(high_cycles * NSEC_PER_SEC, + clk_rate); + state->period =3D state->duty_cycle + + DIV_ROUND_UP_ULL(low_cycles * NSEC_PER_SEC, + clk_rate); + } else { + state->duty_cycle =3D DIV_ROUND_UP_ULL(low_cycles * NSEC_PER_SEC, + clk_rate); + state->period =3D state->duty_cycle + + DIV_ROUND_UP_ULL(high_cycles * NSEC_PER_SEC, + clk_rate); + } + + return 0; +} + +static const struct pwm_ops andes_pwm_ops =3D { + .apply =3D andes_pwm_apply, + .get_state =3D andes_pwm_get_state, +}; + +static int andes_pwm_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct pwm_chip *chip; + struct andes_pwm *ap; + void __iomem *reg_base; + int ret; + + chip =3D devm_pwmchip_alloc(dev, ANDES_PWM_CH_MAX, sizeof(*ap)); + if (IS_ERR(chip)) + return PTR_ERR(chip); + + ap =3D to_andes_pwm(chip); + reg_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(reg_base)) + return dev_err_probe(dev, PTR_ERR(reg_base), + "failed to map I/O space\n"); + + ap->pclk =3D devm_clk_get_enabled(dev, "pclk"); + if (IS_ERR(ap->pclk)) + return dev_err_probe(dev, PTR_ERR(ap->pclk), + "failed to get APB clock\n"); + + ap->extclk =3D devm_clk_get_optional_enabled(dev, "extclk"); + if (IS_ERR(ap->extclk)) + return dev_err_probe(dev, PTR_ERR(ap->extclk), + "failed to get external clock\n"); + + /* + * If the clock rate is greater than 10^9, there may be an overflow when + * calculating the cycles in andes_pwm_config() + */ + ap->pclk_rate =3D clk_get_rate(ap->pclk); + if (ap->pclk_rate > NSEC_PER_SEC) + ap->pclk =3D NULL; + + ap->extclk_rate =3D ap->extclk ? clk_get_rate(ap->extclk) : 0; + if (ap->extclk_rate > NSEC_PER_SEC) + ap->extclk =3D NULL; + + if (!ap->pclk && !ap->extclk) + return dev_err_probe(dev, -EINVAL, "clocks are out of range\n"); + + ap->regmap =3D devm_regmap_init_mmio(dev, reg_base, + &andes_pwm_regmap_config); + if (IS_ERR(ap->regmap)) { + return dev_err_probe(dev, PTR_ERR(ap->regmap), + "failed to initialize regmap\n"); + } + + chip->ops =3D &andes_pwm_ops; + ret =3D devm_pwmchip_add(dev, chip); + if (ret) + return dev_err_probe(dev, ret, "failed to add pwm chip\n"); + + return 0; +} + +static const struct of_device_id andes_pwm_of_match[] =3D { + { .compatible =3D "andestech,ae350-pwm" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, andes_pwm_of_match); + +static struct platform_driver andes_pwm_driver =3D { + .driver =3D { + .name =3D "andes_pwm", + .of_match_table =3D andes_pwm_of_match, + }, + .probe =3D andes_pwm_probe, +}; +module_platform_driver(andes_pwm_driver); + +MODULE_AUTHOR("Ben Zong-You Xie "); +MODULE_DESCRIPTION("Andes PWM driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Mon Feb 9 01:01:25 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCD013A1D19; Wed, 4 Feb 2026 11:30:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770204642; cv=none; b=dVpFGwZUJPhQO0QpgD2ITpCiqHljuH8gDcb4vG53DZkuxygLx0Ujfiu+zgKNmxOabmb+ntyvLCUN5tzG8tnEU4ZAS4+a3lj3o2UhgVtMP0IFZxO5gioo1Dijse7+CgctOtarGaBc6WIPf0Hoa+noK+jiWzbKxogrwT4PVPb3Uow= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770204642; c=relaxed/simple; bh=KOVm3C+Lsqdu0105X0Xiq4lwszVKTM1v3AwHILpokuw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=u+DBDz4CXuAmD66JAE4tF5mrNFM+6eSp5xA8nRYStjEZUB2dZ2ajLvBhWy1Nr6GxoQ3wEVw9Xq32UwjSqP+/HxYRm8DrIX23Rwomw0MDQG8oxvhCENQUDkP7BhRmJOklKJPwvaNahsOmfDVATnr5PnQUXiGtjUrFnbwPYEaBVok= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Au9+sHeA; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Au9+sHeA" Received: by smtp.kernel.org (Postfix) with ESMTPS id ABCFDC2BC86; Wed, 4 Feb 2026 11:30:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1770204642; bh=KOVm3C+Lsqdu0105X0Xiq4lwszVKTM1v3AwHILpokuw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Au9+sHeAGjBhm33g5kDKqgW4r9VzgR3x6zJJVOhbMXbJFrUjaNRbvKmG62JXzK0ga NSMut2Kgn98NPVpbKsad5IbLQFq8qZzJ9aANR5Wc8g8paJPZE9HjfWwrshAyCtquKx AA3lf2VK3g7+HzeCc3HYlD9wVKWojyqjV0Bkc8AwDNRtBk/v4eaQ87GA+JXqn6clAb hcbCcad6AjBkRRpnhBJMArhX1/NnVNxb9H/DDIJRVhwsnxvs32zoHG1NvjWDxmQHYN G6d3vT6WW4xRToZnB4lnaCZ3TSX5GpSc7EacmHyMTBE4QLK7x7z0xunYUroFuNHux+ nkVXkIvUjCyfA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F90AE9538A; Wed, 4 Feb 2026 11:30:42 +0000 (UTC) From: Ben Zong-You Xie via B4 Relay Date: Wed, 04 Feb 2026 19:30:43 +0800 Subject: [PATCH v4 3/3] MAINTAINERS: add an entry for Andes PWM driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260204-andes-pwm-v4-3-67016bb13555@andestech.com> References: <20260204-andes-pwm-v4-0-67016bb13555@andestech.com> In-Reply-To: <20260204-andes-pwm-v4-0-67016bb13555@andestech.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ben Zong-You Xie X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770204641; l=718; i=ben717@andestech.com; s=20260120; h=from:subject:message-id; bh=L+fNVfc7JYf3+aGNasKyAhP0+tchIMKM44EzBGRUsVE=; b=dMDOp2I9fAG+kHI2pDIJDcSRPnnewYchBKmOPeVja702WL++cO63RH3O+uQ63cWrKSthH/Za+ 10Jr2KmL5TqCu/gY8CQDrRGwEpSsON5ZGJOhHwI64d8NGvdUhhihXBc X-Developer-Key: i=ben717@andestech.com; a=ed25519; pk=nb8L7zQKGJpYk0yvrYKjViOZ34A36g1ZIsCmCsP518s= X-Endpoint-Received: by B4 Relay for ben717@andestech.com/20260120 with auth_id=610 X-Original-From: Ben Zong-You Xie Reply-To: ben717@andestech.com From: Ben Zong-You Xie Add an entry for the Andes PWM driver to the MAINTAINERS file. Signed-off-by: Ben Zong-You Xie --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 75ebe5750242..536d692c0fb8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1817,6 +1817,12 @@ S: Supported F: drivers/clk/analogbits/* F: include/linux/clk/analogbits* =20 +ANDES PWM DRIVER +M: Ben Zong-You Xie +S: Supported +F: Documentation/devicetree/bindings/pwm/andestech,ae350-pwm.yaml +F: drivers/pwm/pwm-andes.c + ANDROID DRIVERS M: Greg Kroah-Hartman M: Arve Hj=C3=B8nnev=C3=A5g --=20 2.34.1