From nobody Sat Feb 7 19:45:25 2026 Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.166.228]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 585EB31ED8A; Tue, 3 Feb 2026 23:45:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.19.166.228 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770162340; cv=none; b=Mm02T5QBi/W+Q263x4gjqZifMVZP12bT0ii9TcylNzGGJqY7FHm/qKPf37yXLSQZObz5Yx2Cq52FFu8DdL/Oh91TGZLQ64YaC9InyTgMImFjf/NrgEqxM85tMMNhrFJ0u8XxZtz4tkjIi2Qij/SCPJTm4HjijqzpAWQjwuA4Zq4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770162340; c=relaxed/simple; bh=ml9v1vB2/T5uCoE4/zhdD80uAV/ygIDmxoi79Luua2U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NcEHVkdQ81witQRqG5b7TV7nkeeiGaTnFFTODkXWZzrr8odGWW4lA+Wxsa2NXRM/ZzPE1x/EhBOzaVnKX+jakkcMd0CB2rj9ZUnI5LLciXkwKcrY696VVXyzuHGU/v2JcihpEMh0y+xCETF94rSdlx9Xeb3vdS38n4X/NnElr1s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=OQouYBO2; arc=none smtp.client-ip=192.19.166.228 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="OQouYBO2" Received: from mail-lvn-it-01.broadcom.com (mail-lvn-it-01.lvn.broadcom.net [10.36.132.253]) by relay.smtp-ext.broadcom.com (Postfix) with ESMTP id EB7ADC08E92E; Tue, 3 Feb 2026 15:45:30 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com EB7ADC08E92E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1770162331; bh=ml9v1vB2/T5uCoE4/zhdD80uAV/ygIDmxoi79Luua2U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OQouYBO2njo6WhRO2sa8ITNwvSTFa6bI79uHVRUNpLVkgYNbrVwB6UHLBnKjOXFFW sAxrUCDykPyEWegyLiuS81IE8u4LdbrfNwPSE96ybJ81XJvtEQAKLE27RZD2GVFdYt Nt6L/W421Juhs+Hp2BZczOcbL+wJNOq12fiarQX8= Received: from fainelli-desktop.igp.broadcom.net (fainelli-desktop.dhcp.broadcom.net [10.67.48.245]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail-lvn-it-01.broadcom.com (Postfix) with ESMTPSA id CE1E417DFF; Tue, 3 Feb 2026 15:45:30 -0800 (PST) From: Florian Fainelli To: linux-kernel@vger.kernel.org Cc: Florian Fainelli , Doug Berger , Broadcom internal kernel review list , Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , Christophe Leroy , linux-gpio@vger.kernel.org (open list:GPIO SUBSYSTEM), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE) Subject: [PATCH v4 1/3] gpio: brcmstb: Utilize irqd_to_hwirq(d) instead of d->hwirq Date: Tue, 3 Feb 2026 15:45:27 -0800 Message-ID: <20260203234529.1081148-2-florian.fainelli@broadcom.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260203234529.1081148-1-florian.fainelli@broadcom.com> References: <20260203234529.1081148-1-florian.fainelli@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Consistently use irqd_to_hwirq(d) which is the recommended helper to fetch the hardware IRQ number from an irq_data structure. While at it, update the brcmstb_gpio_set_imask() function signature to use the proper type for the "hwirq" argument rather than "unsigned int". Signed-off-by: Florian Fainelli Reviewed-by: Andy Shevchenko Reviewed-by: Linus Walleij --- drivers/gpio/gpio-brcmstb.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpio/gpio-brcmstb.c b/drivers/gpio/gpio-brcmstb.c index 2352d099709c..4c35ed664f65 100644 --- a/drivers/gpio/gpio-brcmstb.c +++ b/drivers/gpio/gpio-brcmstb.c @@ -96,7 +96,7 @@ static int brcmstb_gpio_hwirq_to_offset(irq_hw_number_t h= wirq, } =20 static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank, - unsigned int hwirq, bool enable) + irq_hw_number_t hwirq, bool enable) { struct brcmstb_gpio_priv *priv =3D bank->parent_priv; u32 mask =3D BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank)); @@ -132,7 +132,7 @@ static void brcmstb_gpio_irq_mask(struct irq_data *d) struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct brcmstb_gpio_bank *bank =3D gpiochip_get_data(gc); =20 - brcmstb_gpio_set_imask(bank, d->hwirq, false); + brcmstb_gpio_set_imask(bank, irqd_to_hwirq(d), false); } =20 static void brcmstb_gpio_irq_unmask(struct irq_data *d) @@ -140,7 +140,7 @@ static void brcmstb_gpio_irq_unmask(struct irq_data *d) struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct brcmstb_gpio_bank *bank =3D gpiochip_get_data(gc); =20 - brcmstb_gpio_set_imask(bank, d->hwirq, true); + brcmstb_gpio_set_imask(bank, irqd_to_hwirq(d), true); } =20 static void brcmstb_gpio_irq_ack(struct irq_data *d) @@ -148,7 +148,7 @@ static void brcmstb_gpio_irq_ack(struct irq_data *d) struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct brcmstb_gpio_bank *bank =3D gpiochip_get_data(gc); struct brcmstb_gpio_priv *priv =3D bank->parent_priv; - u32 mask =3D BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank)); + u32 mask =3D BIT(brcmstb_gpio_hwirq_to_offset(irqd_to_hwirq(d), bank)); =20 gpio_generic_write_reg(&bank->chip, priv->reg_base + GIO_STAT(bank->id), mask); @@ -159,7 +159,7 @@ static int brcmstb_gpio_irq_set_type(struct irq_data *d= , unsigned int type) struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct brcmstb_gpio_bank *bank =3D gpiochip_get_data(gc); struct brcmstb_gpio_priv *priv =3D bank->parent_priv; - u32 mask =3D BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank)); + u32 mask =3D BIT(brcmstb_gpio_hwirq_to_offset(irqd_to_hwirq(d), bank)); u32 edge_insensitive, iedge_insensitive; u32 edge_config, iedge_config; u32 level, ilevel; @@ -236,7 +236,7 @@ static int brcmstb_gpio_irq_set_wake(struct irq_data *d= , unsigned int enable) struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct brcmstb_gpio_bank *bank =3D gpiochip_get_data(gc); struct brcmstb_gpio_priv *priv =3D bank->parent_priv; - u32 mask =3D BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank)); + u32 mask =3D BIT(brcmstb_gpio_hwirq_to_offset(irqd_to_hwirq(d), bank)); =20 /* * Do not do anything specific for now, suspend/resume callbacks will --=20 2.43.0 From nobody Sat Feb 7 19:45:25 2026 Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.166.231]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5853D1E7C18; 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Tue, 3 Feb 2026 15:45:30 -0800 (PST) From: Florian Fainelli To: linux-kernel@vger.kernel.org Cc: Doug Berger , Linus Walleij , Florian Fainelli , Broadcom internal kernel review list , Bartosz Golaszewski , Andy Shevchenko , Christophe Leroy , linux-gpio@vger.kernel.org (open list:GPIO SUBSYSTEM), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE) Subject: [PATCH v4 2/3] gpio: brcmstb: implement .irq_mask_ack Date: Tue, 3 Feb 2026 15:45:28 -0800 Message-ID: <20260203234529.1081148-3-florian.fainelli@broadcom.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260203234529.1081148-1-florian.fainelli@broadcom.com> References: <20260203234529.1081148-1-florian.fainelli@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Doug Berger The .irq_mask_ack operation is slightly more efficient than doing .irq_mask and .irq_ack separately. More importantly for this driver it bypasses the check of irqd_irq_masked ensuring a previously masked but still active interrupt gets remasked if unmasked at the hardware level. This allows the driver to more efficiently unmask the wake capable interrupts when quiescing without needing to enable the irqs individually to clear the irqd_irq_masked state. Reviewed-by: Linus Walleij Signed-off-by: Doug Berger Co-developed-by: Florian Fainelli Signed-off-by: Florian Fainelli Reviewed-by: Andy Shevchenko --- drivers/gpio/gpio-brcmstb.c | 30 +++++++++++++++++++++++++----- 1 file changed, 25 insertions(+), 5 deletions(-) diff --git a/drivers/gpio/gpio-brcmstb.c b/drivers/gpio/gpio-brcmstb.c index 4c35ed664f65..fff8e4100295 100644 --- a/drivers/gpio/gpio-brcmstb.c +++ b/drivers/gpio/gpio-brcmstb.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -// Copyright (C) 2015-2017 Broadcom +// Copyright (C) 2015-2017, 2026 Broadcom =20 #include #include @@ -95,15 +95,13 @@ static int brcmstb_gpio_hwirq_to_offset(irq_hw_number_t= hwirq, return hwirq - bank->chip.gc.offset; } =20 -static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank, - irq_hw_number_t hwirq, bool enable) +static void __brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank, + irq_hw_number_t hwirq, bool enable) { struct brcmstb_gpio_priv *priv =3D bank->parent_priv; u32 mask =3D BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank)); u32 imask; =20 - guard(gpio_generic_lock_irqsave)(&bank->chip); - imask =3D gpio_generic_read_reg(&bank->chip, priv->reg_base + GIO_MASK(bank->id)); if (enable) @@ -114,6 +112,13 @@ static void brcmstb_gpio_set_imask(struct brcmstb_gpio= _bank *bank, priv->reg_base + GIO_MASK(bank->id), imask); } =20 +static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank, + unsigned int hwirq, bool enable) +{ + guard(gpio_generic_lock_irqsave)(&bank->chip); + __brcmstb_gpio_set_imask(bank, hwirq, enable); +} + static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset) { struct brcmstb_gpio_priv *priv =3D brcmstb_gpio_gc_to_priv(gc); @@ -135,6 +140,20 @@ static void brcmstb_gpio_irq_mask(struct irq_data *d) brcmstb_gpio_set_imask(bank, irqd_to_hwirq(d), false); } =20 +static void brcmstb_gpio_irq_mask_ack(struct irq_data *d) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct brcmstb_gpio_bank *bank =3D gpiochip_get_data(gc); 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Tue, 3 Feb 2026 15:45:31 -0800 (PST) From: Florian Fainelli To: linux-kernel@vger.kernel.org Cc: Doug Berger , Florian Fainelli , Broadcom internal kernel review list , Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , Christophe Leroy , linux-gpio@vger.kernel.org (open list:GPIO SUBSYSTEM), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE) Subject: [PATCH v4 3/3] gpio: brcmstb: allow parent_irq to wake Date: Tue, 3 Feb 2026 15:45:29 -0800 Message-ID: <20260203234529.1081148-4-florian.fainelli@broadcom.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260203234529.1081148-1-florian.fainelli@broadcom.com> References: <20260203234529.1081148-1-florian.fainelli@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Doug Berger The classic parent_wake_irq can only occur after the system has been placed into a hardware managed power management state. This prevents its use for waking from software managed suspend states like s2idle. By allowing the parent_irq to be enabled for wake enabled GPIO during suspend, these GPIO can now be used to wake from these states. The 'suspended' boolean is introduced to support wake event accounting. Signed-off-by: Doug Berger [florian: port changes after generic gpio chip conversion] Signed-off-by: Florian Fainelli --- drivers/gpio/gpio-brcmstb.c | 85 +++++++++++++++++++++++++------------ 1 file changed, 57 insertions(+), 28 deletions(-) diff --git a/drivers/gpio/gpio-brcmstb.c b/drivers/gpio/gpio-brcmstb.c index fff8e4100295..d90e692b54a4 100644 --- a/drivers/gpio/gpio-brcmstb.c +++ b/drivers/gpio/gpio-brcmstb.c @@ -54,6 +54,7 @@ struct brcmstb_gpio_priv { int parent_irq; int num_gpios; int parent_wake_irq; + bool suspended; }; =20 #define MAX_GPIO_PER_BANK 32 @@ -240,6 +241,9 @@ static int brcmstb_gpio_priv_set_wake(struct brcmstb_gp= io_priv *priv, { int ret =3D 0; =20 + if (priv->parent_wake_irq =3D=3D priv->parent_irq) + return ret; + if (enable) ret =3D enable_irq_wake(priv->parent_wake_irq); else @@ -290,6 +294,11 @@ static void brcmstb_gpio_irq_bank_handler(struct brcms= tb_gpio_bank *bank) while ((status =3D brcmstb_gpio_get_active_irqs(bank))) { unsigned int offset; =20 + if (priv->suspended && bank->wake_active & status) { + priv->suspended =3D false; + pm_wakeup_event(&priv->pdev->dev, 0); + } + for_each_set_bit(offset, &status, 32) { if (offset >=3D bank->width) dev_warn(&priv->pdev->dev, @@ -463,18 +472,18 @@ static int brcmstb_gpio_irq_setup(struct platform_dev= ice *pdev, } =20 if (of_property_read_bool(np, "wakeup-source")) { + /* + * Set wakeup capability so we can process boot-time + * "wakeups" (e.g., from S5 cold boot). + */ + device_set_wakeup_capable(dev, true); + device_wakeup_enable(dev); priv->parent_wake_irq =3D platform_get_irq(pdev, 1); if (priv->parent_wake_irq < 0) { - priv->parent_wake_irq =3D 0; + priv->parent_wake_irq =3D priv->parent_irq; dev_warn(dev, "Couldn't get wake IRQ - GPIOs will not be able to wake from sleep"); } else { - /* - * Set wakeup capability so we can process boot-time - * "wakeups" (e.g., from S5 cold boot) - */ - device_set_wakeup_capable(dev, true); - device_wakeup_enable(dev); err =3D devm_request_irq(dev, priv->parent_wake_irq, brcmstb_gpio_wake_irq_handler, IRQF_SHARED, @@ -485,6 +494,7 @@ static int brcmstb_gpio_irq_setup(struct platform_devic= e *pdev, goto out_free_domain; } } + priv->irq_chip.irq_set_wake =3D brcmstb_gpio_irq_set_wake; } =20 priv->irq_chip.name =3D dev_name(dev); @@ -495,9 +505,6 @@ static int brcmstb_gpio_irq_setup(struct platform_devic= e *pdev, priv->irq_chip.irq_ack =3D brcmstb_gpio_irq_ack; priv->irq_chip.irq_set_type =3D brcmstb_gpio_irq_set_type; =20 - if (priv->parent_wake_irq) - priv->irq_chip.irq_set_wake =3D brcmstb_gpio_irq_set_wake; - irq_set_chained_handler_and_data(priv->parent_irq, brcmstb_gpio_irq_handler, priv); irq_set_status_flags(priv->parent_irq, IRQ_DISABLE_UNLAZY); @@ -520,16 +527,11 @@ static void brcmstb_gpio_bank_save(struct brcmstb_gpi= o_priv *priv, priv->reg_base + GIO_BANK_OFF(bank->id, i)); } =20 -static void brcmstb_gpio_quiesce(struct device *dev, bool save) +static void brcmstb_gpio_quiesce(struct brcmstb_gpio_priv *priv, bool save) { - struct brcmstb_gpio_priv *priv =3D dev_get_drvdata(dev); struct brcmstb_gpio_bank *bank; u32 imask; =20 - /* disable non-wake interrupt */ - if (priv->parent_irq >=3D 0) - disable_irq(priv->parent_irq); - list_for_each_entry(bank, &priv->bank_list, node) { if (save) brcmstb_gpio_bank_save(priv, bank); @@ -547,8 +549,13 @@ static void brcmstb_gpio_quiesce(struct device *dev, b= ool save) =20 static void brcmstb_gpio_shutdown(struct platform_device *pdev) { + struct brcmstb_gpio_priv *priv =3D dev_get_drvdata(&pdev->dev); + + if (priv->parent_irq > 0) + disable_irq(priv->parent_irq); + /* Enable GPIO for S5 cold boot */ - brcmstb_gpio_quiesce(&pdev->dev, false); + brcmstb_gpio_quiesce(priv, false); } =20 static void brcmstb_gpio_bank_restore(struct brcmstb_gpio_priv *priv, @@ -564,7 +571,30 @@ static void brcmstb_gpio_bank_restore(struct brcmstb_g= pio_priv *priv, =20 static int brcmstb_gpio_suspend(struct device *dev) { - brcmstb_gpio_quiesce(dev, true); + struct brcmstb_gpio_priv *priv =3D dev_get_drvdata(dev); + + if (priv->parent_irq > 0) + priv->suspended =3D true; + + return 0; +} + +static int brcmstb_gpio_suspend_noirq(struct device *dev) +{ + struct brcmstb_gpio_priv *priv =3D dev_get_drvdata(dev); + + /* Catch any wakeup sources occurring between suspend and noirq */ + if (!priv->suspended) + return -EBUSY; + + if (priv->parent_irq > 0) + disable_irq(priv->parent_irq); + + brcmstb_gpio_quiesce(priv, true); + + if (priv->parent_wake_irq) + enable_irq(priv->parent_irq); + return 0; } =20 @@ -572,25 +602,24 @@ static int brcmstb_gpio_resume(struct device *dev) { struct brcmstb_gpio_priv *priv =3D dev_get_drvdata(dev); struct brcmstb_gpio_bank *bank; - bool need_wakeup_event =3D false; =20 - list_for_each_entry(bank, &priv->bank_list, node) { - need_wakeup_event |=3D !!__brcmstb_gpio_get_active_irqs(bank); - brcmstb_gpio_bank_restore(priv, bank); - } + if (priv->parent_wake_irq) + disable_irq(priv->parent_irq); =20 - if (priv->parent_wake_irq && need_wakeup_event) - pm_wakeup_event(dev, 0); + priv->suspended =3D false; + + list_for_each_entry(bank, &priv->bank_list, node) + brcmstb_gpio_bank_restore(priv, bank); =20 - /* enable non-wake interrupt */ - if (priv->parent_irq >=3D 0) + if (priv->parent_irq > 0) enable_irq(priv->parent_irq); =20 return 0; } =20 static const struct dev_pm_ops brcmstb_gpio_pm_ops =3D { - .suspend_noirq =3D pm_sleep_ptr(brcmstb_gpio_suspend), + .suspend =3D pm_sleep_ptr(brcmstb_gpio_suspend), + .suspend_noirq =3D pm_sleep_ptr(brcmstb_gpio_suspend_noirq), .resume_noirq =3D pm_sleep_ptr(brcmstb_gpio_resume), }; =20 --=20 2.43.0