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Tue, 03 Feb 2026 15:18:32 -0800 (PST) Received: from iku.Home ([2a06:5906:61b:2d00:2e50:5c7f:afca:5f9f]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-436180647aasm1739832f8f.41.2026.02.03.15.18.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Feb 2026 15:18:31 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Thomas Gleixner , Philipp Zabel , Geert Uytterhoeven , Magnus Damm Cc: linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 5/6] irqchip/renesas-rzv2h: Add CA55 software interrupt support Date: Tue, 3 Feb 2026 23:18:22 +0000 Message-ID: <20260203231823.208661-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260203231823.208661-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260203231823.208661-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar The Renesas RZ/V2H ICU provides a software interrupt register (ICU_SWINT) that allows software to explicitly assert interrupts toward individual CA55 cores. Writing BIT(n) to ICU_SWINT triggers the corresponding interrupt. Extend the RZ/V2H ICU IRQ domain to include CA55 software interrupts as part of the hierarchical IRQ numbering, backed by the ICU_SWINT register. SW interrupts can now be triggered when GENERIC_IRQ_INJECTION is enabled. Signed-off-by: Lad Prabhakar --- v1->v2: - Made CA55 SW interrupt as part of ICU IRQ domain. - Implemented rzv2h_icu_irq_set_irqchip_state() to trigger SWINT. - Updated commit message accordingly. --- drivers/irqchip/irq-renesas-rzv2h.c | 89 ++++++++++++++++++++++++++++- 1 file changed, 86 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-rene= sas-rzv2h.c index 6c7bbb04c6e4..a2ff7524889c 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -29,7 +30,10 @@ #define ICU_TINT_START (ICU_IRQ_LAST + 1) #define ICU_TINT_COUNT 32 #define ICU_TINT_LAST (ICU_TINT_START + ICU_TINT_COUNT - 1) -#define ICU_NUM_IRQ (ICU_TINT_LAST + 1) +#define ICU_CA55_INT_START (ICU_TINT_LAST + 1) +#define ICU_CA55_INT_COUNT 4 +#define ICU_CA55_INT_LAST (ICU_CA55_INT_START + ICU_= CA55_INT_COUNT - 1) +#define ICU_NUM_IRQ (ICU_CA55_INT_LAST + 1) =20 /* Registers */ #define ICU_NSCNT 0x00 @@ -42,6 +46,7 @@ #define ICU_TSCLR 0x24 #define ICU_TITSR(k) (0x28 + (k) * 4) #define ICU_TSSR(k) (0x30 + (k) * 4) +#define ICU_SWINT 0x130 #define ICU_DMkSELy(k, y) (0x420 + (k) * 0x20 + (y) * 4) #define ICU_DMACKSELk(k) (0x500 + (k) * 4) =20 @@ -248,6 +253,30 @@ static void rzv2h_icu_irq_enable(struct irq_data *d) irq_chip_enable_parent(d); } =20 +static int rzv2h_icu_irq_set_irqchip_state(struct irq_data *d, + enum irqchip_irq_state which, + bool state) +{ + unsigned int hwirq =3D irqd_to_hwirq(d); + struct rzv2h_icu_priv *priv; + unsigned int bit; + + if (hwirq < ICU_CA55_INT_START || hwirq > ICU_CA55_INT_LAST || + which !=3D IRQCHIP_STATE_PENDING) + return irq_chip_set_parent_state(d, which, state); + + if (!state) + return 0; + + priv =3D irq_data_to_priv(d); + bit =3D BIT(hwirq - ICU_CA55_INT_START); + + guard(raw_spinlock)(&priv->lock); + /* Trigger the software interrupt */ + writel_relaxed(bit, priv->base + ICU_SWINT); + return 0; +} + static int rzv2h_nmi_set_type(struct irq_data *d, unsigned int type) { struct rzv2h_icu_priv *priv =3D irq_data_to_priv(d); @@ -429,6 +458,7 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsi= gned int type) =20 static int rzv2h_icu_set_type(struct irq_data *d, unsigned int type) { + unsigned int gic_type =3D IRQ_TYPE_LEVEL_HIGH; unsigned int hw_irq =3D irqd_to_hwirq(d); int ret; =20 @@ -445,6 +475,11 @@ static int rzv2h_icu_set_type(struct irq_data *d, unsi= gned int type) /* TINT */ ret =3D rzv2h_tint_set_type(d, type); break; + case ICU_CA55_INT_START ... ICU_CA55_INT_LAST: + /* CA55 Software Interrupts have EDGE_RISING type */ + gic_type =3D IRQ_TYPE_EDGE_RISING; + ret =3D 0; + break; default: ret =3D -EINVAL; } @@ -452,7 +487,7 @@ static int rzv2h_icu_set_type(struct irq_data *d, unsig= ned int type) if (ret) return ret; =20 - return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); + return irq_chip_set_type_parent(d, gic_type); } =20 static int rzv2h_irqc_irq_suspend(void *data) @@ -501,7 +536,7 @@ static const struct irq_chip rzv2h_icu_chip =3D { .irq_disable =3D rzv2h_icu_irq_disable, .irq_enable =3D rzv2h_icu_irq_enable, .irq_get_irqchip_state =3D irq_chip_get_parent_state, - .irq_set_irqchip_state =3D irq_chip_set_parent_state, + .irq_set_irqchip_state =3D rzv2h_icu_irq_set_irqchip_state, .irq_retrigger =3D irq_chip_retrigger_hierarchy, .irq_set_type =3D rzv2h_icu_set_type, .irq_set_affinity =3D irq_chip_set_affinity_parent, @@ -571,6 +606,50 @@ static int rzv2h_icu_parse_interrupts(struct rzv2h_icu= _priv *priv, struct device return 0; } =20 +static irqreturn_t rzv2h_icu_swint_irq(int irq, void *data) +{ + u8 cpu =3D *(u8 *)data; + + pr_debug("SWINT interrupt for CA55 core %u\n", cpu); + return IRQ_HANDLED; +} + +static int rzv2h_icu_setup_irqs(struct platform_device *pdev, + struct irq_domain *irq_domain) +{ + bool irq_inject =3D IS_ENABLED(CONFIG_GENERIC_IRQ_INJECTION); + static const char * const rzv2h_swint_names[] =3D { + "int-ca55-0", "int-ca55-1", + "int-ca55-2", "int-ca55-3", + }; + static const u8 swint_idx[] =3D { 0, 1, 2, 3 }; + struct device *dev =3D &pdev->dev; + struct irq_fwspec fwspec; + unsigned int virq; + unsigned int i; + int ret; + + for (i =3D 0; i < ICU_CA55_INT_COUNT && irq_inject; i++) { + fwspec.fwnode =3D irq_domain->fwnode; + fwspec.param_count =3D 2; + fwspec.param[0] =3D ICU_CA55_INT_START + i; + fwspec.param[1] =3D IRQ_TYPE_EDGE_RISING; + + virq =3D irq_create_fwspec_mapping(&fwspec); + if (!virq) + return dev_err_probe(dev, -EINVAL, "failed to create IRQ mapping for %s= \n", + rzv2h_swint_names[i]); + + ret =3D devm_request_irq(dev, virq, rzv2h_icu_swint_irq, 0, dev_name(dev= ), + (void *)&swint_idx[i]); + if (ret) + return dev_err_probe(dev, ret, "Failed to request %s IRQ\n", + rzv2h_swint_names[i]); + } + + return 0; +} + static int rzv2h_icu_probe_common(struct platform_device *pdev, struct dev= ice_node *parent, const struct rzv2h_hw_info *hw_info) { @@ -626,6 +705,10 @@ static int rzv2h_icu_probe_common(struct platform_devi= ce *pdev, struct device_no =20 register_syscore(&rzv2h_irqc_syscore); =20 + ret =3D rzv2h_icu_setup_irqs(pdev, irq_domain); + if (ret) + goto pm_put; + /* * coccicheck complains about a missing put_device call before returning,= but it's a false * positive. We still need dev after successfully returning from this fun= ction. --=20 2.52.0