From nobody Mon Feb 9 14:43:55 2026 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9558E27AC45 for ; Tue, 3 Feb 2026 23:18:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770160712; cv=none; b=la4LR63HCNIREP0prwPuAj+NxK7zzbEcoBMIQXw9gflcGwurIZfTwceVObbitHcgmifAspF4SN0u2BfZk6Z4YXNLUbO7W5aS7JmwkRe2qHIr+QBqB78bLAMBr2IfSUFF+QWsLIH/02ySoADasREOX2E0vaUnFnT7HZz2huO9FDY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770160712; c=relaxed/simple; bh=Yw1CvyzkH+FPw285yDEXihARjsHXEfYJtM/N4/sl9Qk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cl96WrSAvSSCj6+adcVc1M4qIHoJ6Lc3EhhXPUbwoU3Z5ljaS7jK3FKuudzLzZaXq1frcl1USFhfjkbFto3sBlGGBDdK8feQVmRdhaZ6HIXORdFPB7ns6X0SAtTw6ZVNHXkGPGmhlgrax0+OxWNR3pXlYMBsE55PL/TpsOfbhHE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=fQTjeBWc; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="fQTjeBWc" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-47fedb7c68dso1154265e9.2 for ; Tue, 03 Feb 2026 15:18:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770160708; x=1770765508; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qXpA/VTDvHzRO9xU14YwumW5QB6sAtjndCGdsJjR57o=; b=fQTjeBWceGl6glk7UodYb6gdEfQkwk5mOF5ybwa8740dKhBXCQxmPQNiuD6X37+Le2 /HDzclLkiFI2YP63WLHfv2FEj5qa1CPvaE2NiqElF3wfijIXqqthpdBDiJDsmmiWm5JG q4c6f8osuQwJ7ssdn8KVCOJ5EmD6wLcUdhfssNlfw973ioYZB4ptj5qIS30rOX5bISjb KmW7sE9nTcQtdm2x2ol4UxurFTSgZNHH7t1yJSV40BLsqLOqbd4f4NlmUHwtkVfQ0qJt nUp5BA4lL1dr5/JW5g44DOJqtBqd4oTo6+k03GY9Ayje/e5JD26cvaJWv5DgqX/MYTCd WOpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770160708; x=1770765508; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=qXpA/VTDvHzRO9xU14YwumW5QB6sAtjndCGdsJjR57o=; b=UGzg407PwZWun96frMkzyV12ur/NKnKV37CL3JsJomBFmTUjrw28tyoOWW8Ybijzp2 /DDU4OOfiL2QC/b0gHLVFFm1ldX8W3sYenBr1bhLRRxPFIjzxeD5W/hyHeq/oeKc4WmV iJt+UkBwM2QpHlZroLC6pKAYvcIVSQKmLiy06amc557Tb/L9wp8EJKdDaqjWIuOqG3NX UIYsnJhxc6gVxECGyV261i9/4n8+gcdC9LasW0DObsIbMZpjWczEp6M6Wm/PPxmJNqsU ayNIpsqPhc68N5+zlhpHR3ryAuRoRuty1ViVHlQ6JuzYNWK8JLU9ASDj0vhmJ0gLUsnC DaaA== X-Gm-Message-State: AOJu0YxlLKb1RfsoOgn/AtvfqdAE4gsD+aeHcX0MASo+/EXhYkeN3qbp queNjvc+/xEUc8nz+gsZ8vdRz96Sp2p3gxwQz7doncE2K4lWZZDPa8tA X-Gm-Gg: AZuq6aJsSxKel6ubvAnPElNUZCUJ/tfiRQ8xrgsbSyp7llREa7GL2N6by6CucBkg/w+ HtzYCRxNHdHPKwlrTMHbjka1SUCwff15V3Zjc6Qhd+EAIt7w/xsoIvDkHHU3w4SjYZvyvzB6Jlr RLQhLUuJNLy+9zgZPRFzLlwNkqyf6V3lbuiPjrwO9mM3+NlvYs4/I8CrQ2v/JySdbEazFxwp+Xb BHI1GtO7jqHPEjOyYCWmOiyn5sWhZT/u3qYraZ7K9dyBniBoEkpiiOmq6O2SWwSVCgOv2udlbR/ sPZqbOBUez6DOpDFMlMCFqsVgURfi0pOIe7j4BnCeY+zbdcpEDZrEupvubQetb0bl86JPxB8tbZ 3urNElWT+YDnp0G1Vdor/j2QRgoViHI2oNocpBXtQ3Z3fixEB3qtdWVCyKaSjIWLOIWUpLsTIez awppWc9+n9sMShzydWM63dOIegu2+dL0OeaPlw9qFFMI8gtHHf29e8oCZ3wcSfmOvzta5RGfIQK l/GAU26OIHzKGWNqiG5Ow2MS362ePYY/tY= X-Received: by 2002:a05:600c:354f:b0:47e:e2eb:bc22 with SMTP id 5b1f17b1804b1-4830e92457fmr16025705e9.5.1770160708396; Tue, 03 Feb 2026 15:18:28 -0800 (PST) Received: from iku.Home ([2a06:5906:61b:2d00:2e50:5c7f:afca:5f9f]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-436180647aasm1739832f8f.41.2026.02.03.15.18.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Feb 2026 15:18:27 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Thomas Gleixner , Philipp Zabel , Geert Uytterhoeven , Magnus Damm Cc: linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 1/6] irqchip/renesas-rzv2h: Use local node pointer Date: Tue, 3 Feb 2026 23:18:18 +0000 Message-ID: <20260203231823.208661-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260203231823.208661-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260203231823.208661-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Avoid dereferencing pdev->dev.of_node again in rzv2h_icu_probe_common(). Reuse the already available local node pointer when mapping the ICU register space. Signed-off-by: Lad Prabhakar --- v1->v2: - No change. --- drivers/irqchip/irq-renesas-rzv2h.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-rene= sas-rzv2h.c index da2bc43a0e12..20c0cd11ef25 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -570,7 +570,7 @@ static int rzv2h_icu_probe_common(struct platform_devic= e *pdev, struct device_no =20 platform_set_drvdata(pdev, rzv2h_icu_data); =20 - rzv2h_icu_data->base =3D devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, = NULL); + rzv2h_icu_data->base =3D devm_of_iomap(&pdev->dev, node, 0, NULL); if (IS_ERR(rzv2h_icu_data->base)) return PTR_ERR(rzv2h_icu_data->base); =20 --=20 2.52.0 From nobody Mon Feb 9 14:43:55 2026 Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6EECD318B80 for ; Tue, 3 Feb 2026 23:18:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770160713; cv=none; b=pgjR2n5t6cPrwe0oOKDbd3Uo24oeLcFC6OCGz1UUPfGxbRr7CqW6d9nb1g9MPTi8b1R9wDefbBaM8dbhm5QUhMOzfz7IADogShsIQMDnq4/AsBnIlZUG3atgghHdRpyhk2JUz7R7nPX9bpeW7WjFKr4z/dVXfdfTaVFYbBlTHC4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770160713; c=relaxed/simple; bh=a8vKkne77LOvoIoaom92AJVMtkb1e2GLPRNFL48TDnQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TpLe6VYSAEcKRzvjmVHnQFvKxmxD9xuLI4ywXHSkJfgnK6gtH40gkSj8zn4Oi8GKYVqmZKwn+cD8gwTZPbZqE3kuW9HADf8s35TLjqtOrdxeQS8uZ7WKqkUAxm+tx8rbUurwXozHYithXYCnLYUZHYdgx9ypLkLNkUA9xNjRAAs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=HBWzV6F/; arc=none smtp.client-ip=209.85.221.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="HBWzV6F/" Received: by mail-wr1-f44.google.com with SMTP id ffacd0b85a97d-4359a316d89so4660998f8f.0 for ; Tue, 03 Feb 2026 15:18:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770160709; x=1770765509; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=omvaMk73tVK4sT4r3gG1rDVi2ZZXxOVPSdZBLdHJNa8=; b=HBWzV6F/80GnojClB05uBojqnuSnx9mgfqAAl7lM37z4401E3eNpS18Ydghnr73D/U ykLUy7jyJuPDp1/CU+CjxJNH0Xft+znp6hYiSq5RIfDPz+xGx6LgGxh0wAkMt9dLq7RC X/QINI8EIRRRzJ3jyQmf/PyCtOgce0lpfuZVX7AzLICKEn6RBx3/+k1FpivI/xF+571A 7t/bAb2Pd0dxH60b0sjnvFN/ZZ9xfnvCCVOY+tojmgpCW5gnc+eUvEwizePvNx/r9GIS 2GirZ/kXVljR/easHZ0xKZM1Ca8WrU3Vao1KsqdBg6bRl1vnrrEHXdk9HvNt2Q4txmep Yc3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770160709; x=1770765509; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=omvaMk73tVK4sT4r3gG1rDVi2ZZXxOVPSdZBLdHJNa8=; b=JGeAcVSt4nED0yf6+DNDp5pYRye6890ddDE1R1YeKR/bICjAmnlmDA8ij61yU3aPq7 MWeDuClcLfGLwDYQx/qJ1RqP7AEi5+c9aLi4MJ8P3kIVghdCqemaNQV1zn6DkrNdmpM3 o+IhQTf20mVHoj+898UKAeu/j+Nk7U1lzU7CCdMJFBF61D0Z29ihdkz+1FKZrx1BIvwm +boHHmI10n0Zf2LNzPhAwLPUTXGIbfNLB3CVgj95Z1j8sbY/HcKRoHRYz1hNN4UuDTl0 hV7qwktZq02CAA0E0RQjo2FV36xqAUWja10CdO3MA+6Fns8Fa+qqvWpvKq0AYAejIflL QXjQ== X-Gm-Message-State: AOJu0YxQGqUn0MIKEoS8VMd6GL2wOLbKLrYVcw6bIUQ4nrNocoa5INOa w1ae6bWDULnHTSEYLs3NWOi5HBB58M1q7m++ECrii0/HBq1vvrIwaaZZ X-Gm-Gg: AZuq6aLWRR/8VqKHUaB7rZcU0RmWMGYgLbcv0zuujsm6ckXQ1htOFn7e+pbzh9zcrQp Mp+pDXi5SP+QcCCn1AiBzMInoqvNv0TgzHkk+u4DiAMm1RWqWVb+D1IBaVQqTt1iOt6mgz8pTdw CuKs05RgYEpIEQlh4xFcgc8f1wPuotQE1PdEf5W7iVRDPUE2mly5vDInhGl7U7d1g0J5n9eGrGL xyt7alng5+9CEKOLAZgLBkVvfQqjR7hz/itfo2Y20710OofIHeUT/e2DTyvnQAJVFBhFerB568e HcQ9l4Ht+uR8f8CF5QChG2y8jwSm+y1Ti8P9GS5n+z3OYZwCWJrSk4H+72iKTf7jgyJ4vrjtjck rKOgV432mXMiFYpG9n+T3sPLvvr+Lg6/MpENw3jfQlP3WnUemBkExQsq/8YSR8DRJ9tvYFscPtT u6F0boL15wXqp0SkeZ54ddSxipolfmXkzRSgFG3sJ2vrSD6Xli/+HJ1LUscerUuytssW9zZwGQ3 gcj6IXEZCs7VpygVh6sixXR X-Received: by 2002:a05:6000:2211:b0:430:f3fb:35fa with SMTP id ffacd0b85a97d-43618061b94mr1325430f8f.57.1770160709500; Tue, 03 Feb 2026 15:18:29 -0800 (PST) Received: from iku.Home ([2a06:5906:61b:2d00:2e50:5c7f:afca:5f9f]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-436180647aasm1739832f8f.41.2026.02.03.15.18.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Feb 2026 15:18:28 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Thomas Gleixner , Philipp Zabel , Geert Uytterhoeven , Magnus Damm Cc: linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 2/6] irqchip/renesas-rzv2h: Use local device pointer in ICU probe Date: Tue, 3 Feb 2026 23:18:19 +0000 Message-ID: <20260203231823.208661-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260203231823.208661-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260203231823.208661-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Use a local struct device pointer in rzv2h_icu_probe_common() to avoid repeated dereferencing of pdev->dev. Signed-off-by: Lad Prabhakar --- v1->v2: - No change. --- drivers/irqchip/irq-renesas-rzv2h.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-rene= sas-rzv2h.c index 20c0cd11ef25..766b981cf3d8 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -555,57 +555,58 @@ static int rzv2h_icu_probe_common(struct platform_dev= ice *pdev, struct device_no { struct irq_domain *irq_domain, *parent_domain; struct device_node *node =3D pdev->dev.of_node; + struct device *dev =3D &pdev->dev; struct reset_control *resetn; int ret; =20 parent_domain =3D irq_find_host(parent); if (!parent_domain) { - dev_err(&pdev->dev, "cannot find parent domain\n"); + dev_err(dev, "cannot find parent domain\n"); return -ENODEV; } =20 - rzv2h_icu_data =3D devm_kzalloc(&pdev->dev, sizeof(*rzv2h_icu_data), GFP_= KERNEL); + rzv2h_icu_data =3D devm_kzalloc(dev, sizeof(*rzv2h_icu_data), GFP_KERNEL); if (!rzv2h_icu_data) return -ENOMEM; =20 platform_set_drvdata(pdev, rzv2h_icu_data); =20 - rzv2h_icu_data->base =3D devm_of_iomap(&pdev->dev, node, 0, NULL); + rzv2h_icu_data->base =3D devm_of_iomap(dev, node, 0, NULL); if (IS_ERR(rzv2h_icu_data->base)) return PTR_ERR(rzv2h_icu_data->base); =20 ret =3D rzv2h_icu_parse_interrupts(rzv2h_icu_data, node); if (ret) { - dev_err(&pdev->dev, "cannot parse interrupts: %d\n", ret); + dev_err(dev, "cannot parse interrupts: %d\n", ret); return ret; } =20 - resetn =3D devm_reset_control_get_exclusive_deasserted(&pdev->dev, NULL); + resetn =3D devm_reset_control_get_exclusive_deasserted(dev, NULL); if (IS_ERR(resetn)) { ret =3D PTR_ERR(resetn); - dev_err(&pdev->dev, "failed to acquire deasserted reset: %d\n", ret); + dev_err(dev, "failed to acquire deasserted reset: %d\n", ret); return ret; } =20 - ret =3D devm_pm_runtime_enable(&pdev->dev); + ret =3D devm_pm_runtime_enable(dev); if (ret < 0) { - dev_err(&pdev->dev, "devm_pm_runtime_enable failed, %d\n", ret); + dev_err(dev, "devm_pm_runtime_enable failed, %d\n", ret); return ret; } =20 - ret =3D pm_runtime_resume_and_get(&pdev->dev); + ret =3D pm_runtime_resume_and_get(dev); if (ret < 0) { - dev_err(&pdev->dev, "pm_runtime_resume_and_get failed: %d\n", ret); + dev_err(dev, "pm_runtime_resume_and_get failed: %d\n", ret); return ret; } =20 raw_spin_lock_init(&rzv2h_icu_data->lock); =20 irq_domain =3D irq_domain_create_hierarchy(parent_domain, 0, ICU_NUM_IRQ, - dev_fwnode(&pdev->dev), &rzv2h_icu_domain_ops, + dev_fwnode(dev), &rzv2h_icu_domain_ops, rzv2h_icu_data); if (!irq_domain) { - dev_err(&pdev->dev, "failed to add irq domain\n"); + dev_err(dev, "failed to add irq domain\n"); ret =3D -ENOMEM; goto pm_put; } @@ -616,12 +617,12 @@ static int rzv2h_icu_probe_common(struct platform_dev= ice *pdev, struct device_no =20 /* * coccicheck complains about a missing put_device call before returning,= but it's a false - * positive. We still need &pdev->dev after successfully returning from t= his function. + * positive. We still need dev after successfully returning from this fun= ction. */ return 0; =20 pm_put: - pm_runtime_put(&pdev->dev); + pm_runtime_put(dev); =20 return ret; } --=20 2.52.0 From nobody Mon Feb 9 14:43:55 2026 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B1BF31C56D for ; Tue, 3 Feb 2026 23:18:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770160714; cv=none; b=XNwFqkDTiDH9jte4U0ASDbJ704KCiMdW993HUMhMLCGGEyB/jVLiH0NtnWPHIhMKpVH/03BBE+TYjAgg3/gnxXFCqtxHhzEmWiGcFQy0S736U2S5YzU6lBNmprZwWeNYAHWVQS/KwjDqX34l3O5m2mbr9ey2SFv9eh8FIIlNkrI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770160714; c=relaxed/simple; bh=Brp5qrTUAsCcym21xMYfoZJ4cOoimrBdqQAWm42fdC8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bG071e1AVu+j3biB0wjZ6PVn0ot5o0++JJvZDfZA7vjTYYpWGYVoU2ekcUrO+Rks1fK6k9b8Rm7cM4JOH54RZ8sT3pTbTYhVCCJGdw8zyqgiX1GpkHrnn0XeuWKnlKDpsBVKP/htGyY4vDHKYJCTKHiBmyZ18D2Rhn/JkILmzdI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Pg6jk0bl; arc=none smtp.client-ip=209.85.221.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Pg6jk0bl" Received: by mail-wr1-f47.google.com with SMTP id ffacd0b85a97d-43591b55727so5424461f8f.3 for ; Tue, 03 Feb 2026 15:18:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770160711; x=1770765511; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CJhmxJ+KI+ZTVz7UVfJJ3AAKvigbqAtSvhVOs0qF4Uk=; b=Pg6jk0blnl0ypZcxqrSrY1Rr5XTnNY9xRgiIl/i+fRYTmxkDjoKP78nR5aV2jfmG2/ NJzewdkgKT+2V0B9t+z98PyONWjKRtVob/rdJKTnAdlF+4xAKRn8OvpnYqc2CQ6iH/KX w2Cc8JcC+IidDxVm3x2LNmYgR0ifMRXmyewS6CPFRLfjB4qcili3skpDEhqYNmn4L+pO MMQ34mC+McrlgXONZOQik6muKgpP+p3zQGO9z6tB+E+HYzcMZJNg76U95IA1GKAWWcCi 2FGqE8c531umK4CffbKjxoSCxG4mjw0oRgfqsrHfrE2qNogogS9Cqz2t26tL8M82+f3h bLRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770160711; x=1770765511; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=CJhmxJ+KI+ZTVz7UVfJJ3AAKvigbqAtSvhVOs0qF4Uk=; b=pv+x4r44w6Ly9T8a214F81Nqrni3T3MJOxQjHnswdwr1+cQFhzanCJD/+LXoShn7mM 7+pR1tv7nnvmWhRGlVERGqU6LXuqrD+CFzeCZgWYZ1L3duLQnQY8aHki3k+AaOUql9Jp 2Z4sISc6EZ5enV54YZwcGqk6GM7rHlt9ttDpeA1TxTxsxGtGwtcMahcrmSva9/lG2o+L iABnal5dYgg/vSOE/i372QM3qWetm69ieh0q44GIjY/ekQZwR09/wpx8MwSdPUfzaBUW MrQoB8uc61KyRf9OHeHVmNdyZ1eSXK4f/46EpDbUAgseorPj2v+TCxkJGCn6LBgvM1xO ur/A== X-Gm-Message-State: AOJu0YwknmjKNyJAyhVCNBkmcpe4o8TqL80Umk/F2R/sv0dW+VAMeO3Z moe3olXkZCZ/+K3qJEGCQHKpL1uHymhnsIOsLn2IjYOi8Q7HiO7sIjYB X-Gm-Gg: AZuq6aJOPhYyM1AyM/dqO7HWUdNsZnW/p3v92/1Y1ANJoLIbuZO+AOKMvJdGOf8jXU+ Fsf8zuGQlxlbgjGLZG/gS65jXgVhR8X8YBB+VxyxvbmPucL6n3XdUnBx/1Ap/EP7+Cp6oz5Wkkf K9laHeh1xftdXyanSaDVc3Q2Uh9AKyhXLhwORAsODSiAOASFv1ERSB5zZaf3wNYhhXAmQ/bMAZ7 JKVJO4NCUsmCVyX3BiPXHZzLgguqg1lbuGwLRpY6CQ3fuBWKvVPOUkE8Jnc6awvg2hx7UD4LxQ5 ziJQv5v4/gl7yuJOW6LK80D1kFWgvY/b7gfAOYatsOQkh7ts+QZud8lWDddQTCuvT0MXlIDKnHG Dck4UQL+lxWWiMocCEi1tO4wz2U7EZtW2kEWdRUMpn9Q9HxsX0ASrAcJJgGt+1wExYzWK3N4Bus huOcrJ9T80wL1QEUlwMvl6aZdq3RVJB4MhuIWwNHRvjRWlVqVGGrf7/M0UBnQMfEHV9hQySUFwJ Kz1xIq10BDVXP9XyVFGo/QU X-Received: by 2002:a05:6000:26c4:b0:436:173c:b8e3 with SMTP id ffacd0b85a97d-43618056bc4mr1401351f8f.29.1770160710658; Tue, 03 Feb 2026 15:18:30 -0800 (PST) Received: from iku.Home ([2a06:5906:61b:2d00:2e50:5c7f:afca:5f9f]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-436180647aasm1739832f8f.41.2026.02.03.15.18.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Feb 2026 15:18:29 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Thomas Gleixner , Philipp Zabel , Geert Uytterhoeven , Magnus Damm Cc: linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 3/6] irqchip/renesas-rzv2h: Switch to using dev_err_probe() Date: Tue, 3 Feb 2026 23:18:20 +0000 Message-ID: <20260203231823.208661-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260203231823.208661-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260203231823.208661-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Make use of dev_err_probe() to simplify rzv2h_icu_probe_common(). Keep dev_err() for -ENOMEM paths, as dev_err_probe() does not print for allocation failures, ensuring they remain visible in logs. Signed-off-by: Lad Prabhakar --- v1->v2: - No change. --- drivers/irqchip/irq-renesas-rzv2h.c | 32 ++++++++++------------------- 1 file changed, 11 insertions(+), 21 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-rene= sas-rzv2h.c index 766b981cf3d8..4aa772ba1a1f 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -560,10 +560,8 @@ static int rzv2h_icu_probe_common(struct platform_devi= ce *pdev, struct device_no int ret; =20 parent_domain =3D irq_find_host(parent); - if (!parent_domain) { - dev_err(dev, "cannot find parent domain\n"); - return -ENODEV; - } + if (!parent_domain) + return dev_err_probe(dev, -ENODEV, "cannot find parent domain\n"); =20 rzv2h_icu_data =3D devm_kzalloc(dev, sizeof(*rzv2h_icu_data), GFP_KERNEL); if (!rzv2h_icu_data) @@ -576,29 +574,21 @@ static int rzv2h_icu_probe_common(struct platform_dev= ice *pdev, struct device_no return PTR_ERR(rzv2h_icu_data->base); =20 ret =3D rzv2h_icu_parse_interrupts(rzv2h_icu_data, node); - if (ret) { - dev_err(dev, "cannot parse interrupts: %d\n", ret); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, "cannot parse interrupts\n"); =20 resetn =3D devm_reset_control_get_exclusive_deasserted(dev, NULL); - if (IS_ERR(resetn)) { - ret =3D PTR_ERR(resetn); - dev_err(dev, "failed to acquire deasserted reset: %d\n", ret); - return ret; - } + if (IS_ERR(resetn)) + return dev_err_probe(dev, PTR_ERR(resetn), + "failed to acquire deasserted reset\n"); =20 ret =3D devm_pm_runtime_enable(dev); - if (ret < 0) { - dev_err(dev, "devm_pm_runtime_enable failed, %d\n", ret); - return ret; - } + if (ret < 0) + return dev_err_probe(dev, ret, "devm_pm_runtime_enable failed\n"); =20 ret =3D pm_runtime_resume_and_get(dev); - if (ret < 0) { - dev_err(dev, "pm_runtime_resume_and_get failed: %d\n", ret); - return ret; - } + if (ret < 0) + return dev_err_probe(dev, ret, "pm_runtime_resume_and_get failed\n"); =20 raw_spin_lock_init(&rzv2h_icu_data->lock); =20 --=20 2.52.0 From nobody Mon Feb 9 14:43:55 2026 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B119324B33 for ; Tue, 3 Feb 2026 23:18:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770160715; cv=none; b=YNKKC2vKLsIt0rxtE4ydUdCozDetf9517x7RShPG+IrW0RJxCtPNEBSPehkr5Id+Y9T8+IdhXYj8sdrNTfbpON6bMNY6Arzu1HkqmRrOil6lu8cDpktVe2jLk6dwht4QqQdhrosRvrtWJuCmq51ZmC9wTrg84OkCpTI62WyeiCo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770160715; c=relaxed/simple; bh=M74STgH1ns3cnMiq1Iga99YIhx0rQEIYF7y5xQ9Bxsk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=AAsfopM/JHoEwKP66ji6S/c508itTiDgXFzm61vH4t9Z0Ke3CaijCMJCqD20ptukeRyl+Tehx+xWFXiDLmCRUBwWt7qmFDHbKn+Y1vXmnUobccchNXMxs7r1ky2cQ6VdTv1Pg9vCLmOAa2z80QA5dm+mwQUEttdbmiyz1y6UpQ4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=jOTgVOak; arc=none smtp.client-ip=209.85.221.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="jOTgVOak" Received: by mail-wr1-f54.google.com with SMTP id ffacd0b85a97d-42fb4eeb482so4230520f8f.0 for ; Tue, 03 Feb 2026 15:18:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770160712; x=1770765512; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+qamj1ZCcGSJBUDcRzNR59i6EIMleinLWFPtTQZPwfs=; b=jOTgVOakGHhYWNs+4rZRq/uTJXWm6tbH0roPC9o8LXZdmsohKQ3S3qN8ZEvRh+x8o8 kHNGeruCGUTKn0eJ6/MfS/kHcS3kPSOu8UmaGU+DPthB68+IyXCDHnBCzmZHv6CICIot deJPyGWQBsTZ9l8SWBjDrXbUzJxdpp2EMovCMqr5eKvnwbwZkb6mHzZIlj4PRXAg5iNc JXrv67b0yhaE2srCppwi6PMpbBIcl8XTW/CaGNMdG++z4OZtwc3nh9SNKOPqZ5CMEhOj DKmzbhwX0QqFpd38OW6GFGYxbVuc0Dk8iKhnLu/Llx7CzViviP95u75aPn5DKO2X9wjj UTUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770160712; x=1770765512; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=+qamj1ZCcGSJBUDcRzNR59i6EIMleinLWFPtTQZPwfs=; b=ZDENbzuauhfl0LNZNpGBaJNTnXfiWQIhf7h00N5OKZCmDCwev06oYcuVZm33pIFION 2ncWk4SE9F6P7SniCPWo6yjniIpsjHOEEFOvTij0A7Yq67XzR4gH9lOqQonZ/gcj2qfz DlXlbAj2fZ3dVCGii7xP63nQCtIE7TzwZ1peRLqhqv3tV6o4CR7PeVhuphJuBUHu3KhZ 06cLcNRDMbv6LbDnmXz4Q8/JvhEfdXCEZeiIrtO1OFXKXnCgEeDtaq7Yrb/MQ3mXagOY IvKGuLK8ZEw1H2nyWNskHkv57OSeODAd5XjoEl4QcnEMStdEB0P9GS2S08lAQBrEY6qk 43UQ== X-Gm-Message-State: AOJu0YyPX8dc6P0yH4DOPhzV4otqYm22RFQRCkhg1GsqgXs84BaOLkO9 YT/NpK310GoHM7mdDW15aggw15mJWNi53FWMHOwMpAPlCmZ/KEyVY/8O X-Gm-Gg: AZuq6aJAWypwc5C5Yiu7ti34ABfJRE1ws5TJaIJTJEXHvm5ZbjE2GB387uPNxWteQCA uRZq8QmvjEAhqMjyXUuYy5ZOLEjDGIsC+o30nLZvwH6xxqXTOG1wghrNSCWT8Aehp/SUHYriheJ b/tf5Z3ikqvclUE1JNCiKL8UhVeDj0rprRmD5WZ+rr7fLSK5y7XuTdNhmJIWgPGuTE53Qw0fAlT sAivYRDDdDv+qf42JT4HWBfQa8rmhJMjJ8A6SSfY7B92yLh76SwgnS0GsBBbfNdP0AmFz+S61d1 VRKYnUSs6XBTIP52rbeuxHb0W3a5KHf5PK3nw43/k1ei3BNLrXzF4WC0ombjGJE9QXolBrGYn7j 0rgGaG6hullyfCHghl60rgTZ5coImOmceQ8u05ZLqPitQAikP/8t0LKlDpXOtDpFzQWDeAcTRyl A9NeZnX574D9WkOv/iYuE9a5SBryQkDBwXiOzeHl6NVIjZrD7CEB0X8Aj/Gz9WE91qSLG6pIpJv kQte6Xet66rTJhMF2q7Tv2E X-Received: by 2002:a05:6000:40c9:b0:435:a8e7:62de with SMTP id ffacd0b85a97d-436180628f8mr1401844f8f.58.1770160711522; Tue, 03 Feb 2026 15:18:31 -0800 (PST) Received: from iku.Home ([2a06:5906:61b:2d00:2e50:5c7f:afca:5f9f]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-436180647aasm1739832f8f.41.2026.02.03.15.18.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Feb 2026 15:18:30 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Thomas Gleixner , Philipp Zabel , Geert Uytterhoeven , Magnus Damm Cc: linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 4/6] irqchip/renesas-rzv2h: Make IRQ type handling range-aware Date: Tue, 3 Feb 2026 23:18:21 +0000 Message-ID: <20260203231823.208661-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260203231823.208661-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260203231823.208661-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Refine IRQ type handling to explicitly bound IRQ and TINT ranges and dispatch based on the hardware IRQ number. This restructures the logic to clearly separate NMI, IRQ, and TINT handling and ensures out-of-range interrupts are ignored safely. The change prepares the driver for adding CA55 interrupts into the IRQ hierarchy domain by making the interrupt classification explicit and extensible. Signed-off-by: Lad Prabhakar --- v1->v2: - New patch. --- drivers/irqchip/irq-renesas-rzv2h.c | 59 +++++++++++++++++++---------- 1 file changed, 40 insertions(+), 19 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-rene= sas-rzv2h.c index 4aa772ba1a1f..6c7bbb04c6e4 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -25,9 +25,11 @@ /* DT "interrupts" indexes */ #define ICU_IRQ_START 1 #define ICU_IRQ_COUNT 16 -#define ICU_TINT_START (ICU_IRQ_START + ICU_IRQ_COUNT) +#define ICU_IRQ_LAST (ICU_IRQ_START + ICU_IRQ_COUNT - 1) +#define ICU_TINT_START (ICU_IRQ_LAST + 1) #define ICU_TINT_COUNT 32 -#define ICU_NUM_IRQ (ICU_TINT_START + ICU_TINT_COUNT) +#define ICU_TINT_LAST (ICU_TINT_START + ICU_TINT_COUNT - 1) +#define ICU_NUM_IRQ (ICU_TINT_LAST + 1) =20 /* Registers */ #define ICU_NSCNT 0x00 @@ -175,18 +177,27 @@ static void rzv2h_icu_eoi(struct irq_data *d) u32 bit; =20 scoped_guard(raw_spinlock, &priv->lock) { - if (hw_irq >=3D ICU_TINT_START) { - tintirq_nr =3D hw_irq - ICU_TINT_START; - bit =3D BIT(tintirq_nr); - if (!irqd_is_level_type(d)) - writel_relaxed(bit, priv->base + priv->info->t_offs + ICU_TSCLR); - } else if (hw_irq >=3D ICU_IRQ_START) { + switch (hw_irq) { + case 0: + /* Clear NMI */ + writel_relaxed(ICU_NSCLR_NCLR, priv->base + ICU_NSCLR); + break; + case ICU_IRQ_START ... ICU_IRQ_LAST: + /* Clear IRQ */ tintirq_nr =3D hw_irq - ICU_IRQ_START; bit =3D BIT(tintirq_nr); if (!irqd_is_level_type(d)) writel_relaxed(bit, priv->base + ICU_ISCLR); - } else { - writel_relaxed(ICU_NSCLR_NCLR, priv->base + ICU_NSCLR); + break; + case ICU_TINT_START ... ICU_TINT_LAST: + /* Clear TINT */ + tintirq_nr =3D hw_irq - ICU_TINT_START; + bit =3D BIT(tintirq_nr); + if (!irqd_is_level_type(d)) + writel_relaxed(bit, priv->base + priv->info->t_offs + ICU_TSCLR); + break; + default: + break; } } =20 @@ -200,7 +211,7 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d= , bool enable) u32 tint_nr, tssel_n, k, tssr; u8 nr_tint; =20 - if (hw_irq < ICU_TINT_START) + if (hw_irq < ICU_TINT_START || hw_irq > ICU_TINT_LAST) return; =20 tint_nr =3D hw_irq - ICU_TINT_START; @@ -421,12 +432,22 @@ static int rzv2h_icu_set_type(struct irq_data *d, uns= igned int type) unsigned int hw_irq =3D irqd_to_hwirq(d); int ret; =20 - if (hw_irq >=3D ICU_TINT_START) - ret =3D rzv2h_tint_set_type(d, type); - else if (hw_irq >=3D ICU_IRQ_START) - ret =3D rzv2h_irq_set_type(d, type); - else + switch (hw_irq) { + case 0: + /* NMI */ ret =3D rzv2h_nmi_set_type(d, type); + break; + case ICU_IRQ_START ... ICU_IRQ_LAST: + /* IRQ */ + ret =3D rzv2h_irq_set_type(d, type); + break; + case ICU_TINT_START ... ICU_TINT_LAST: + /* TINT */ + ret =3D rzv2h_tint_set_type(d, type); + break; + default: + ret =3D -EINVAL; + } =20 if (ret) return ret; @@ -507,11 +528,11 @@ static int rzv2h_icu_alloc(struct irq_domain *domain,= unsigned int virq, unsigne * fwspec->param[0]. * hwirq is embedded in bits 0-15. * TINT is embedded in bits 16-31. + * Check if bits 16-31 are set to identify TINT interrupts. */ - if (hwirq >=3D ICU_TINT_START) { - tint =3D ICU_TINT_EXTRACT_GPIOINT(hwirq); + tint =3D ICU_TINT_EXTRACT_GPIOINT(hwirq); + if (tint) { hwirq =3D ICU_TINT_EXTRACT_HWIRQ(hwirq); - if (hwirq < ICU_TINT_START) return -EINVAL; } --=20 2.52.0 From nobody Mon Feb 9 14:43:55 2026 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F94A329C7D for ; Tue, 3 Feb 2026 23:18:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770160716; cv=none; b=BM9vmMVPaNIVsu3OhrHWp0ytO6JjOZ3E0iH423VC7nM9++N6iY33LhWw05l2Z7if+PRawiTCyxz0s1DmhYliOSdqllZ5KesR27JuyLJkGL7elD2sZmgqojGf6wlo9MrzXVEHaIAL91/gZb7AAczh72N+1CDi0PEAb4WZep3rm+Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770160716; c=relaxed/simple; bh=1uF0wBkSjxeFSATeAkszaNl/BxV9vt5+gPDNPaKaTo4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LcJrJEVbBcHhzI+woOxeSmo1xbxTgYLwcINmWlL5UfWkePFqkVeR1WrtdWGc5ide+nx37/WtcCpU5xRRFYrl41z23TUI2lVgJCQ1h7KfLA96wDJ8/LiWly/kLP6RT6nkfJc+4qPWNDo13BJHjhEk+LjD4/TtbxEblET0xuR+/K8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=e0xf5gJN; arc=none smtp.client-ip=209.85.221.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="e0xf5gJN" Received: by mail-wr1-f45.google.com with SMTP id ffacd0b85a97d-42fbbc3df8fso4799342f8f.2 for ; Tue, 03 Feb 2026 15:18:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770160713; x=1770765513; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/5hoJf68rQR7rnJWTnRUztO/z8AoqWtSofT0jabEpYg=; b=e0xf5gJNMBstCMedophYAmeF0kK3f8X2jc7Vk0360QTfAZd6VU5jgSa3FMbcRTy+IZ RK4ugBnEaYK0h5BdElAF/tt9bo2ltVZclFyKs1c4uayc0YgagVsnmnokbf30M9BiyKrB 45aR/sBye9IYxkPjCuxAx8drht3SGfQK+dpv1O98t4WhAJzHSrpqla8EfLALokRMa1k/ JPFvCyFd8487+qw7UadK1AuR7sjPElwntlniNCKXSpC2LY6LDPepnOi+Ph/CY8ENV/7s KiD/ozDNkl82oIQXRQao/Wu2l99kPHwBrnR0JF6v/BpuIHMLb6JUeGQPwBK3CrKQyNaG U9sQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770160713; x=1770765513; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=/5hoJf68rQR7rnJWTnRUztO/z8AoqWtSofT0jabEpYg=; b=KwC8SIORR+u6kQVT/6TSZBgLlfXvAYsWb8knRmIbGoLE2Rc32vrJ7QjvBC+mhyRXBI BvZP998PUCpq9HWldnGN/KAsa2Nlma90HWW2vN1cQl+JtMhCAlaVQrNkKZplXtRDkmWY VSHDf/C5sks9Ki/vpjngOvmLAuFPSZcdmu8nVaCW8HLXkp8atculBSgAVu7vowLxA8Tf A08MXCKzoEYo1J6YPpCqPEibs/HVHsqvm5I9s0OlizrmnG0f80pBUvkLwTR3nITV2udB aIBv7B0kLUBhEOQxlKQA/A6601PfBSYZKygIXwCTuzi5Sd2BmIgVuclFFgeFctvte7up LbMA== X-Gm-Message-State: AOJu0YzF7qJ43ocn2+r+8eAXPgqvZFpaDW6QII1zQGPj6hVPopyjVL/p WO/t2lS3pw/x6JNoiH2w4GLFbq+f3HYvf7Rd9/pOK93px2CAgUoiXQR0 X-Gm-Gg: AZuq6aJAqQyIxOM/6xB9Vej3nWRb6yFbgkh5VhRXZCnx3nw3WMbZGGNOT2rMctaXvX8 m2smuWXcQrbyEX82QTYF/MY1BuLfPUumD92KC47z9ox+DuS2oCV7h/oEuGf1SkZTyqBXttpzMhg TiBAlqYW/QflqCKzkbazVHz8xRj6rQX+8nBh8z1m33bOP488nqHfgS+VrQUOsZ8lZPDhmyOovDh VKOJKPPh42aLSxmDxm9MjFi79JDSEf8zCn3goXFn5rdNTd2O7O3i1SuBmwrvN3UGHqjiSrtjAak Ohf+95R/wSfiUcxqk+cudsKD1OWs069VJXVjrAjEY2W8q7Qz9vXy/5CRpOJcYFLUYhFB1seG2tH YbEtzdnVe9xDuM6sMBmtoUe1vW9Z9oYNvNpqjqoJ2BhNAz+VnPI0sbtRY2HUlqaqCxpK0KgD/vY +CBJ4uTKWDl54plGoheO8Mugk3TFs4h/0lR9KZprmCCdCg4AYwtHkNmNwdm7s4Dh39YNrS0tdx5 mxAudN7/t7KnWvI4Iol1jr2 X-Received: by 2002:a05:6000:2387:b0:435:9522:2bc9 with SMTP id ffacd0b85a97d-43617e398c0mr1519895f8f.5.1770160712641; Tue, 03 Feb 2026 15:18:32 -0800 (PST) Received: from iku.Home ([2a06:5906:61b:2d00:2e50:5c7f:afca:5f9f]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-436180647aasm1739832f8f.41.2026.02.03.15.18.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Feb 2026 15:18:31 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Thomas Gleixner , Philipp Zabel , Geert Uytterhoeven , Magnus Damm Cc: linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 5/6] irqchip/renesas-rzv2h: Add CA55 software interrupt support Date: Tue, 3 Feb 2026 23:18:22 +0000 Message-ID: <20260203231823.208661-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260203231823.208661-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260203231823.208661-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar The Renesas RZ/V2H ICU provides a software interrupt register (ICU_SWINT) that allows software to explicitly assert interrupts toward individual CA55 cores. Writing BIT(n) to ICU_SWINT triggers the corresponding interrupt. Extend the RZ/V2H ICU IRQ domain to include CA55 software interrupts as part of the hierarchical IRQ numbering, backed by the ICU_SWINT register. SW interrupts can now be triggered when GENERIC_IRQ_INJECTION is enabled. Signed-off-by: Lad Prabhakar --- v1->v2: - Made CA55 SW interrupt as part of ICU IRQ domain. - Implemented rzv2h_icu_irq_set_irqchip_state() to trigger SWINT. - Updated commit message accordingly. --- drivers/irqchip/irq-renesas-rzv2h.c | 89 ++++++++++++++++++++++++++++- 1 file changed, 86 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-rene= sas-rzv2h.c index 6c7bbb04c6e4..a2ff7524889c 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -29,7 +30,10 @@ #define ICU_TINT_START (ICU_IRQ_LAST + 1) #define ICU_TINT_COUNT 32 #define ICU_TINT_LAST (ICU_TINT_START + ICU_TINT_COUNT - 1) -#define ICU_NUM_IRQ (ICU_TINT_LAST + 1) +#define ICU_CA55_INT_START (ICU_TINT_LAST + 1) +#define ICU_CA55_INT_COUNT 4 +#define ICU_CA55_INT_LAST (ICU_CA55_INT_START + ICU_= CA55_INT_COUNT - 1) +#define ICU_NUM_IRQ (ICU_CA55_INT_LAST + 1) =20 /* Registers */ #define ICU_NSCNT 0x00 @@ -42,6 +46,7 @@ #define ICU_TSCLR 0x24 #define ICU_TITSR(k) (0x28 + (k) * 4) #define ICU_TSSR(k) (0x30 + (k) * 4) +#define ICU_SWINT 0x130 #define ICU_DMkSELy(k, y) (0x420 + (k) * 0x20 + (y) * 4) #define ICU_DMACKSELk(k) (0x500 + (k) * 4) =20 @@ -248,6 +253,30 @@ static void rzv2h_icu_irq_enable(struct irq_data *d) irq_chip_enable_parent(d); } =20 +static int rzv2h_icu_irq_set_irqchip_state(struct irq_data *d, + enum irqchip_irq_state which, + bool state) +{ + unsigned int hwirq =3D irqd_to_hwirq(d); + struct rzv2h_icu_priv *priv; + unsigned int bit; + + if (hwirq < ICU_CA55_INT_START || hwirq > ICU_CA55_INT_LAST || + which !=3D IRQCHIP_STATE_PENDING) + return irq_chip_set_parent_state(d, which, state); + + if (!state) + return 0; + + priv =3D irq_data_to_priv(d); + bit =3D BIT(hwirq - ICU_CA55_INT_START); + + guard(raw_spinlock)(&priv->lock); + /* Trigger the software interrupt */ + writel_relaxed(bit, priv->base + ICU_SWINT); + return 0; +} + static int rzv2h_nmi_set_type(struct irq_data *d, unsigned int type) { struct rzv2h_icu_priv *priv =3D irq_data_to_priv(d); @@ -429,6 +458,7 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsi= gned int type) =20 static int rzv2h_icu_set_type(struct irq_data *d, unsigned int type) { + unsigned int gic_type =3D IRQ_TYPE_LEVEL_HIGH; unsigned int hw_irq =3D irqd_to_hwirq(d); int ret; =20 @@ -445,6 +475,11 @@ static int rzv2h_icu_set_type(struct irq_data *d, unsi= gned int type) /* TINT */ ret =3D rzv2h_tint_set_type(d, type); break; + case ICU_CA55_INT_START ... ICU_CA55_INT_LAST: + /* CA55 Software Interrupts have EDGE_RISING type */ + gic_type =3D IRQ_TYPE_EDGE_RISING; + ret =3D 0; + break; default: ret =3D -EINVAL; } @@ -452,7 +487,7 @@ static int rzv2h_icu_set_type(struct irq_data *d, unsig= ned int type) if (ret) return ret; =20 - return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); + return irq_chip_set_type_parent(d, gic_type); } =20 static int rzv2h_irqc_irq_suspend(void *data) @@ -501,7 +536,7 @@ static const struct irq_chip rzv2h_icu_chip =3D { .irq_disable =3D rzv2h_icu_irq_disable, .irq_enable =3D rzv2h_icu_irq_enable, .irq_get_irqchip_state =3D irq_chip_get_parent_state, - .irq_set_irqchip_state =3D irq_chip_set_parent_state, + .irq_set_irqchip_state =3D rzv2h_icu_irq_set_irqchip_state, .irq_retrigger =3D irq_chip_retrigger_hierarchy, .irq_set_type =3D rzv2h_icu_set_type, .irq_set_affinity =3D irq_chip_set_affinity_parent, @@ -571,6 +606,50 @@ static int rzv2h_icu_parse_interrupts(struct rzv2h_icu= _priv *priv, struct device return 0; } =20 +static irqreturn_t rzv2h_icu_swint_irq(int irq, void *data) +{ + u8 cpu =3D *(u8 *)data; + + pr_debug("SWINT interrupt for CA55 core %u\n", cpu); + return IRQ_HANDLED; +} + +static int rzv2h_icu_setup_irqs(struct platform_device *pdev, + struct irq_domain *irq_domain) +{ + bool irq_inject =3D IS_ENABLED(CONFIG_GENERIC_IRQ_INJECTION); + static const char * const rzv2h_swint_names[] =3D { + "int-ca55-0", "int-ca55-1", + "int-ca55-2", "int-ca55-3", + }; + static const u8 swint_idx[] =3D { 0, 1, 2, 3 }; + struct device *dev =3D &pdev->dev; + struct irq_fwspec fwspec; + unsigned int virq; + unsigned int i; + int ret; + + for (i =3D 0; i < ICU_CA55_INT_COUNT && irq_inject; i++) { + fwspec.fwnode =3D irq_domain->fwnode; + fwspec.param_count =3D 2; + fwspec.param[0] =3D ICU_CA55_INT_START + i; + fwspec.param[1] =3D IRQ_TYPE_EDGE_RISING; + + virq =3D irq_create_fwspec_mapping(&fwspec); + if (!virq) + return dev_err_probe(dev, -EINVAL, "failed to create IRQ mapping for %s= \n", + rzv2h_swint_names[i]); + + ret =3D devm_request_irq(dev, virq, rzv2h_icu_swint_irq, 0, dev_name(dev= ), + (void *)&swint_idx[i]); + if (ret) + return dev_err_probe(dev, ret, "Failed to request %s IRQ\n", + rzv2h_swint_names[i]); + } + + return 0; +} + static int rzv2h_icu_probe_common(struct platform_device *pdev, struct dev= ice_node *parent, const struct rzv2h_hw_info *hw_info) { @@ -626,6 +705,10 @@ static int rzv2h_icu_probe_common(struct platform_devi= ce *pdev, struct device_no =20 register_syscore(&rzv2h_irqc_syscore); =20 + ret =3D rzv2h_icu_setup_irqs(pdev, irq_domain); + if (ret) + goto pm_put; + /* * coccicheck complains about a missing put_device call before returning,= but it's a false * positive. We still need dev after successfully returning from this fun= ction. --=20 2.52.0 From nobody Mon Feb 9 14:43:56 2026 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6BC936405E for ; Tue, 3 Feb 2026 23:18:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770160717; cv=none; b=gRLicP4RS3KRYbKv/uoQhMviFVASLB/NqtKrQklB4cCW9qg5X7qyAPrGnscPgbXy5VRJjHXOroyY9iZS7Cc08H+TMCl6wNfFYUWHRfN1zT1MVgKtKk3IFD1S2s2ifIIKL32RzQ2OBWWIwLXCK9QuuI5E4/LwGaU649Qxii8xFAU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770160717; c=relaxed/simple; bh=+8PL5Ixzxv6q40l8iUL9vZ9LOzsZmNxHJKAkQAAjwYU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Kxq2lOB6KMYisJsQPyR1l2WQOxaqB0P3av9JzuRJ4wZqQsRLhYrzgOYpcxzmdrr18O6vWSgrK9mU+aTORek6qQbuJyaHOPlflAqWz3CfprYQdNjpY7O6CLy/X+GsZ3+TVYGLf6YFezsEVykkeyHD5v3ah3r1nXjaciWCrYaGKzc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=O3/Kco8Q; arc=none smtp.client-ip=209.85.128.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="O3/Kco8Q" Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-4806f9e61f9so31998355e9.1 for ; Tue, 03 Feb 2026 15:18:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770160714; x=1770765514; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BShUaX58BJSoQ+jnQUrTyp17jL8XdIs4C5TLsuymRCo=; b=O3/Kco8QilzA5fua2h1tbqVnNgW03m/PjJ+ompr+xAAqPBDRkdp6GIKJfEE+JRqIl4 lCbbR7B1Oup2CSXHRs9NDJM2S9A1l9Y0azuy/ncTKHXoKSfrT5uuLSw99J3r53rZhyvs xJPmw+0ci9vjk9z5T0lzFcU1gwd3H3RnmmnB7MDCpnfMY93kVGDR0EVQF4fDegitw8Iy ngfLDzKdkVY/GhMWmHhB9wiYw/qrzBDnxyAQtX0/MalQnmllU6Y53IU/GCuTXN4QPxFg LpSsIBnuN844C4Mqt5PWuqbq2l2nJ8Xw5bAZkQOR09OuAa7GccZ5e0Q3kgRJHHmr9MpX m1Dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770160714; x=1770765514; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=BShUaX58BJSoQ+jnQUrTyp17jL8XdIs4C5TLsuymRCo=; b=CcG0+/5P9whMlTMalzVtQgeQ2693Pzj/MKV6rbSK6FpB2Grz1OsifGc9GZt56psbVz Z1pNABIJsjPYxpY5BVS4qABRJ0R1IzYc824l1nD4mXPA8MvgrvF8DM5nol6hk2PjpbCQ /5xP5HJal7DFcTy1h06F/Cuz+DCRk100HntvZqzOm/zFYrGYX9L0yZ8AOABsLTdQJSWa GavgeTg5qxN7c6oMovMb9dlRYRIOjxq6VxH0RNPjZ9X2jADOpix6kVxP1I2slroutV/6 3fgWNgnn+njmE2hOWj1RB+hsC6jke3T9SL8g32EceZ/GgMdn7Jx6fbAPVABP4pN2pgdX 9/RQ== X-Gm-Message-State: AOJu0YzuB5TFw+7tdUM+aC1hVia5g4iO4l3I/mAdFZmpQzyzI5bOwkGB qu8WIpVxuypf4QFPKpuOQjtPofW3Btx6HucHXI6TwUCrhknsxp/CnUUU X-Gm-Gg: AZuq6aKinMBmjr9CLMxkMbWsT6aCoFe7GyvU4vsPuadPc8sQcWUWsri4fBOxbGTQiCD +tgpf09hQuM5nTyHfg3Bs0eO99zqed4xr1BtoCo1CG8dITo6WvbXC5itnoaphjHbcr3rwZkw99R 2HTA3eMxCsQdooV0mOGXvXwunAvWNBj5c/Z2DuBm4sPuynmqMU2dtMDxpVDQek2Xr/kwfU7juzB wBXvqIFyckjGNKRJn2TT/oOktX2RBDUCsGec9Nbhc54KmhJlL2eZ3H7yxspMO0SViiOJlstsIaw tymkXIB/58hC5kMqEbS/1IuBCtqccsyaMe7+jC4Xf0wqtYFJb2nr7aBygZNY2/EpMsVqhw36usG 7fvRxUIEbIGH/TAJYbq1cRdRpkJN3YJaXXQriTcR20ahQ3sgkpmLCjmKkM6w+YR7EqoECD6B83i 0DYeWj+Dh9/amvarvl8ZcIvuk9vMD/Nc3/QJhIPAkRAfQpZAasdY84m0uBot0TtWHQe/Mokw+mP 2VSXjn19LrdqHiE2thsoJOv X-Received: by 2002:a05:600c:1c1e:b0:47a:7fd0:9eea with SMTP id 5b1f17b1804b1-4830e92a706mr17809735e9.3.1770160713792; Tue, 03 Feb 2026 15:18:33 -0800 (PST) Received: from iku.Home ([2a06:5906:61b:2d00:2e50:5c7f:afca:5f9f]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-436180647aasm1739832f8f.41.2026.02.03.15.18.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Feb 2026 15:18:32 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Thomas Gleixner , Philipp Zabel , Geert Uytterhoeven , Magnus Damm Cc: linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 6/6] irqchip/renesas-rzv2h: Handle ICU error IRQ and add SWPE trigger Date: Tue, 3 Feb 2026 23:18:23 +0000 Message-ID: <20260203231823.208661-7-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260203231823.208661-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260203231823.208661-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Handle the RZ/V2H ICU error interrupt to help diagnose latched bus, ECC RAM, and CA55/IP error conditions. Extend the hardware IRQ numbering to include a single error interrupt line and route IRQCHIP_STATE_PENDING requests to hardware-triggered error injection via ICU_SWPE. Account for SoC differences in ECC RAM error register coverage so the handler only iterates over valid ECC status/clear banks, and route the RZ/V2N compatible to a probe path with the correct ECC range while keeping the existing RZ/V2H and RZ/G3E handling. Signed-off-by: Lad Prabhakar --- v1->v2: - Made Error interrupt as part of ICU IRQ domain. - Updated rzv2h_icu_irq_set_irqchip_state() to trigger pseudo interrupt. - Updated commit message accordingly. --- drivers/irqchip/irq-renesas-rzv2h.c | 149 ++++++++++++++++++++++++++-- 1 file changed, 143 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-rene= sas-rzv2h.c index a2ff7524889c..3937a857af8b 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -33,7 +33,10 @@ #define ICU_CA55_INT_START (ICU_TINT_LAST + 1) #define ICU_CA55_INT_COUNT 4 #define ICU_CA55_INT_LAST (ICU_CA55_INT_START + ICU_= CA55_INT_COUNT - 1) -#define ICU_NUM_IRQ (ICU_CA55_INT_LAST + 1) +#define ICU_ERR_INT_START (ICU_CA55_INT_LAST + 1) +#define ICU_ERR_INT_COUNT 1 +#define ICU_ERR_INT_LAST (ICU_ERR_INT_START + ICU_ER= R_INT_COUNT - 1) +#define ICU_NUM_IRQ (ICU_ERR_INT_LAST + 1) =20 /* Registers */ #define ICU_NSCNT 0x00 @@ -46,7 +49,15 @@ #define ICU_TSCLR 0x24 #define ICU_TITSR(k) (0x28 + (k) * 4) #define ICU_TSSR(k) (0x30 + (k) * 4) +#define ICU_BEISR(k) (0x70 + (k) * 4) +#define ICU_BECLR(k) (0x80 + (k) * 4) +#define ICU_EREISR(k) (0x90 + (k) * 4) +#define ICU_ERCLR(k) (0xE0 + (k) * 4) #define ICU_SWINT 0x130 +#define ICU_ERINTA55CTL(k) (0x338 + (k) * 4) +#define ICU_ERINTA55CRL(k) (0x348 + (k) * 4) +#define ICU_ERINTA55MSK(k) (0x358 + (k) * 4) +#define ICU_SWPE 0x370 #define ICU_DMkSELy(k, y) (0x420 + (k) * 0x20 + (y) * 4) #define ICU_DMACKSELk(k) (0x500 + (k) * 4) =20 @@ -97,6 +108,10 @@ #define ICU_RZG3E_TSSEL_MAX_VAL 0x8c #define ICU_RZV2H_TSSEL_MAX_VAL 0x55 =20 +#define ICU_SWPE_NUM 16 +#define ICU_NUM_BE 4 +#define ICU_NUM_A55ERR 4 + /** * struct rzv2h_irqc_reg_cache - registers cache (necessary for suspend/re= sume) * @nitsr: ICU_NITSR register @@ -115,12 +130,16 @@ struct rzv2h_irqc_reg_cache { * @t_offs: TINT offset * @max_tssel: TSSEL max value * @field_width: TSSR field width + * @ecc_start: Start index of ECC RAM interrupts + * @ecc_end: End index of ECC RAM interrupts */ struct rzv2h_hw_info { const u8 *tssel_lut; u16 t_offs; u8 max_tssel; u8 field_width; + u8 ecc_start; + u8 ecc_end; }; =20 /* DMAC */ @@ -259,10 +278,10 @@ static int rzv2h_icu_irq_set_irqchip_state(struct irq= _data *d, { unsigned int hwirq =3D irqd_to_hwirq(d); struct rzv2h_icu_priv *priv; + void __iomem *offset; unsigned int bit; =20 - if (hwirq < ICU_CA55_INT_START || hwirq > ICU_CA55_INT_LAST || - which !=3D IRQCHIP_STATE_PENDING) + if (which !=3D IRQCHIP_STATE_PENDING) return irq_chip_set_parent_state(d, which, state); =20 if (!state) @@ -271,9 +290,33 @@ static int rzv2h_icu_irq_set_irqchip_state(struct irq_= data *d, priv =3D irq_data_to_priv(d); bit =3D BIT(hwirq - ICU_CA55_INT_START); =20 + switch (hwirq) { + case ICU_CA55_INT_START ... ICU_CA55_INT_LAST: + bit =3D BIT(hwirq - ICU_CA55_INT_START); + offset =3D priv->base + ICU_SWINT; + break; + case ICU_ERR_INT_START ... ICU_ERR_INT_LAST: { + static u8 swpe; + + bit =3D BIT(swpe); + /* + * SWPE has 16 bits; the bit position is rotated on each trigger + * and wraps around once all bits have been used. + */ + if (++swpe >=3D ICU_SWPE_NUM) + swpe =3D 0; + + offset =3D priv->base + ICU_SWPE; + break; + } + default: + return irq_chip_set_parent_state(d, which, state); + } + guard(raw_spinlock)(&priv->lock); - /* Trigger the software interrupt */ - writel_relaxed(bit, priv->base + ICU_SWINT); + /* Trigger the error/software interrupt */ + writel_relaxed(bit, offset); + return 0; } =20 @@ -480,6 +523,10 @@ static int rzv2h_icu_set_type(struct irq_data *d, unsi= gned int type) gic_type =3D IRQ_TYPE_EDGE_RISING; ret =3D 0; break; + case ICU_ERR_INT_START ... ICU_ERR_INT_LAST: + /* Error Interrupts */ + ret =3D 0; + break; default: ret =3D -EINVAL; } @@ -606,6 +653,48 @@ static int rzv2h_icu_parse_interrupts(struct rzv2h_icu= _priv *priv, struct device return 0; } =20 +static irqreturn_t rzv2h_icu_error_irq(int irq, void *data) +{ + struct rzv2h_icu_priv *priv =3D data; + const struct rzv2h_hw_info *hw_info =3D priv->info; + void __iomem *base =3D priv->base; + unsigned int k; + u32 st; + + /* 1) Bus errors (BEISR0..3) */ + for (k =3D 0; k < ICU_NUM_BE; k++) { + st =3D readl(base + ICU_BEISR(k)); + if (!st) + continue; + + writel_relaxed(st, base + ICU_BECLR(k)); + pr_debug("rzv2h-icu: BUS error k=3D%u status=3D0x%08x\n", k, st); + } + + /* 2) ECC RAM errors (EREISR0..X) */ + for (k =3D hw_info->ecc_start; k <=3D hw_info->ecc_end; k++) { + st =3D readl(base + ICU_EREISR(k)); + if (!st) + continue; + + writel_relaxed(st, base + ICU_ERCLR(k)); + pr_debug("rzv2h-icu: ECC error k=3D%u status=3D0x%08x\n", k, st); + } + + /* 3) IP/CA55 error interrupt status (ERINTA55CTL0..3) */ + for (k =3D 0; k < ICU_NUM_A55ERR; k++) { + st =3D readl(base + ICU_ERINTA55CTL(k)); + if (!st) + continue; + + /* there is no relation with status bits so clear all the interrupts */ + writel_relaxed(0xffffffff, base + ICU_ERINTA55CRL(k)); + pr_debug("rzv2h-icu: IP/CA55 error k=3D%u status=3D0x%08x\n", k, st); + } + + return IRQ_HANDLED; +} + static irqreturn_t rzv2h_icu_swint_irq(int irq, void *data) { u8 cpu =3D *(u8 *)data; @@ -617,12 +706,15 @@ static irqreturn_t rzv2h_icu_swint_irq(int irq, void = *data) static int rzv2h_icu_setup_irqs(struct platform_device *pdev, struct irq_domain *irq_domain) { + const struct rzv2h_hw_info *hw_info =3D rzv2h_icu_data->info; bool irq_inject =3D IS_ENABLED(CONFIG_GENERIC_IRQ_INJECTION); static const char * const rzv2h_swint_names[] =3D { "int-ca55-0", "int-ca55-1", "int-ca55-2", "int-ca55-3", }; + static const char *icu_err =3D "icu-error-ca55"; static const u8 swint_idx[] =3D { 0, 1, 2, 3 }; + void __iomem *base =3D rzv2h_icu_data->base; struct device *dev =3D &pdev->dev; struct irq_fwspec fwspec; unsigned int virq; @@ -647,6 +739,34 @@ static int rzv2h_icu_setup_irqs(struct platform_device= *pdev, rzv2h_swint_names[i]); } =20 + /* Unmask and clear all IP/CA55 error interrupts */ + for (i =3D 0; i < ICU_NUM_A55ERR; i++) { + writel_relaxed(0xffffff, base + ICU_ERINTA55CRL(i)); + writel_relaxed(0x0, base + ICU_ERINTA55MSK(i)); + } + + /* Clear all Bus errors */ + for (i =3D 0; i < ICU_NUM_BE; i++) + writel_relaxed(0xffffffff, base + ICU_BECLR(i)); + + /* Clear all ECCRAM errors */ + for (i =3D hw_info->ecc_start; i <=3D hw_info->ecc_end; i++) + writel_relaxed(0xffffffff, base + ICU_ERCLR(i)); + + fwspec.fwnode =3D irq_domain->fwnode; + fwspec.param_count =3D 2; + fwspec.param[0] =3D ICU_ERR_INT_START; + fwspec.param[1] =3D IRQ_TYPE_LEVEL_HIGH; + + virq =3D irq_create_fwspec_mapping(&fwspec); + if (!virq) + return dev_err_probe(dev, -EINVAL, "failed to create IRQ mapping for %s\= n", + icu_err); + + ret =3D devm_request_irq(dev, virq, rzv2h_icu_error_irq, 0, dev_name(dev)= , rzv2h_icu_data); + if (ret) + return dev_err_probe(dev, ret, "Failed to request %s IRQ\n", icu_err); + return 0; } =20 @@ -752,12 +872,24 @@ static const struct rzv2h_hw_info rzg3e_hw_params =3D= { .t_offs =3D ICU_RZG3E_TINT_OFFSET, .max_tssel =3D ICU_RZG3E_TSSEL_MAX_VAL, .field_width =3D 16, + .ecc_start =3D 1, + .ecc_end =3D 4, +}; + +static const struct rzv2h_hw_info rzv2n_hw_params =3D { + .t_offs =3D 0, + .max_tssel =3D ICU_RZV2H_TSSEL_MAX_VAL, + .field_width =3D 8, + .ecc_start =3D 0, + .ecc_end =3D 2, }; =20 static const struct rzv2h_hw_info rzv2h_hw_params =3D { .t_offs =3D 0, .max_tssel =3D ICU_RZV2H_TSSEL_MAX_VAL, .field_width =3D 8, + .ecc_start =3D 0, + .ecc_end =3D 11, }; =20 static int rzg3e_icu_probe(struct platform_device *pdev, struct device_nod= e *parent) @@ -765,6 +897,11 @@ static int rzg3e_icu_probe(struct platform_device *pde= v, struct device_node *par return rzv2h_icu_probe_common(pdev, parent, &rzg3e_hw_params); } =20 +static int rzv2n_icu_probe(struct platform_device *pdev, struct device_nod= e *parent) +{ + return rzv2h_icu_probe_common(pdev, parent, &rzv2n_hw_params); +} + static int rzv2h_icu_probe(struct platform_device *pdev, struct device_nod= e *parent) { return rzv2h_icu_probe_common(pdev, parent, &rzv2h_hw_params); @@ -772,7 +909,7 @@ static int rzv2h_icu_probe(struct platform_device *pdev= , struct device_node *par =20 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzv2h_icu) IRQCHIP_MATCH("renesas,r9a09g047-icu", rzg3e_icu_probe) -IRQCHIP_MATCH("renesas,r9a09g056-icu", rzv2h_icu_probe) +IRQCHIP_MATCH("renesas,r9a09g056-icu", rzv2n_icu_probe) IRQCHIP_MATCH("renesas,r9a09g057-icu", rzv2h_icu_probe) IRQCHIP_PLATFORM_DRIVER_END(rzv2h_icu) MODULE_AUTHOR("Fabrizio Castro "); --=20 2.52.0