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charset="utf-8" The SEV-SNP IBPB-on-Entry feature does not require a guest-side implementation. The feature was added in Zen5 h/w, after the first SNP Zen implementation, and thus was not accounted for when the initial set of SNP features were added to the kernel. In its abundant precaution, commit 8c29f0165405 ("x86/sev: Add SEV-SNP guest feature negotiation support") included SEV_STATUS' IBPB-on-Entry bit as a reserved bit, thereby masking guests from using the feature. Allow guests to make use of IBPB-on-Entry when supported by the hypervisor, as the bit is now architecturally defined and safe to expose. Fixes: 8c29f0165405 ("x86/sev: Add SEV-SNP guest feature negotiation suppor= t") Reviewed-by: Nikunj A Dadhania Reviewed-by: Tom Lendacky Cc: Borislav Petkov (AMD) Cc: Michael Roth Cc: stable@kernel.org Signed-off-by: Kim Phillips --- v2: - Change title (Nikunj) - Add reviews-by (Nikunj, Tom) - Change the description to more generally explain what the patch does (Bo= ris) v1: https://lore.kernel.org/kvm/20260126224205.1442196-2-kim.phillips@amd.c= om/ arch/x86/boot/compressed/sev.c | 1 + arch/x86/coco/sev/core.c | 1 + arch/x86/include/asm/msr-index.h | 5 ++++- 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c index c8c1464b3a56..2b639703b8dd 100644 --- a/arch/x86/boot/compressed/sev.c +++ b/arch/x86/boot/compressed/sev.c @@ -188,6 +188,7 @@ bool sev_es_check_ghcb_fault(unsigned long address) MSR_AMD64_SNP_RESERVED_BIT13 | \ MSR_AMD64_SNP_RESERVED_BIT15 | \ MSR_AMD64_SNP_SECURE_AVIC | \ + MSR_AMD64_SNP_RESERVED_BITS19_22 | \ MSR_AMD64_SNP_RESERVED_MASK) =20 #ifdef CONFIG_AMD_SECURE_AVIC diff --git a/arch/x86/coco/sev/core.c b/arch/x86/coco/sev/core.c index 9ae3b11754e6..13f608117411 100644 --- a/arch/x86/coco/sev/core.c +++ b/arch/x86/coco/sev/core.c @@ -122,6 +122,7 @@ static const char * const sev_status_feat_names[] =3D { [MSR_AMD64_SNP_VMSA_REG_PROT_BIT] =3D "VMSARegProt", [MSR_AMD64_SNP_SMT_PROT_BIT] =3D "SMTProt", [MSR_AMD64_SNP_SECURE_AVIC_BIT] =3D "SecureAVIC", + [MSR_AMD64_SNP_IBPB_ON_ENTRY_BIT] =3D "IBPBOnEntry", }; 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Tue, 3 Feb 2026 16:24:39 -0600 From: Kim Phillips To: , , , CC: Sean Christopherson , Paolo Bonzini , K Prateek Nayak , "Nikunj A Dadhania" , Tom Lendacky , "Michael Roth" , Borislav Petkov , Borislav Petkov , Naveen Rao , David Kaplan , Kim Phillips Subject: [PATCH v2 2/3] KVM: SEV: Add support for IBPB-on-Entry Date: Tue, 3 Feb 2026 16:24:04 -0600 Message-ID: <20260203222405.4065706-3-kim.phillips@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260203222405.4065706-1-kim.phillips@amd.com> References: <20260203222405.4065706-1-kim.phillips@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003442:EE_|BL4PR12MB9533:EE_ X-MS-Office365-Filtering-Correlation-Id: 14969d09-187c-4944-3a26-08de637305e9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026|13003099007; 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charset="utf-8" AMD EPYC 5th generation and above processors support IBPB-on-Entry for SNP guests. By invoking an Indirect Branch Prediction Barrier (IBPB) on VMRUN, old indirect branch predictions are prevented from influencing indirect branches within the guest. SNP guests may choose to enable IBPB-on-Entry by setting SEV_FEATURES bit 21 (IbpbOnEntry). Host support for IBPB on Entry is indicated by CPUID Fn8000_001F[IbpbOnEntry], bit 31. If supported, indicate support for IBPB on Entry in sev_supported_vmsa_features bit 23 (IbpbOnEntry). For more info, refer to page 615, Section 15.36.17 "Side-Channel Protection", AMD64 Architecture Programmer's Manual Volume 2: System Programming Part 2, Pub. 24593 Rev. 3.42 - March 2024 (see Link). Link: https://bugzilla.kernel.org/attachment.cgi?id=3D306250 Signed-off-by: Kim Phillips Reviewed-by: Tom Lendacky --- v2: Added Tom's Reviewed-by. v1: https://lore.kernel.org/kvm/20260126224205.1442196-3-kim.phillips@amd.c= om/ arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/svm.h | 1 + arch/x86/kvm/svm/sev.c | 9 ++++++++- 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index c01fdde465de..3ce5dff36f78 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -459,6 +459,7 @@ #define X86_FEATURE_ALLOWED_SEV_FEATURES (19*32+27) /* Allowed SEV Feature= s */ #define X86_FEATURE_SVSM (19*32+28) /* "svsm" SVSM present */ #define X86_FEATURE_HV_INUSE_WR_ALLOWED (19*32+30) /* Allow Write to in-us= e hypervisor-owned pages */ +#define X86_FEATURE_IBPB_ON_ENTRY (19*32+31) /* SEV-SNP IBPB on VM Entry */ =20 /* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word = 20 */ #define X86_FEATURE_NO_NESTED_DATA_BP (20*32+ 0) /* No Nested Data Breakpo= ints */ diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index edde36097ddc..eebc65ec948f 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -306,6 +306,7 @@ static_assert((X2AVIC_4K_MAX_PHYSICAL_ID & AVIC_PHYSICA= L_MAX_INDEX_MASK) =3D=3D X2AV #define SVM_SEV_FEAT_ALTERNATE_INJECTION BIT(4) #define SVM_SEV_FEAT_DEBUG_SWAP BIT(5) #define SVM_SEV_FEAT_SECURE_TSC BIT(9) +#define SVM_SEV_FEAT_IBPB_ON_ENTRY BIT(21) =20 #define VMCB_ALLOWED_SEV_FEATURES_VALID BIT_ULL(63) =20 diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index ea515cf41168..8a6d25db0c00 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -3165,8 +3165,15 @@ void __init sev_hardware_setup(void) cpu_feature_enabled(X86_FEATURE_NO_NESTED_DATA_BP)) sev_supported_vmsa_features |=3D SVM_SEV_FEAT_DEBUG_SWAP; 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charset="utf-8" Rename SNP_FEATURES_PRESENT->SNP_FEATURES_IMPL to denote its counterpart relationship with SNP_FEATURES_IMPL_REQ. Fixes: 8c29f0165405 ("x86/sev: Add SEV-SNP guest feature negotiation suppor= t") Suggested-by: Borislav Petkov (AMD) Suggested-by: Tom Lendacky Cc: Nikunj A Dadhania Cc: Michael Roth Cc: stable@kernel.org Signed-off-by: Kim Phillips --- v2: new this series arch/x86/boot/compressed/sev.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c index 2b639703b8dd..aca5313d193c 100644 --- a/arch/x86/boot/compressed/sev.c +++ b/arch/x86/boot/compressed/sev.c @@ -198,11 +198,11 @@ bool sev_es_check_ghcb_fault(unsigned long address) #endif =20 /* - * SNP_FEATURES_PRESENT is the mask of SNP features that are implemented + * SNP_FEATURES_IMPL is the mask of SNP features that are implemented * by the guest kernel. As and when a new feature is implemented in the * guest kernel, a corresponding bit should be added to the mask. */ -#define SNP_FEATURES_PRESENT (MSR_AMD64_SNP_DEBUG_SWAP | \ +#define SNP_FEATURES_IMPL (MSR_AMD64_SNP_DEBUG_SWAP | \ MSR_AMD64_SNP_SECURE_TSC | \ SNP_FEATURE_SECURE_AVIC) =20 @@ -211,7 +211,7 @@ u64 snp_get_unsupported_features(u64 status) if (!(status & MSR_AMD64_SEV_SNP_ENABLED)) return 0; =20 - return status & SNP_FEATURES_IMPL_REQ & ~SNP_FEATURES_PRESENT; + return status & SNP_FEATURES_IMPL_REQ & ~SNP_FEATURES_IMPL; } =20 void snp_check_features(void) --=20 2.43.0