From nobody Mon Feb 9 16:01:00 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id CBEA036A037; Tue, 3 Feb 2026 21:44:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770155088; cv=none; b=MaErFq0t3SerZrwpfRmHHSdbfTf3ZfXpLmmdTtPIe8q8mVHwPEKCegQ9udxhYGQhWE1dgQg9LC+7vGKJ9Grvh8mJZT7I7VHPumebwPtgP4fdm9oXMp/FMrLTYXrzeUAFGb2OmT8sIey1F/UsjjXXsEQA3TXgcIhrbCVd0ym8JeU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770155088; c=relaxed/simple; bh=R87NELJ0Lv3IiHyRGWOY1E+88UP1rj1MjNwUume4E6g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FIGXOkJ83UCjmxd8TA1HX6Qhn5ZNpCOjHgAInTsD+H8raLHyDkaE+NjQjJRJGZnUgFz8JBulsqmyrgXYQr++2gMts6l283ppLyrBH6gbryHCstXZdDA+2+yuTRMFeE2i8lMpQWG/j9OJN9Au6qfFJpEavJ6+yTixN0HqEYveEE8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0FB44339; Tue, 3 Feb 2026 13:44:40 -0800 (PST) Received: from e134344.cambridge.arm.com (e134344.arm.com [10.1.196.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id DC5963F778; Tue, 3 Feb 2026 13:44:40 -0800 (PST) From: Ben Horgan To: ben.horgan@arm.com Cc: amitsinght@marvell.com, baisheng.gao@unisoc.com, baolin.wang@linux.alibaba.com, carl@os.amperecomputing.com, dave.martin@arm.com, david@kernel.org, dfustini@baylibre.com, fenghuay@nvidia.com, gshan@redhat.com, james.morse@arm.com, jonathan.cameron@huawei.com, kobak@nvidia.com, lcherian@marvell.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, peternewman@google.com, punit.agrawal@oss.qualcomm.com, quic_jiles@quicinc.com, reinette.chatre@intel.com, rohit.mathew@arm.com, scott@os.amperecomputing.com, sdonthineni@nvidia.com, tan.shaopeng@fujitsu.com, xhao@linux.alibaba.com, catalin.marinas@arm.com, will@kernel.org, corbet@lwn.net, maz@kernel.org, oupton@kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com, kvmarm@lists.linux.dev, zengheng4@huawei.com, linux-doc@vger.kernel.org, Shaopeng Tan Subject: [PATCH v4 08/41] arm64: mpam: Add cpu_pm notifier to restore MPAM sysregs Date: Tue, 3 Feb 2026 21:43:09 +0000 Message-ID: <20260203214342.584712-9-ben.horgan@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260203214342.584712-1-ben.horgan@arm.com> References: <20260203214342.584712-1-ben.horgan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: James Morse The MPAM system registers will be lost if the CPU is reset during PSCI's CPU_SUSPEND. Add a PM notifier to restore them. mpam_thread_switch(current) can't be used as this won't make any changes if the in-memory copy says the register already has the correct value. In reality the system register is UNKNOWN out of reset. Tested-by: Gavin Shan Tested-by: Shaopeng Tan Tested-by: Peter Newman Reviewed-by: Jonathan Cameron Reviewed-by: Gavin Shan Signed-off-by: James Morse Signed-off-by: Ben Horgan Reviewed-by: Catalin Marinas --- Changes since v3: Always set MPAM1_EL1.MPAMEN rather than relying on it being read only Bail out early if mpam not supported (Gavin) --- arch/arm64/kernel/mpam.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/kernel/mpam.c b/arch/arm64/kernel/mpam.c index e6feff2324ac..48ec0ffd5999 100644 --- a/arch/arm64/kernel/mpam.c +++ b/arch/arm64/kernel/mpam.c @@ -4,6 +4,7 @@ #include =20 #include +#include #include #include =20 @@ -13,12 +14,44 @@ DEFINE_PER_CPU(u64, arm64_mpam_current); =20 u64 arm64_mpam_global_default; =20 +static int mpam_pm_notifier(struct notifier_block *self, + unsigned long cmd, void *v) +{ + u64 regval; + int cpu =3D smp_processor_id(); + + switch (cmd) { + case CPU_PM_EXIT: + /* + * Don't use mpam_thread_switch() as the system register + * value has changed under our feet. + */ + regval =3D READ_ONCE(per_cpu(arm64_mpam_current, cpu)); + write_sysreg_s(regval | MPAM1_EL1_MPAMEN, SYS_MPAM1_EL1); + isb(); + + write_sysreg_s(regval, SYS_MPAM0_EL1); + + return NOTIFY_OK; + default: + return NOTIFY_DONE; + } +} + +static struct notifier_block mpam_pm_nb =3D { + .notifier_call =3D mpam_pm_notifier, +}; + static int __init arm64_mpam_register_cpus(void) { u64 mpamidr =3D read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); u16 partid_max =3D FIELD_GET(MPAMIDR_EL1_PARTID_MAX, mpamidr); u8 pmg_max =3D FIELD_GET(MPAMIDR_EL1_PMG_MAX, mpamidr); =20 + if (!system_supports_mpam()) + return 0; + + cpu_pm_register_notifier(&mpam_pm_nb); return mpam_register_requestor(partid_max, pmg_max); } /* Must occur before mpam_msc_driver_init() from subsys_initcall() */ --=20 2.43.0