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Tue, 03 Feb 2026 11:38:58 -0800 (PST) Received: from hu-uchheda-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a9338a11f1sm3368055ad.38.2026.02.03.11.38.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Feb 2026 11:38:58 -0800 (PST) From: Umang Chheda To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, richardcochran@gmail.com Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, umang.chheda@oss.qualcomm.com, mohd.anwar@oss.qualcomm.com, krishna.chundru@oss.qualcomm.com, monish.chunara@oss.qualcomm.com Subject: [PATCH v3 1/1] arm64: dts: qcom: lemans-evk: Add Mezzanine Date: Wed, 4 Feb 2026 01:08:48 +0530 Message-Id: <20260203193848.123307-2-umang.chheda@oss.qualcomm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260203193848.123307-1-umang.chheda@oss.qualcomm.com> References: <20260203193848.123307-1-umang.chheda@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: gSG39nbqqdMO1KYRV0AmSi5hekOHGbk6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjAzMDE1NiBTYWx0ZWRfX9XF8OAyp+DB+ QKJZMhlYsGlwovlgOkJ0fqtvPr9Lw+tpk8qIByosHO+4Oy8KsFsZyEXJa/oLPtvjek3Z7ZmEez1 IRkZK0bXipTb1knruECdNiqWlDxWWXUJlYAoICvrqZ4WuHH0pRSxRiv29nBu8PdgWljKa55KZW0 +knkL1uff7sw4cfEqw4TQdJRgkPzfW51//zF7f9ovc0tZAKwL3Zy5qp9ywwdPtLaWXDZZCwuc6m nXTFBAzNei/yEvT979gFrIYPqdhJXVMI4o7nl9EYClxDb3WnaVyFrAu9kPwRspRdN9m7r1IiJId VeyAXa6LOhEhaf//YdS0cLcd4L/wgZRUjqJyn81wX5gHo728S4Qhk1dDWl/5MMFCFYqnJVrCgeE cqOAYD4wrcs4rKgczolD10N5JQ7DLREUPEZjx3OqmIunUb0PjAH5uCFIeop/9boOLbPT/xr+Nw3 lhzEWZ0pOBy2HssPJsw== X-Authority-Analysis: v=2.4 cv=BKy+bVQG c=1 sm=1 tr=0 ts=69824ed3 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=jnsgzKaiXtoIhPlfe4IA:9 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-GUID: gSG39nbqqdMO1KYRV0AmSi5hekOHGbk6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-03_05,2026-02-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 adultscore=0 bulkscore=0 spamscore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 malwarescore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602030156 Content-Type: text/plain; charset="utf-8" The Mezzanine is an hardware expansion add-on board designed to be stacked on top of Lemans EVK. It has following peripherals : - 4x Type A USB ports in host mode. - TC9563 PCIe switch, which has following three downstream ports (DSP) : - 1st DSP connects M.2 E-key connector for connecting WLAN endpoints. - 2nd DSP connects M.2 B-key connector for connecting cellular modems. - 3rd DSP with support for Dual Ethernet ports. - eMMC. - Additional 2.5GbE Ethernet PHY connected to native EMAC with support for MAC Address configuration via NVMEM. - EEPROM. - LVDS Display. - 2*mini DP. Add support for following peripherals : - TC9563 PCIe Switch. - Additional 2.5GbE Ethernet Port. - EEPROM. Written with inputs from : Mohd Ayaan Anwar - Ethernet. Krishna Chaitanya Chundru - PCIe Monish Chunara - EEPROM. Signed-off-by: Umang Chheda Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/Makefile | 4 + .../boot/dts/qcom/lemans-evk-mezzanine.dtso | 301 ++++++++++++++++++ 2 files changed, 305 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/lemans-evk-mezzanine.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index f80b5d9cf1e8..79449004adfd 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -43,6 +43,10 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk-camera.dtb lemans-evk-el2-dtbs :=3D lemans-evk.dtb lemans-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk-el2.dtb + +lemans-evk-mezzanine-dtbs :=3D lemans-evk.dtb lemans-evk-mezzanine.dtbo + +dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D milos-fairphone-fp6.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D monaco-evk.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8216-samsung-fortuna3g.dtb diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-mezzanine.dtso b/arch/arm6= 4/boot/dts/qcom/lemans-evk-mezzanine.dtso new file mode 100644 index 000000000000..4fab96ba873c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-evk-mezzanine.dtso @@ -0,0 +1,301 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + model =3D "Qualcomm Technologies, Inc. Lemans-evk Mezzanine"; + + vreg_0p9: regulator-vreg-0p9 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_0P9"; + + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-always-on; + regulator-boot-on; + + vin-supply =3D <&vreg_3p3>; + }; + + vreg_1p8: regulator-vreg-1p8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_1P8"; + + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + regulator-boot-on; + + vin-supply =3D <&vreg_4p2>; + }; + + vreg_3p3: regulator-vreg-3p3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_3P3"; + + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + regulator-boot-on; + + vin-supply =3D <&vreg_4p2>; + }; + + vreg_4p2: regulator-vreg-4p2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_4P2"; + + regulator-min-microvolt =3D <4200000>; + regulator-max-microvolt =3D <4200000>; + regulator-always-on; + regulator-boot-on; + + vin-supply =3D <&vreg_sys_pwr>; + }; + + vreg_sys_pwr: regulator-vreg-sys-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_SYS_PWR"; + + regulator-min-microvolt =3D <24000000>; + regulator-max-microvolt =3D <24000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +ðernet1 { + phy-handle =3D <&hsgmii_phy1>; + phy-mode =3D "2500base-x"; + + pinctrl-0 =3D <ðernet1_default>; + pinctrl-names =3D "default"; + + snps,mtl-rx-config =3D <&mtl_rx_setup1>; + snps,mtl-tx-config =3D <&mtl_tx_setup1>; + + nvmem-cells =3D <&mac_addr1>; + nvmem-cell-names =3D "mac-address"; + + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + hsgmii_phy1: ethernet-phy@18 { + compatible =3D "ethernet-phy-id004d.d101"; + reg =3D <0x18>; + reset-gpios =3D <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <11000>; + reset-deassert-us =3D <70000>; + }; + }; + + mtl_rx_setup1: rx-queues-config { + snps,rx-queues-to-use =3D <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + snps,route-up; + snps,priority =3D <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel =3D <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel =3D <0x3>; + snps,priority =3D <0xc>; + }; + }; + + mtl_tx_setup1: tx-queues-config { + snps,tx-queues-to-use =3D <4>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope =3D <0x1000>; + snps,idle_slope =3D <0x1000>; + snps,high_credit =3D <0x3e800>; + snps,low_credit =3D <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope =3D <0x1000>; + snps,idle_slope =3D <0x1000>; + snps,high_credit =3D <0x3e800>; + snps,low_credit =3D <0xffc18000>; + }; + }; +}; + +&i2c18 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + eeprom@52 { + compatible =3D "giantec,gt24c256c", "atmel,24c256"; + reg =3D <0x52>; + pagesize =3D <64>; + + nvmem-layout { + compatible =3D "fixed-layout"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + mac_addr1: mac-addr@0 { + reg =3D <0x0 0x6>; + }; + }; + }; +}; + +&pcie0 { + iommu-map =3D <0x0 &pcie_smmu 0x0 0x1>, + <0x100 &pcie_smmu 0x1 0x1>, + <0x208 &pcie_smmu 0x2 0x1>, + <0x210 &pcie_smmu 0x3 0x1>, + <0x218 &pcie_smmu 0x4 0x1>, + <0x300 &pcie_smmu 0x5 0x1>, + <0x400 &pcie_smmu 0x6 0x1>, + <0x500 &pcie_smmu 0x7 0x1>, + <0x501 &pcie_smmu 0x8 0x1>; +}; + +&pcieport0 { + #address-cells =3D <3>; + #size-cells =3D <2>; + + pcie@0,0 { + compatible =3D "pci1179,0623"; + reg =3D <0x10000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x2 0xff>; + + vddc-supply =3D <&vreg_0p9>; + vdd18-supply =3D <&vreg_1p8>; + vdd09-supply =3D <&vreg_0p9>; + vddio1-supply =3D <&vreg_1p8>; + vddio2-supply =3D <&vreg_1p8>; + vddio18-supply =3D <&vreg_1p8>; + + i2c-parent =3D <&i2c18 0x77>; + + resx-gpios =3D <&tlmm 140 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&tc9563_resx_n>; + pinctrl-names =3D "default"; + + pcie@1,0 { + reg =3D <0x20800 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x3 0xff>; + }; + + pcie@2,0 { + reg =3D <0x21000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x4 0xff>; + }; + + pcie@3,0 { + reg =3D <0x21800 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + bus-range =3D <0x5 0xff>; + + pci@0,0 { + reg =3D <0x50000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + }; + + pci@0,1 { + reg =3D <0x50100 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + }; + }; + }; +}; + +&serdes1 { + phy-supply =3D <&vreg_l5a>; + + status =3D "okay"; +}; + +&tlmm { + ethernet1_default: ethernet1-default-state { + ethernet1-mdc-pins { + pins =3D "gpio20"; + function =3D "emac1_mdc"; + drive-strength =3D <16>; + bias-pull-up; + }; + + ethernet1-mdio-pins { + pins =3D "gpio21"; + function =3D "emac1_mdio"; + drive-strength =3D <16>; + bias-pull-up; + }; + }; + + tc9563_resx_n: tc9563-resx-state { + pins =3D "gpio140"; + function =3D "gpio"; + + bias-disable; + input-disable; + output-enable; + power-source =3D <0>; + }; +}; -- 2.34.1