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[87.205.5.123]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8e9fad97a7sm16715766b.0.2026.02.03.10.56.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Feb 2026 10:56:36 -0800 (PST) From: =?UTF-8?q?Tomasz=20Paku=C5=82a?= To: alexander.deucher@amd.com, harry.wentland@amd.com, sunpeng.li@amd.com Cc: maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, siqueira@igalia.com, dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, tomasz.pakula.oficjalny@gmail.com, bernhard.berger@gmail.com, michel.daenzer@mailbox.org, daniel@fooishbar.org, admin@ptr1337.dev Subject: [PATCH v3 05/19] drm/amd/display: Refactor PCON VRR compatibility check Date: Tue, 3 Feb 2026 19:56:12 +0100 Message-ID: <20260203185626.55428-6-tomasz.pakula.oficjalny@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260203185626.55428-1-tomasz.pakula.oficjalny@gmail.com> References: <20260203185626.55428-1-tomasz.pakula.oficjalny@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable [Why] DP->HDMI PCONs prevously entered the DP path [How] Restructure amdgpu_dm_update_freesync_caps() and move dm_get_adaptive_sync_support_type() to dm_helpers_is_vrr_pcon_allowed() to better reflect what this function does. It never actually gave us any other info. Signed-off-by: Tomasz Paku=C5=82a --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 24 +++++++----- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 39 ++++++------------- drivers/gpu/drm/amd/display/dc/dm_helpers.h | 2 +- 3 files changed, 27 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gp= u/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 284f5b326c18..9346b62d981b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -13278,7 +13278,8 @@ void amdgpu_dm_update_freesync_caps(struct drm_conn= ector *connector, struct dpcd_caps dpcd_caps =3D {0}; const struct edid *edid; bool freesync_capable =3D false; - enum adaptive_sync_type as_type =3D ADAPTIVE_SYNC_TYPE_NONE; + bool pcon_allowed =3D false; + bool is_pcon =3D false; =20 if (!connector->state) { drm_err(adev_to_drm(adev), "%s - Connector has no state", __func__); @@ -13306,18 +13307,23 @@ void amdgpu_dm_update_freesync_caps(struct drm_co= nnector *connector, if (!adev->dm.freesync_module || !dc_supports_vrr(sink->ctx->dce_version)) goto update; =20 + /* Gather all data */ edid =3D drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw() parse_amd_vsdb_cea(amdgpu_dm_connector, edid, &vsdb_info); =20 - if (amdgpu_dm_connector->dc_link) + if (amdgpu_dm_connector->dc_link) { dpcd_caps =3D amdgpu_dm_connector->dc_link->dpcd_caps; + is_pcon =3D dpcd_caps.dongle_type =3D=3D DISPLAY_DONGLE_DP_HDMI_CONVERTE= R; + pcon_allowed =3D dm_helpers_is_vrr_pcon_allowed(amdgpu_dm_connector->dc_= link); + } =20 /* Some eDP panels only have the refresh rate range info in DisplayID */ if (is_monitor_range_invalid(connector)) parse_edid_displayid_vrr(connector, edid); =20 - if (sink->sink_signal =3D=3D SIGNAL_TYPE_DISPLAY_PORT || - sink->sink_signal =3D=3D SIGNAL_TYPE_EDP) { + /* DP & eDP excluding PCONs */ + if ((sink->sink_signal =3D=3D SIGNAL_TYPE_EDP || + sink->sink_signal =3D=3D SIGNAL_TYPE_DISPLAY_PORT) && !is_pcon) { /* * Many monitors expose AMD vsdb in CAE even for DP and their * monitor ranges do not contain Range Limits Only flag @@ -13342,17 +13348,15 @@ void amdgpu_dm_update_freesync_caps(struct drm_co= nnector *connector, amdgpu_dm_connector->as_type =3D ADAPTIVE_SYNC_TYPE_EDP; } =20 + /* HDMI */ } else if (sink->sink_signal =3D=3D SIGNAL_TYPE_HDMI_TYPE_A && vsdb_info.= freesync_supported) { monitor_range_from_vsdb(&connector->display_info, &vsdb_info); freesync_capable =3D copy_range_to_amdgpu_connector(connector); - } =20 - if (amdgpu_dm_connector->dc_link) - as_type =3D dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_li= nk); - - if (as_type =3D=3D FREESYNC_TYPE_PCON_IN_WHITELIST && vsdb_info.freesync_= supported) { + /* DP -> HDMI PCON */ + } else if (pcon_allowed && vsdb_info.freesync_supported) { + amdgpu_dm_connector->as_type =3D FREESYNC_TYPE_PCON_IN_WHITELIST; amdgpu_dm_connector->pack_sdp_v1_3 =3D true; - amdgpu_dm_connector->as_type =3D as_type; amdgpu_dm_connector->vsdb_info =3D vsdb_info; =20 monitor_range_from_vsdb(&connector->display_info, &vsdb_info); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/dr= ivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 1f41d6540b83..45a91df619d9 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -1381,40 +1381,25 @@ void dm_helpers_dp_mst_update_branch_bandwidth( // TODO } =20 -static bool dm_is_freesync_pcon_whitelist(const uint32_t branch_dev_id) +bool dm_helpers_is_vrr_pcon_allowed(const struct dc_link *link) { - bool ret_val =3D false; + if (link->dpcd_caps.dongle_type !=3D DISPLAY_DONGLE_DP_HDMI_CONVERTER) + return false; =20 - switch (branch_dev_id) { + if (!link->dpcd_caps.allow_invalid_MSA_timing_param) + return false; + + if (!link->dpcd_caps.adaptive_sync_caps.dp_adap_sync_caps.bits.ADAPTIVE_S= YNC_SDP_SUPPORT) + return false; + + switch (link->dpcd_caps.branch_dev_id) { case DP_BRANCH_DEVICE_ID_0060AD: case DP_BRANCH_DEVICE_ID_00E04C: case DP_BRANCH_DEVICE_ID_90CC24: - ret_val =3D true; - break; - default: - break; + return true; } =20 - return ret_val; -} - -enum adaptive_sync_type dm_get_adaptive_sync_support_type(struct dc_link *= link) -{ - struct dpcd_caps *dpcd_caps =3D &link->dpcd_caps; - enum adaptive_sync_type as_type =3D ADAPTIVE_SYNC_TYPE_NONE; - - switch (dpcd_caps->dongle_type) { - case DISPLAY_DONGLE_DP_HDMI_CONVERTER: - if (dpcd_caps->adaptive_sync_caps.dp_adap_sync_caps.bits.ADAPTIVE_SYNC_S= DP_SUPPORT =3D=3D true && - dpcd_caps->allow_invalid_MSA_timing_param =3D=3D true && - dm_is_freesync_pcon_whitelist(dpcd_caps->branch_dev_id)) - as_type =3D FREESYNC_TYPE_PCON_IN_WHITELIST; - break; - default: - break; - } - - return as_type; + return false; } =20 bool dm_helpers_is_fullscreen(struct dc_context *ctx, struct dc_stream_sta= te *stream) diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/= amd/display/dc/dm_helpers.h index 7014b8c2c956..e51f1e489129 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h +++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h @@ -220,10 +220,10 @@ int dm_helpers_dmub_set_config_sync(struct dc_context= *ctx, const struct dc_link *link, struct set_config_cmd_payload *payload, enum set_config_status *operation_result); -enum adaptive_sync_type dm_get_adaptive_sync_support_type(struct dc_link *= link); =20 enum dc_edid_status dm_helpers_get_sbios_edid(struct dc_link *link, struct= dc_edid *edid); =20 +bool dm_helpers_is_vrr_pcon_allowed(const struct dc_link *link); bool dm_helpers_is_fullscreen(struct dc_context *ctx, struct dc_stream_sta= te *stream); bool dm_helpers_is_hdr_on(struct dc_context *ctx, struct dc_stream_state *= stream); =20 --=20 2.52.0