From nobody Sat Feb 7 04:47:32 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C77D35CBD8 for ; Tue, 3 Feb 2026 17:40:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770140426; cv=none; b=BwuPMPjzh4RRJEaCOAvQlMH8bCEwTO/oWLYQw4p0QbWfxeXgu++StgF3t+mBFuZlZ960+44sfWByI6qEeO7XXoSH/2zmVIBlOC0J740VS95Q1C7ms7hvJUaykgsZNGh5eqXo9ZiKivw7zSTn5sEtUY/04cAQp0IwKMeU6u8OKBQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770140426; c=relaxed/simple; bh=7MdL99wkkvJKCcspFZ7dHx/o5TRD0QM+Phv7EkFdsGU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uc1TosSM/PsXb4ecoSK6+lXf+DwtldkNQyzTjENSpMZrisfTEfjL6nDxY6tWllG0AOP059IvFAwvyK0lwTm3p76LQuhhEeXTw67b5opJtVMI/LPtufkrBYgyAOLxWAOB3w2DU97zbN5cHjS8WzQ9vrCtJzm0XCJ0qebRN2HIWTs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=fhJAChM4; arc=none smtp.client-ip=170.10.133.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="fhJAChM4" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1770140424; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ieWU+M1MjJPFA1lViUGn95ZPJD7pQx03GN9yV+TnYA8=; b=fhJAChM4M6Ha9/GWhLow/i9dnuZqRAdrGJ2K0dmdpqe/fNAR+0H1gGDLhcJAHL+5FTdabD OmotplhAvD+N2/L+5l2/SE6pak2VBr7CwV7SPHaE7eUJuRnJifC9yVuQVKwBqmSj3jO/Eo 7f6U6h9KpijZcVa3p7AfixGvVEHCbYo= Received: from mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-554-ItWmfpOSOAOT2dDR4kCwFw-1; Tue, 03 Feb 2026 12:40:20 -0500 X-MC-Unique: ItWmfpOSOAOT2dDR4kCwFw-1 X-Mimecast-MFC-AGG-ID: ItWmfpOSOAOT2dDR4kCwFw_1770140417 Received: from mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.4]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 5A26618002C5; Tue, 3 Feb 2026 17:40:17 +0000 (UTC) Received: from p16v.luc.cera.cz (unknown [10.45.224.28]) by mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 015C03001DBA; Tue, 3 Feb 2026 17:40:10 +0000 (UTC) From: Ivan Vecera To: netdev@vger.kernel.org Cc: Aleksandr Loktionov , Vadim Fedorenko , Alexander Lobakin , Andrew Lunn , Arkadiusz Kubalewski , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Jiri Pirko , Jonathan Lemon , Leon Romanovsky , Mark Bloch , Paolo Abeni , Prathosh Satish , Przemek Kitszel , Richard Cochran , Saeed Mahameed , Tariq Toukan , Tony Nguyen , intel-wired-lan@lists.osuosl.org, linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org Subject: [PATCH net-next v5 1/9] dpll: Allow associating dpll pin with a firmware node Date: Tue, 3 Feb 2026 18:39:54 +0100 Message-ID: <20260203174002.705176-2-ivecera@redhat.com> In-Reply-To: <20260203174002.705176-1-ivecera@redhat.com> References: <20260203174002.705176-1-ivecera@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Content-Type: text/plain; charset="utf-8" Extend the DPLL core to support associating a DPLL pin with a firmware node. This association is required to allow other subsystems (such as network drivers) to locate and request specific DPLL pins defined in the Device Tree or ACPI. * Add a .fwnode field to the struct dpll_pin * Introduce dpll_pin_fwnode_set() helper to allow the provider driver to associate a pin with a fwnode after the pin has been allocated * Introduce fwnode_dpll_pin_find() helper to allow consumers to search for a registered DPLL pin using its associated fwnode handle * Ensure the fwnode reference is properly released in dpll_pin_put() Reviewed-by: Aleksandr Loktionov Reviewed-by: Vadim Fedorenko Signed-off-by: Ivan Vecera Reviewed-by: Arkadiusz Kubalewski --- v4: * fixed fwnode_dpll_pin_find() return value description --- drivers/dpll/dpll_core.c | 49 ++++++++++++++++++++++++++++++++++++++++ drivers/dpll/dpll_core.h | 2 ++ include/linux/dpll.h | 11 +++++++++ 3 files changed, 62 insertions(+) diff --git a/drivers/dpll/dpll_core.c b/drivers/dpll/dpll_core.c index 8879a72351561..f04ed7195cadd 100644 --- a/drivers/dpll/dpll_core.c +++ b/drivers/dpll/dpll_core.c @@ -10,6 +10,7 @@ =20 #include #include +#include #include #include =20 @@ -595,12 +596,60 @@ void dpll_pin_put(struct dpll_pin *pin) xa_destroy(&pin->parent_refs); xa_destroy(&pin->ref_sync_pins); dpll_pin_prop_free(&pin->prop); + fwnode_handle_put(pin->fwnode); kfree_rcu(pin, rcu); } mutex_unlock(&dpll_lock); } EXPORT_SYMBOL_GPL(dpll_pin_put); =20 +/** + * dpll_pin_fwnode_set - set dpll pin firmware node reference + * @pin: pointer to a dpll pin + * @fwnode: firmware node handle + * + * Set firmware node handle for the given dpll pin. + */ +void dpll_pin_fwnode_set(struct dpll_pin *pin, struct fwnode_handle *fwnod= e) +{ + mutex_lock(&dpll_lock); + fwnode_handle_put(pin->fwnode); /* Drop fwnode previously set */ + pin->fwnode =3D fwnode_handle_get(fwnode); + mutex_unlock(&dpll_lock); +} +EXPORT_SYMBOL_GPL(dpll_pin_fwnode_set); + +/** + * fwnode_dpll_pin_find - find dpll pin by firmware node reference + * @fwnode: reference to firmware node + * + * Get existing object of a pin that is associated with given firmware node + * reference. + * + * Context: Acquires a lock (dpll_lock) + * Return: + * * valid dpll_pin pointer on success + * * NULL when no such pin exists + */ +struct dpll_pin *fwnode_dpll_pin_find(struct fwnode_handle *fwnode) +{ + struct dpll_pin *pin, *ret =3D NULL; + unsigned long index; + + mutex_lock(&dpll_lock); + xa_for_each(&dpll_pin_xa, index, pin) { + if (pin->fwnode =3D=3D fwnode) { + ret =3D pin; + refcount_inc(&ret->refcount); + break; + } + } + mutex_unlock(&dpll_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(fwnode_dpll_pin_find); + static int __dpll_pin_register(struct dpll_device *dpll, struct dpll_pin *pin, const struct dpll_pin_ops *ops, void *priv, void *cookie) diff --git a/drivers/dpll/dpll_core.h b/drivers/dpll/dpll_core.h index 8ce969bbeb64e..d3e17ff0ecef0 100644 --- a/drivers/dpll/dpll_core.h +++ b/drivers/dpll/dpll_core.h @@ -42,6 +42,7 @@ struct dpll_device { * @pin_idx: index of a pin given by dev driver * @clock_id: clock_id of creator * @module: module of creator + * @fwnode: optional reference to firmware node * @dpll_refs: hold referencees to dplls pin was registered with * @parent_refs: hold references to parent pins pin was registered with * @ref_sync_pins: hold references to pins for Reference SYNC feature @@ -54,6 +55,7 @@ struct dpll_pin { u32 pin_idx; u64 clock_id; struct module *module; + struct fwnode_handle *fwnode; struct xarray dpll_refs; struct xarray parent_refs; struct xarray ref_sync_pins; diff --git a/include/linux/dpll.h b/include/linux/dpll.h index c6d0248fa5273..f2e8660e90cdf 100644 --- a/include/linux/dpll.h +++ b/include/linux/dpll.h @@ -16,6 +16,7 @@ struct dpll_device; struct dpll_pin; struct dpll_pin_esync; +struct fwnode_handle; =20 struct dpll_device_ops { int (*mode_get)(const struct dpll_device *dpll, void *dpll_priv, @@ -178,6 +179,8 @@ void dpll_netdev_pin_clear(struct net_device *dev); size_t dpll_netdev_pin_handle_size(const struct net_device *dev); int dpll_netdev_add_pin_handle(struct sk_buff *msg, const struct net_device *dev); + +struct dpll_pin *fwnode_dpll_pin_find(struct fwnode_handle *fwnode); #else static inline void dpll_netdev_pin_set(struct net_device *dev, struct dpll_pin *dpll_pin) { } @@ -193,6 +196,12 @@ dpll_netdev_add_pin_handle(struct sk_buff *msg, const = struct net_device *dev) { return 0; } + +static inline struct dpll_pin * +fwnode_dpll_pin_find(struct fwnode_handle *fwnode) +{ + return NULL; +} #endif =20 struct dpll_device * @@ -218,6 +227,8 @@ void dpll_pin_unregister(struct dpll_device *dpll, stru= ct dpll_pin *pin, =20 void dpll_pin_put(struct dpll_pin *pin); =20 +void dpll_pin_fwnode_set(struct dpll_pin *pin, struct fwnode_handle *fwnod= e); + int dpll_pin_on_pin_register(struct dpll_pin *parent, struct dpll_pin *pin, const struct dpll_pin_ops *ops, void *priv); =20 --=20 2.52.0 From nobody Sat Feb 7 04:47:32 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50CA534CFCF for ; Tue, 3 Feb 2026 17:40:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Tue, 3 Feb 2026 17:40:24 +0000 (UTC) Received: from p16v.luc.cera.cz (unknown [10.45.224.28]) by mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id C296930001A7; Tue, 3 Feb 2026 17:40:17 +0000 (UTC) From: Ivan Vecera To: netdev@vger.kernel.org Cc: Aleksandr Loktionov , Alexander Lobakin , Andrew Lunn , Arkadiusz Kubalewski , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Jiri Pirko , Jonathan Lemon , Leon Romanovsky , Mark Bloch , Paolo Abeni , Prathosh Satish , Przemek Kitszel , Richard Cochran , Saeed Mahameed , Tariq Toukan , Tony Nguyen , Vadim Fedorenko , intel-wired-lan@lists.osuosl.org, linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org Subject: [PATCH net-next v5 2/9] dpll: zl3073x: Associate pin with fwnode handle Date: Tue, 3 Feb 2026 18:39:55 +0100 Message-ID: <20260203174002.705176-3-ivecera@redhat.com> In-Reply-To: <20260203174002.705176-1-ivecera@redhat.com> References: <20260203174002.705176-1-ivecera@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Content-Type: text/plain; charset="utf-8" Associate the registered DPLL pin with its firmware node by calling dpll_pin_fwnode_set(). This links the created pin object to its corresponding DT/ACPI node in the DPLL core. Consequently, this enables consumer drivers (such as network drivers) to locate and request this specific pin using the fwnode_dpll_pin_find() helper. Reviewed-by: Aleksandr Loktionov Signed-off-by: Ivan Vecera Reviewed-by: Arkadiusz Kubalewski --- drivers/dpll/zl3073x/dpll.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/dpll/zl3073x/dpll.c b/drivers/dpll/zl3073x/dpll.c index 7d8ed948b9706..9eed21088adac 100644 --- a/drivers/dpll/zl3073x/dpll.c +++ b/drivers/dpll/zl3073x/dpll.c @@ -1485,6 +1485,7 @@ zl3073x_dpll_pin_register(struct zl3073x_dpll_pin *pi= n, u32 index) rc =3D PTR_ERR(pin->dpll_pin); goto err_pin_get; } + dpll_pin_fwnode_set(pin->dpll_pin, props->fwnode); =20 if (zl3073x_dpll_is_input_pin(pin)) ops =3D &zl3073x_dpll_input_pin_ops; --=20 2.52.0 From nobody Sat Feb 7 04:47:32 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7047535D5E6 for ; Tue, 3 Feb 2026 17:40:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.129.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770140439; cv=none; b=AoGgKdRWz3lFau770nh94yOnYdUsgAT3Ky0tcRChl26uK5MPl0d1f90V/KwkNsFwyTT5twwDS+DvrP+t72sMoiAcmArT/U6iiIiX2FfwLn23+FmkKKIHptGOzZ1jhGwHO8coD0EXdk2PEOv+6tg5OYyDgFwq3zrYTXP2dgL5oWw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770140439; c=relaxed/simple; bh=Wu4TFjJn7wdJkKWvlWIf/Y9H66rs7imfLQoxr2ebYhQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YmZiP3Y98wW/ysCto9queg8Uin+uUZ7akf9bjL3NSLY4uCOgXlrFYL54F8RRsXDMK1zdDgMDBXgHbBRS10MSt8/l/cAHfujVuhHqsKpwgZ7Kh+uo+QvytrMOHyGROKhLiMrJryWf0C3Ysytbz+Jmrxgw0ggX3SX2DhfR1vZKIAo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=Aubl7g1W; arc=none smtp.client-ip=170.10.129.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="Aubl7g1W" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1770140436; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=QV89xPUnCNJIH6v1OPSMlUsAUmfkwSqBeHfnsysjb1c=; b=Aubl7g1WuoYmW/Nkat/0s5xDZh2dl7RLcAiKsNHmUJCDWDNWfMeU2jgtzKQpwKvrpRv+ZR sXvWtNtcVlT0ma7wBq24fqx3rrdHTp04uS8W+e+kZlG1Lpa3A5SD3UPmbKl2l0zt6MkKP2 /yNPZGfHe/F8EGutZbVltBdZBw4jPxo= Received: from mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-175-PoA89Cl-O22aPNebNTLJpA-1; Tue, 03 Feb 2026 12:40:33 -0500 X-MC-Unique: PoA89Cl-O22aPNebNTLJpA-1 X-Mimecast-MFC-AGG-ID: PoA89Cl-O22aPNebNTLJpA_1770140430 Received: from mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.4]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 5CE4818003FD; Tue, 3 Feb 2026 17:40:30 +0000 (UTC) Received: from p16v.luc.cera.cz (unknown [10.45.224.28]) by mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 76B2230001A7; Tue, 3 Feb 2026 17:40:24 +0000 (UTC) From: Ivan Vecera To: netdev@vger.kernel.org Cc: Petr Oros , Vadim Fedorenko , Alexander Lobakin , Andrew Lunn , Arkadiusz Kubalewski , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Jiri Pirko , Jonathan Lemon , Leon Romanovsky , Mark Bloch , Paolo Abeni , Prathosh Satish , Przemek Kitszel , Richard Cochran , Saeed Mahameed , Tariq Toukan , Tony Nguyen , intel-wired-lan@lists.osuosl.org, linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org Subject: [PATCH net-next v5 3/9] dpll: Add notifier chain for dpll events Date: Tue, 3 Feb 2026 18:39:56 +0100 Message-ID: <20260203174002.705176-4-ivecera@redhat.com> In-Reply-To: <20260203174002.705176-1-ivecera@redhat.com> References: <20260203174002.705176-1-ivecera@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Content-Type: text/plain; charset="utf-8" From: Petr Oros Currently, the DPLL subsystem reports events (creation, deletion, changes) to userspace via Netlink. However, there is no mechanism for other kernel components to be notified of these events directly. Add a raw notifier chain to the DPLL core protected by dpll_lock. This allows other kernel subsystems or drivers to register callbacks and receive notifications when DPLL devices or pins are created, deleted, or modified. Define the following: - Registration helpers: {,un}register_dpll_notifier() - Event types: DPLL_DEVICE_CREATED, DPLL_PIN_CREATED, etc. - Context structures: dpll_{device,pin}_notifier_info to pass relevant data to the listeners. The notification chain is invoked alongside the existing Netlink event generation to ensure in-kernel listeners are kept in sync with the subsystem state. Reviewed-by: Vadim Fedorenko Co-developed-by: Ivan Vecera Signed-off-by: Ivan Vecera Signed-off-by: Petr Oros Reviewed-by: Aleksandr Loktionov Reviewed-by: Arkadiusz Kubalewski --- drivers/dpll/dpll_core.c | 57 +++++++++++++++++++++++++++++++++++++ drivers/dpll/dpll_core.h | 4 +++ drivers/dpll/dpll_netlink.c | 6 ++++ include/linux/dpll.h | 29 +++++++++++++++++++ 4 files changed, 96 insertions(+) diff --git a/drivers/dpll/dpll_core.c b/drivers/dpll/dpll_core.c index f04ed7195cadd..b05fe2ba46d91 100644 --- a/drivers/dpll/dpll_core.c +++ b/drivers/dpll/dpll_core.c @@ -23,6 +23,8 @@ DEFINE_MUTEX(dpll_lock); DEFINE_XARRAY_FLAGS(dpll_device_xa, XA_FLAGS_ALLOC); DEFINE_XARRAY_FLAGS(dpll_pin_xa, XA_FLAGS_ALLOC); =20 +static RAW_NOTIFIER_HEAD(dpll_notifier_chain); + static u32 dpll_device_xa_id; static u32 dpll_pin_xa_id; =20 @@ -46,6 +48,39 @@ struct dpll_pin_registration { void *cookie; }; =20 +static int call_dpll_notifiers(unsigned long action, void *info) +{ + lockdep_assert_held(&dpll_lock); + return raw_notifier_call_chain(&dpll_notifier_chain, action, info); +} + +void dpll_device_notify(struct dpll_device *dpll, unsigned long action) +{ + struct dpll_device_notifier_info info =3D { + .dpll =3D dpll, + .id =3D dpll->id, + .idx =3D dpll->device_idx, + .clock_id =3D dpll->clock_id, + .type =3D dpll->type, + }; + + call_dpll_notifiers(action, &info); +} + +void dpll_pin_notify(struct dpll_pin *pin, unsigned long action) +{ + struct dpll_pin_notifier_info info =3D { + .pin =3D pin, + .id =3D pin->id, + .idx =3D pin->pin_idx, + .clock_id =3D pin->clock_id, + .fwnode =3D pin->fwnode, + .prop =3D &pin->prop, + }; + + call_dpll_notifiers(action, &info); +} + struct dpll_device *dpll_device_get_by_id(int id) { if (xa_get_mark(&dpll_device_xa, id, DPLL_REGISTERED)) @@ -539,6 +574,28 @@ void dpll_netdev_pin_clear(struct net_device *dev) } EXPORT_SYMBOL(dpll_netdev_pin_clear); =20 +int register_dpll_notifier(struct notifier_block *nb) +{ + int ret; + + mutex_lock(&dpll_lock); + ret =3D raw_notifier_chain_register(&dpll_notifier_chain, nb); + mutex_unlock(&dpll_lock); + return ret; +} +EXPORT_SYMBOL_GPL(register_dpll_notifier); + +int unregister_dpll_notifier(struct notifier_block *nb) +{ + int ret; + + mutex_lock(&dpll_lock); + ret =3D raw_notifier_chain_unregister(&dpll_notifier_chain, nb); + mutex_unlock(&dpll_lock); + return ret; +} +EXPORT_SYMBOL_GPL(unregister_dpll_notifier); + /** * dpll_pin_get - find existing or create new dpll pin * @clock_id: clock_id of creator diff --git a/drivers/dpll/dpll_core.h b/drivers/dpll/dpll_core.h index d3e17ff0ecef0..b7b4bb251f739 100644 --- a/drivers/dpll/dpll_core.h +++ b/drivers/dpll/dpll_core.h @@ -91,4 +91,8 @@ struct dpll_pin_ref *dpll_xa_ref_dpll_first(struct xarray= *xa_refs); extern struct xarray dpll_device_xa; extern struct xarray dpll_pin_xa; extern struct mutex dpll_lock; + +void dpll_device_notify(struct dpll_device *dpll, unsigned long action); +void dpll_pin_notify(struct dpll_pin *pin, unsigned long action); + #endif diff --git a/drivers/dpll/dpll_netlink.c b/drivers/dpll/dpll_netlink.c index 904199ddd1781..83cbd64abf5a4 100644 --- a/drivers/dpll/dpll_netlink.c +++ b/drivers/dpll/dpll_netlink.c @@ -761,17 +761,20 @@ dpll_device_event_send(enum dpll_cmd event, struct dp= ll_device *dpll) =20 int dpll_device_create_ntf(struct dpll_device *dpll) { + dpll_device_notify(dpll, DPLL_DEVICE_CREATED); return dpll_device_event_send(DPLL_CMD_DEVICE_CREATE_NTF, dpll); } =20 int dpll_device_delete_ntf(struct dpll_device *dpll) { + dpll_device_notify(dpll, DPLL_DEVICE_DELETED); return dpll_device_event_send(DPLL_CMD_DEVICE_DELETE_NTF, dpll); } =20 static int __dpll_device_change_ntf(struct dpll_device *dpll) { + dpll_device_notify(dpll, DPLL_DEVICE_CHANGED); return dpll_device_event_send(DPLL_CMD_DEVICE_CHANGE_NTF, dpll); } =20 @@ -829,16 +832,19 @@ dpll_pin_event_send(enum dpll_cmd event, struct dpll_= pin *pin) =20 int dpll_pin_create_ntf(struct dpll_pin *pin) { + dpll_pin_notify(pin, DPLL_PIN_CREATED); return dpll_pin_event_send(DPLL_CMD_PIN_CREATE_NTF, pin); } =20 int dpll_pin_delete_ntf(struct dpll_pin *pin) { + dpll_pin_notify(pin, DPLL_PIN_DELETED); return dpll_pin_event_send(DPLL_CMD_PIN_DELETE_NTF, pin); } =20 int __dpll_pin_change_ntf(struct dpll_pin *pin) { + dpll_pin_notify(pin, DPLL_PIN_CHANGED); return dpll_pin_event_send(DPLL_CMD_PIN_CHANGE_NTF, pin); } =20 diff --git a/include/linux/dpll.h b/include/linux/dpll.h index f2e8660e90cdf..8ed90dfc65f05 100644 --- a/include/linux/dpll.h +++ b/include/linux/dpll.h @@ -11,6 +11,7 @@ #include #include #include +#include #include =20 struct dpll_device; @@ -172,6 +173,30 @@ struct dpll_pin_properties { u32 phase_gran; }; =20 +#define DPLL_DEVICE_CREATED 1 +#define DPLL_DEVICE_DELETED 2 +#define DPLL_DEVICE_CHANGED 3 +#define DPLL_PIN_CREATED 4 +#define DPLL_PIN_DELETED 5 +#define DPLL_PIN_CHANGED 6 + +struct dpll_device_notifier_info { + struct dpll_device *dpll; + u32 id; + u32 idx; + u64 clock_id; + enum dpll_type type; +}; + +struct dpll_pin_notifier_info { + struct dpll_pin *pin; + u32 id; + u32 idx; + u64 clock_id; + const struct fwnode_handle *fwnode; + const struct dpll_pin_properties *prop; +}; + #if IS_ENABLED(CONFIG_DPLL) void dpll_netdev_pin_set(struct net_device *dev, struct dpll_pin *dpll_pin= ); void dpll_netdev_pin_clear(struct net_device *dev); @@ -242,4 +267,8 @@ int dpll_device_change_ntf(struct dpll_device *dpll); =20 int dpll_pin_change_ntf(struct dpll_pin *pin); =20 +int register_dpll_notifier(struct notifier_block *nb); + +int unregister_dpll_notifier(struct notifier_block *nb); + #endif --=20 2.52.0 From nobody Sat Feb 7 04:47:32 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7269A3469E7 for ; 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Tue, 03 Feb 2026 12:40:40 -0500 X-MC-Unique: BNtItwj8P-il7I9leF_O1A-1 X-Mimecast-MFC-AGG-ID: BNtItwj8P-il7I9leF_O1A_1770140437 Received: from mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.4]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 17F361956048; Tue, 3 Feb 2026 17:40:37 +0000 (UTC) Received: from p16v.luc.cera.cz (unknown [10.45.224.28]) by mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id C47B73001DBA; Tue, 3 Feb 2026 17:40:30 +0000 (UTC) From: Ivan Vecera To: netdev@vger.kernel.org Cc: Aleksandr Loktionov , Alexander Lobakin , Andrew Lunn , Arkadiusz Kubalewski , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Jiri Pirko , Jonathan Lemon , Leon Romanovsky , Mark Bloch , Paolo Abeni , Prathosh Satish , Przemek Kitszel , Richard Cochran , Saeed Mahameed , Tariq Toukan , Tony Nguyen , Vadim Fedorenko , intel-wired-lan@lists.osuosl.org, linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org Subject: [PATCH net-next v5 4/9] dpll: Support dynamic pin index allocation Date: Tue, 3 Feb 2026 18:39:57 +0100 Message-ID: <20260203174002.705176-5-ivecera@redhat.com> In-Reply-To: <20260203174002.705176-1-ivecera@redhat.com> References: <20260203174002.705176-1-ivecera@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Content-Type: text/plain; charset="utf-8" Allow drivers to register DPLL pins without manually specifying a pin index. Currently, drivers must provide a unique pin index when calling dpll_pin_get(). This works well for hardware-mapped pins but creates friction for drivers handling virtual pins or those without a strict hardware indexing scheme. Introduce DPLL_PIN_IDX_UNSPEC (U32_MAX). When a driver passes this value as the pin index: 1. The core allocates a unique index using an IDA 2. The allocated index is mapped to a range starting above `INT_MAX` This separation ensures that dynamically allocated indices never collide with standard driver-provided hardware indices, which are assumed to be within the `0` to `INT_MAX` range. The index is automatically freed when the pin is released in dpll_pin_put(). Reviewed-by: Aleksandr Loktionov Signed-off-by: Ivan Vecera Reviewed-by: Arkadiusz Kubalewski --- v2: * fixed integer overflow in dpll_pin_idx_free() --- drivers/dpll/dpll_core.c | 48 ++++++++++++++++++++++++++++++++++++++-- include/linux/dpll.h | 2 ++ 2 files changed, 48 insertions(+), 2 deletions(-) diff --git a/drivers/dpll/dpll_core.c b/drivers/dpll/dpll_core.c index b05fe2ba46d91..59081cf2c73ae 100644 --- a/drivers/dpll/dpll_core.c +++ b/drivers/dpll/dpll_core.c @@ -10,6 +10,7 @@ =20 #include #include +#include #include #include #include @@ -24,6 +25,7 @@ DEFINE_XARRAY_FLAGS(dpll_device_xa, XA_FLAGS_ALLOC); DEFINE_XARRAY_FLAGS(dpll_pin_xa, XA_FLAGS_ALLOC); =20 static RAW_NOTIFIER_HEAD(dpll_notifier_chain); +static DEFINE_IDA(dpll_pin_idx_ida); =20 static u32 dpll_device_xa_id; static u32 dpll_pin_xa_id; @@ -464,6 +466,36 @@ void dpll_device_unregister(struct dpll_device *dpll, } EXPORT_SYMBOL_GPL(dpll_device_unregister); =20 +static int dpll_pin_idx_alloc(u32 *pin_idx) +{ + int ret; + + if (!pin_idx) + return -EINVAL; + + /* Alloc unique number from IDA. Number belongs to <0, INT_MAX> range */ + ret =3D ida_alloc(&dpll_pin_idx_ida, GFP_KERNEL); + if (ret < 0) + return ret; + + /* Map the value to dynamic pin index range */ + *pin_idx =3D (u32)ret + INT_MAX + 1; + + return 0; +} + +static void dpll_pin_idx_free(u32 pin_idx) +{ + if (pin_idx <=3D INT_MAX) + return; /* Not a dynamic pin index */ + + /* Map the index value from dynamic pin index range to IDA range and + * free it. + */ + pin_idx -=3D (u32)INT_MAX + 1; + ida_free(&dpll_pin_idx_ida, pin_idx); +} + static void dpll_pin_prop_free(struct dpll_pin_properties *prop) { kfree(prop->package_label); @@ -521,9 +553,18 @@ dpll_pin_alloc(u64 clock_id, u32 pin_idx, struct modul= e *module, struct dpll_pin *pin; int ret; =20 + if (pin_idx =3D=3D DPLL_PIN_IDX_UNSPEC) { + ret =3D dpll_pin_idx_alloc(&pin_idx); + if (ret) + return ERR_PTR(ret); + } else if (pin_idx > INT_MAX) { + return ERR_PTR(-EINVAL); + } pin =3D kzalloc(sizeof(*pin), GFP_KERNEL); - if (!pin) - return ERR_PTR(-ENOMEM); + if (!pin) { + ret =3D -ENOMEM; + goto err_pin_alloc; + } pin->pin_idx =3D pin_idx; pin->clock_id =3D clock_id; pin->module =3D module; @@ -551,6 +592,8 @@ dpll_pin_alloc(u64 clock_id, u32 pin_idx, struct module= *module, dpll_pin_prop_free(&pin->prop); err_pin_prop: kfree(pin); +err_pin_alloc: + dpll_pin_idx_free(pin_idx); return ERR_PTR(ret); } =20 @@ -654,6 +697,7 @@ void dpll_pin_put(struct dpll_pin *pin) xa_destroy(&pin->ref_sync_pins); dpll_pin_prop_free(&pin->prop); fwnode_handle_put(pin->fwnode); + dpll_pin_idx_free(pin->pin_idx); kfree_rcu(pin, rcu); } mutex_unlock(&dpll_lock); diff --git a/include/linux/dpll.h b/include/linux/dpll.h index 8ed90dfc65f05..8fff048131f1d 100644 --- a/include/linux/dpll.h +++ b/include/linux/dpll.h @@ -240,6 +240,8 @@ int dpll_device_register(struct dpll_device *dpll, enum= dpll_type type, void dpll_device_unregister(struct dpll_device *dpll, const struct dpll_device_ops *ops, void *priv); =20 +#define DPLL_PIN_IDX_UNSPEC U32_MAX + struct dpll_pin * dpll_pin_get(u64 clock_id, u32 dev_driver_id, struct module *module, const struct dpll_pin_properties *prop); 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Tue, 03 Feb 2026 12:40:46 -0500 X-MC-Unique: 9U3qrlHUM5qeUpQnKAN7Cg-1 X-Mimecast-MFC-AGG-ID: 9U3qrlHUM5qeUpQnKAN7Cg_1770140443 Received: from mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.4]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 5144B19560A1; Tue, 3 Feb 2026 17:40:43 +0000 (UTC) Received: from p16v.luc.cera.cz (unknown [10.45.224.28]) by mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 6A61C30001A7; Tue, 3 Feb 2026 17:40:37 +0000 (UTC) From: Ivan Vecera To: netdev@vger.kernel.org Cc: Aleksandr Loktionov , Alexander Lobakin , Andrew Lunn , Arkadiusz Kubalewski , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Jiri Pirko , Jonathan Lemon , Leon Romanovsky , Mark Bloch , Paolo Abeni , Prathosh Satish , Przemek Kitszel , Richard Cochran , Saeed Mahameed , Tariq Toukan , Tony Nguyen , Vadim Fedorenko , intel-wired-lan@lists.osuosl.org, linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org Subject: [PATCH net-next v5 5/9] dpll: zl3073x: Add support for mux pin type Date: Tue, 3 Feb 2026 18:39:58 +0100 Message-ID: <20260203174002.705176-6-ivecera@redhat.com> In-Reply-To: <20260203174002.705176-1-ivecera@redhat.com> References: <20260203174002.705176-1-ivecera@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Content-Type: text/plain; charset="utf-8" Add parsing for the "mux" string in the 'connection-type' pin property mapping it to DPLL_PIN_TYPE_MUX. Recognizing this type in the driver allows these pins to be taken as parent pins for pin-on-pin pins coming from different modules (e.g. network drivers). Reviewed-by: Aleksandr Loktionov Signed-off-by: Ivan Vecera Reviewed-by: Arkadiusz Kubalewski --- drivers/dpll/zl3073x/prop.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/dpll/zl3073x/prop.c b/drivers/dpll/zl3073x/prop.c index 4ed153087570b..ad1f099cbe2b5 100644 --- a/drivers/dpll/zl3073x/prop.c +++ b/drivers/dpll/zl3073x/prop.c @@ -249,6 +249,8 @@ struct zl3073x_pin_props *zl3073x_pin_props_get(struct = zl3073x_dev *zldev, props->dpll_props.type =3D DPLL_PIN_TYPE_INT_OSCILLATOR; else if (!strcmp(type, "synce")) props->dpll_props.type =3D DPLL_PIN_TYPE_SYNCE_ETH_PORT; + else if (!strcmp(type, "mux")) + props->dpll_props.type =3D DPLL_PIN_TYPE_MUX; else dev_warn(zldev->dev, "Unknown or unsupported pin type '%s'\n", --=20 2.52.0 From nobody Sat Feb 7 04:47:32 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CCFA320A00 for ; Tue, 3 Feb 2026 17:40:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770140459; cv=none; b=JwUjoDt/vX1Ruk20EgflellF4uJqqq5TcHKUWU1hyp9Oem76tOvNcZlh+V4LLwX0zbLEDan7CShTN2jRNQIxyZb3QeRrrYpqvTQT+xb9bs4ubs5Q/D1rxRNJNvO7JQ5uzkhMf8M2Ou9r+kz43XiPY8RJdoPJdQ2lqKWsauLpqZ8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770140459; c=relaxed/simple; bh=ZP5l4GDeIZpW7jo9sPH/jCJXfAYiA6ygHOot/kAn208=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=btM7nYGqmem02xaBPYYTO7homntX1FFWVV3NVYz5Wlwwic3bj68iSEcLE/QMcCzip6Lgj2xPvcEWkp/kl3Vm3kw8BX9beXM8mwMF4L6fqOzT05gSiW+dQ0GxL5A0t+JXZPz5M7x18ggzJLrdkaA04+h+ntcDMph+gcj72sSkr7c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=R2rU8ZXI; arc=none smtp.client-ip=170.10.133.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="R2rU8ZXI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1770140457; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=fqgpupl6TZ1uKajdvBDXaOANTcHHnIuThaEdhuGBKDs=; b=R2rU8ZXIwr/XwfAoiEu8gl+DAEP7A0ocUMCB/zJNkKej/4gA/DIRV5Fr/9LNalxp5Zqy03 fvSEpIHEfhwuaG+kiDDI+n0t5w9ByljaNi+TNvhOzJ1xBwLH50pUTu9+j0157VgG35VpTX 61w0pGqW4suTUv2zkJsQVPTgLVQ8+PA= Received: from mx-prod-mc-03.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-342-6oSPkHo3NKm_AugAQxNWtA-1; Tue, 03 Feb 2026 12:40:53 -0500 X-MC-Unique: 6oSPkHo3NKm_AugAQxNWtA-1 X-Mimecast-MFC-AGG-ID: 6oSPkHo3NKm_AugAQxNWtA_1770140450 Received: from mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.4]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id B76B11956063; Tue, 3 Feb 2026 17:40:49 +0000 (UTC) Received: from p16v.luc.cera.cz (unknown [10.45.224.28]) by mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id B99D530001A7; Tue, 3 Feb 2026 17:40:43 +0000 (UTC) From: Ivan Vecera To: netdev@vger.kernel.org Cc: Aleksandr Loktionov , Alexander Lobakin , Andrew Lunn , Arkadiusz Kubalewski , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Jiri Pirko , Jonathan Lemon , Leon Romanovsky , Mark Bloch , Paolo Abeni , Prathosh Satish , Przemek Kitszel , Richard Cochran , Saeed Mahameed , Tariq Toukan , Tony Nguyen , Vadim Fedorenko , intel-wired-lan@lists.osuosl.org, linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org Subject: [PATCH net-next v5 6/9] dpll: Enhance and consolidate reference counting logic Date: Tue, 3 Feb 2026 18:39:59 +0100 Message-ID: <20260203174002.705176-7-ivecera@redhat.com> In-Reply-To: <20260203174002.705176-1-ivecera@redhat.com> References: <20260203174002.705176-1-ivecera@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Content-Type: text/plain; charset="utf-8" Refactor the reference counting mechanism for DPLL devices and pins to improve consistency and prevent potential lifetime issues. Introduce internal helpers __dpll_{device,pin}_{hold,put}() to centralize reference management. Update the internal XArray reference helpers (dpll_xa_ref_*) to automatically grab a reference to the target object when it is added to a list, and release it when removed. This ensures that objects linked internally (e.g., pins referenced by parent pins) are properly kept alive without relying on the caller to manually manage the count. Consequently, remove the now redundant manual `refcount_inc/dec` calls in dpll_pin_on_pin_{,un}register()`, as ownership is now correctly handled by the dpll_xa_ref_* functions. Additionally, ensure that dpll_device_{,un}register()` takes/releases a reference to the device, ensuring the device object remains valid for the duration of its registration. Reviewed-by: Aleksandr Loktionov Signed-off-by: Ivan Vecera Reviewed-by: Arkadiusz Kubalewski --- drivers/dpll/dpll_core.c | 74 +++++++++++++++++++++++++++------------- 1 file changed, 50 insertions(+), 24 deletions(-) diff --git a/drivers/dpll/dpll_core.c b/drivers/dpll/dpll_core.c index 59081cf2c73ae..f6ab4f0cad84d 100644 --- a/drivers/dpll/dpll_core.c +++ b/drivers/dpll/dpll_core.c @@ -83,6 +83,45 @@ void dpll_pin_notify(struct dpll_pin *pin, unsigned long= action) call_dpll_notifiers(action, &info); } =20 +static void __dpll_device_hold(struct dpll_device *dpll) +{ + refcount_inc(&dpll->refcount); +} + +static void __dpll_device_put(struct dpll_device *dpll) +{ + if (refcount_dec_and_test(&dpll->refcount)) { + ASSERT_DPLL_NOT_REGISTERED(dpll); + WARN_ON_ONCE(!xa_empty(&dpll->pin_refs)); + xa_destroy(&dpll->pin_refs); + xa_erase(&dpll_device_xa, dpll->id); + WARN_ON(!list_empty(&dpll->registration_list)); + kfree(dpll); + } +} + +static void __dpll_pin_hold(struct dpll_pin *pin) +{ + refcount_inc(&pin->refcount); +} + +static void dpll_pin_idx_free(u32 pin_idx); +static void dpll_pin_prop_free(struct dpll_pin_properties *prop); + +static void __dpll_pin_put(struct dpll_pin *pin) +{ + if (refcount_dec_and_test(&pin->refcount)) { + xa_erase(&dpll_pin_xa, pin->id); + xa_destroy(&pin->dpll_refs); + xa_destroy(&pin->parent_refs); + xa_destroy(&pin->ref_sync_pins); + dpll_pin_prop_free(&pin->prop); + fwnode_handle_put(pin->fwnode); + dpll_pin_idx_free(pin->pin_idx); + kfree_rcu(pin, rcu); + } +} + struct dpll_device *dpll_device_get_by_id(int id) { if (xa_get_mark(&dpll_device_xa, id, DPLL_REGISTERED)) @@ -152,6 +191,7 @@ dpll_xa_ref_pin_add(struct xarray *xa_pins, struct dpll= _pin *pin, reg->ops =3D ops; reg->priv =3D priv; reg->cookie =3D cookie; + __dpll_pin_hold(pin); if (ref_exists) refcount_inc(&ref->refcount); list_add_tail(®->list, &ref->registration_list); @@ -174,6 +214,7 @@ static int dpll_xa_ref_pin_del(struct xarray *xa_pins, = struct dpll_pin *pin, if (WARN_ON(!reg)) return -EINVAL; list_del(®->list); + __dpll_pin_put(pin); kfree(reg); if (refcount_dec_and_test(&ref->refcount)) { xa_erase(xa_pins, i); @@ -231,6 +272,7 @@ dpll_xa_ref_dpll_add(struct xarray *xa_dplls, struct dp= ll_device *dpll, reg->ops =3D ops; reg->priv =3D priv; reg->cookie =3D cookie; + __dpll_device_hold(dpll); if (ref_exists) refcount_inc(&ref->refcount); list_add_tail(®->list, &ref->registration_list); @@ -253,6 +295,7 @@ dpll_xa_ref_dpll_del(struct xarray *xa_dplls, struct dp= ll_device *dpll, if (WARN_ON(!reg)) return; list_del(®->list); + __dpll_device_put(dpll); kfree(reg); if (refcount_dec_and_test(&ref->refcount)) { xa_erase(xa_dplls, i); @@ -323,8 +366,8 @@ dpll_device_get(u64 clock_id, u32 device_idx, struct mo= dule *module) if (dpll->clock_id =3D=3D clock_id && dpll->device_idx =3D=3D device_idx && dpll->module =3D=3D module) { + __dpll_device_hold(dpll); ret =3D dpll; - refcount_inc(&ret->refcount); break; } } @@ -347,14 +390,7 @@ EXPORT_SYMBOL_GPL(dpll_device_get); void dpll_device_put(struct dpll_device *dpll) { mutex_lock(&dpll_lock); - if (refcount_dec_and_test(&dpll->refcount)) { - ASSERT_DPLL_NOT_REGISTERED(dpll); - WARN_ON_ONCE(!xa_empty(&dpll->pin_refs)); - xa_destroy(&dpll->pin_refs); - xa_erase(&dpll_device_xa, dpll->id); - WARN_ON(!list_empty(&dpll->registration_list)); - kfree(dpll); - } + __dpll_device_put(dpll); mutex_unlock(&dpll_lock); } EXPORT_SYMBOL_GPL(dpll_device_put); @@ -416,6 +452,7 @@ int dpll_device_register(struct dpll_device *dpll, enum= dpll_type type, reg->ops =3D ops; reg->priv =3D priv; dpll->type =3D type; + __dpll_device_hold(dpll); first_registration =3D list_empty(&dpll->registration_list); list_add_tail(®->list, &dpll->registration_list); if (!first_registration) { @@ -455,6 +492,7 @@ void dpll_device_unregister(struct dpll_device *dpll, return; } list_del(®->list); + __dpll_device_put(dpll); kfree(reg); =20 if (!list_empty(&dpll->registration_list)) { @@ -666,8 +704,8 @@ dpll_pin_get(u64 clock_id, u32 pin_idx, struct module *= module, if (pos->clock_id =3D=3D clock_id && pos->pin_idx =3D=3D pin_idx && pos->module =3D=3D module) { + __dpll_pin_hold(pos); ret =3D pos; - refcount_inc(&ret->refcount); break; } } @@ -690,16 +728,7 @@ EXPORT_SYMBOL_GPL(dpll_pin_get); void dpll_pin_put(struct dpll_pin *pin) { mutex_lock(&dpll_lock); - if (refcount_dec_and_test(&pin->refcount)) { - xa_erase(&dpll_pin_xa, pin->id); - xa_destroy(&pin->dpll_refs); - xa_destroy(&pin->parent_refs); - xa_destroy(&pin->ref_sync_pins); - dpll_pin_prop_free(&pin->prop); - fwnode_handle_put(pin->fwnode); - dpll_pin_idx_free(pin->pin_idx); - kfree_rcu(pin, rcu); - } + __dpll_pin_put(pin); mutex_unlock(&dpll_lock); } EXPORT_SYMBOL_GPL(dpll_pin_put); @@ -740,8 +769,8 @@ struct dpll_pin *fwnode_dpll_pin_find(struct fwnode_han= dle *fwnode) mutex_lock(&dpll_lock); xa_for_each(&dpll_pin_xa, index, pin) { if (pin->fwnode =3D=3D fwnode) { + __dpll_pin_hold(pin); ret =3D pin; - refcount_inc(&ret->refcount); break; } } @@ -893,7 +922,6 @@ int dpll_pin_on_pin_register(struct dpll_pin *parent, s= truct dpll_pin *pin, ret =3D dpll_xa_ref_pin_add(&pin->parent_refs, parent, ops, priv, pin); if (ret) goto unlock; - refcount_inc(&pin->refcount); xa_for_each(&parent->dpll_refs, i, ref) { ret =3D __dpll_pin_register(ref->dpll, pin, ops, priv, parent); if (ret) { @@ -913,7 +941,6 @@ int dpll_pin_on_pin_register(struct dpll_pin *parent, s= truct dpll_pin *pin, parent); dpll_pin_delete_ntf(pin); } - refcount_dec(&pin->refcount); dpll_xa_ref_pin_del(&pin->parent_refs, parent, ops, priv, pin); unlock: mutex_unlock(&dpll_lock); @@ -940,7 +967,6 @@ void dpll_pin_on_pin_unregister(struct dpll_pin *parent= , struct dpll_pin *pin, mutex_lock(&dpll_lock); dpll_pin_delete_ntf(pin); dpll_xa_ref_pin_del(&pin->parent_refs, parent, ops, priv, pin); - refcount_dec(&pin->refcount); xa_for_each(&pin->dpll_refs, i, ref) __dpll_pin_unregister(ref->dpll, pin, ops, priv, parent); mutex_unlock(&dpll_lock); --=20 2.52.0 From nobody Sat Feb 7 04:47:32 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8BD01363C74 for ; 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Tue, 03 Feb 2026 12:41:00 -0500 X-MC-Unique: sMwUEMfUOJC03t4qXo4Cgw-1 X-Mimecast-MFC-AGG-ID: sMwUEMfUOJC03t4qXo4Cgw_1770140456 Received: from mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.4]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 562FF18005AE; Tue, 3 Feb 2026 17:40:56 +0000 (UTC) Received: from p16v.luc.cera.cz (unknown [10.45.224.28]) by mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 13E733001DB7; Tue, 3 Feb 2026 17:40:49 +0000 (UTC) From: Ivan Vecera To: netdev@vger.kernel.org Cc: Aleksandr Loktionov , Petr Oros , Alexander Lobakin , Andrew Lunn , Arkadiusz Kubalewski , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Jiri Pirko , Jonathan Lemon , Leon Romanovsky , Mark Bloch , Paolo Abeni , Prathosh Satish , Przemek Kitszel , Richard Cochran , Saeed Mahameed , Tariq Toukan , Tony Nguyen , Vadim Fedorenko , intel-wired-lan@lists.osuosl.org, linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org Subject: [PATCH net-next v5 7/9] dpll: Add reference count tracking support Date: Tue, 3 Feb 2026 18:40:00 +0100 Message-ID: <20260203174002.705176-8-ivecera@redhat.com> In-Reply-To: <20260203174002.705176-1-ivecera@redhat.com> References: <20260203174002.705176-1-ivecera@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Content-Type: text/plain; charset="utf-8" Add support for the REF_TRACKER infrastructure to the DPLL subsystem. When enabled, this allows developers to track and debug reference counting leaks or imbalances for dpll_device and dpll_pin objects. It records stack traces for every get/put operation and exposes this information via debugfs at: /sys/kernel/debug/ref_tracker/dpll_device_* /sys/kernel/debug/ref_tracker/dpll_pin_* The following API changes are made to support this: 1. dpll_device_get() / dpll_device_put() now accept a 'dpll_tracker *' (which is a typedef to 'struct ref_tracker *' when enabled, or an empty struct otherwise). 2. dpll_pin_get() / dpll_pin_put() and fwnode_dpll_pin_find() similarly accept the tracker argument. 3. Internal registration structures now hold a tracker to associate the reference held by the registration with the specific owner. All existing in-tree drivers (ice, mlx5, ptp_ocp, zl3073x) are updated to pass NULL for the new tracker argument, maintaining current behavior while enabling future debugging capabilities. Reviewed-by: Aleksandr Loktionov Co-developed-by: Petr Oros Signed-off-by: Petr Oros Signed-off-by: Ivan Vecera --- v5: * fixed typo v4: * added missing tracker parameter to fwnode_dpll_pin_find() stub v3: * added Kconfig dependency on STACKTRACE_SUPPORT and DEBUG_KERNEL --- drivers/dpll/Kconfig | 15 +++ drivers/dpll/dpll_core.c | 98 ++++++++++++++----- drivers/dpll/dpll_core.h | 5 + drivers/dpll/zl3073x/dpll.c | 12 +-- drivers/net/ethernet/intel/ice/ice_dpll.c | 14 +-- .../net/ethernet/mellanox/mlx5/core/dpll.c | 13 +-- drivers/ptp/ptp_ocp.c | 15 +-- include/linux/dpll.h | 21 ++-- 8 files changed, 139 insertions(+), 54 deletions(-) diff --git a/drivers/dpll/Kconfig b/drivers/dpll/Kconfig index ade872c915ac6..be98969f040ab 100644 --- a/drivers/dpll/Kconfig +++ b/drivers/dpll/Kconfig @@ -8,6 +8,21 @@ menu "DPLL device support" config DPLL bool =20 +config DPLL_REFCNT_TRACKER + bool "DPLL reference count tracking" + depends on DEBUG_KERNEL && STACKTRACE_SUPPORT && DPLL + select REF_TRACKER + help + Enable reference count tracking for DPLL devices and pins. + This helps debugging reference leaks and use-after-free bugs + by recording stack traces for each get/put operation. + + The tracking information is exposed via debugfs at: + /sys/kernel/debug/ref_tracker/dpll_device_* + /sys/kernel/debug/ref_tracker/dpll_pin_* + + If unsure, say N. + source "drivers/dpll/zl3073x/Kconfig" =20 endmenu diff --git a/drivers/dpll/dpll_core.c b/drivers/dpll/dpll_core.c index f6ab4f0cad84d..627a5b39a0efd 100644 --- a/drivers/dpll/dpll_core.c +++ b/drivers/dpll/dpll_core.c @@ -41,6 +41,7 @@ struct dpll_device_registration { struct list_head list; const struct dpll_device_ops *ops; void *priv; + dpll_tracker tracker; }; =20 struct dpll_pin_registration { @@ -48,6 +49,7 @@ struct dpll_pin_registration { const struct dpll_pin_ops *ops; void *priv; void *cookie; + dpll_tracker tracker; }; =20 static int call_dpll_notifiers(unsigned long action, void *info) @@ -83,33 +85,68 @@ void dpll_pin_notify(struct dpll_pin *pin, unsigned lon= g action) call_dpll_notifiers(action, &info); } =20 -static void __dpll_device_hold(struct dpll_device *dpll) +static void dpll_device_tracker_alloc(struct dpll_device *dpll, + dpll_tracker *tracker) { +#ifdef CONFIG_DPLL_REFCNT_TRACKER + ref_tracker_alloc(&dpll->refcnt_tracker, tracker, GFP_KERNEL); +#endif +} + +static void dpll_device_tracker_free(struct dpll_device *dpll, + dpll_tracker *tracker) +{ +#ifdef CONFIG_DPLL_REFCNT_TRACKER + ref_tracker_free(&dpll->refcnt_tracker, tracker); +#endif +} + +static void __dpll_device_hold(struct dpll_device *dpll, dpll_tracker *tra= cker) +{ + dpll_device_tracker_alloc(dpll, tracker); refcount_inc(&dpll->refcount); } =20 -static void __dpll_device_put(struct dpll_device *dpll) +static void __dpll_device_put(struct dpll_device *dpll, dpll_tracker *trac= ker) { + dpll_device_tracker_free(dpll, tracker); if (refcount_dec_and_test(&dpll->refcount)) { ASSERT_DPLL_NOT_REGISTERED(dpll); WARN_ON_ONCE(!xa_empty(&dpll->pin_refs)); xa_destroy(&dpll->pin_refs); xa_erase(&dpll_device_xa, dpll->id); WARN_ON(!list_empty(&dpll->registration_list)); + ref_tracker_dir_exit(&dpll->refcnt_tracker); kfree(dpll); } } =20 -static void __dpll_pin_hold(struct dpll_pin *pin) +static void dpll_pin_tracker_alloc(struct dpll_pin *pin, dpll_tracker *tra= cker) { +#ifdef CONFIG_DPLL_REFCNT_TRACKER + ref_tracker_alloc(&pin->refcnt_tracker, tracker, GFP_KERNEL); +#endif +} + +static void dpll_pin_tracker_free(struct dpll_pin *pin, dpll_tracker *trac= ker) +{ +#ifdef CONFIG_DPLL_REFCNT_TRACKER + ref_tracker_free(&pin->refcnt_tracker, tracker); +#endif +} + +static void __dpll_pin_hold(struct dpll_pin *pin, dpll_tracker *tracker) +{ + dpll_pin_tracker_alloc(pin, tracker); refcount_inc(&pin->refcount); } =20 static void dpll_pin_idx_free(u32 pin_idx); static void dpll_pin_prop_free(struct dpll_pin_properties *prop); =20 -static void __dpll_pin_put(struct dpll_pin *pin) +static void __dpll_pin_put(struct dpll_pin *pin, dpll_tracker *tracker) { + dpll_pin_tracker_free(pin, tracker); if (refcount_dec_and_test(&pin->refcount)) { xa_erase(&dpll_pin_xa, pin->id); xa_destroy(&pin->dpll_refs); @@ -118,6 +155,7 @@ static void __dpll_pin_put(struct dpll_pin *pin) dpll_pin_prop_free(&pin->prop); fwnode_handle_put(pin->fwnode); dpll_pin_idx_free(pin->pin_idx); + ref_tracker_dir_exit(&pin->refcnt_tracker); kfree_rcu(pin, rcu); } } @@ -191,7 +229,7 @@ dpll_xa_ref_pin_add(struct xarray *xa_pins, struct dpll= _pin *pin, reg->ops =3D ops; reg->priv =3D priv; reg->cookie =3D cookie; - __dpll_pin_hold(pin); + __dpll_pin_hold(pin, ®->tracker); if (ref_exists) refcount_inc(&ref->refcount); list_add_tail(®->list, &ref->registration_list); @@ -214,7 +252,7 @@ static int dpll_xa_ref_pin_del(struct xarray *xa_pins, = struct dpll_pin *pin, if (WARN_ON(!reg)) return -EINVAL; list_del(®->list); - __dpll_pin_put(pin); + __dpll_pin_put(pin, ®->tracker); kfree(reg); if (refcount_dec_and_test(&ref->refcount)) { xa_erase(xa_pins, i); @@ -272,7 +310,7 @@ dpll_xa_ref_dpll_add(struct xarray *xa_dplls, struct dp= ll_device *dpll, reg->ops =3D ops; reg->priv =3D priv; reg->cookie =3D cookie; - __dpll_device_hold(dpll); + __dpll_device_hold(dpll, ®->tracker); if (ref_exists) refcount_inc(&ref->refcount); list_add_tail(®->list, &ref->registration_list); @@ -295,7 +333,7 @@ dpll_xa_ref_dpll_del(struct xarray *xa_dplls, struct dp= ll_device *dpll, if (WARN_ON(!reg)) return; list_del(®->list); - __dpll_device_put(dpll); + __dpll_device_put(dpll, ®->tracker); kfree(reg); if (refcount_dec_and_test(&ref->refcount)) { xa_erase(xa_dplls, i); @@ -337,6 +375,7 @@ dpll_device_alloc(const u64 clock_id, u32 device_idx, s= truct module *module) return ERR_PTR(ret); } xa_init_flags(&dpll->pin_refs, XA_FLAGS_ALLOC); + ref_tracker_dir_init(&dpll->refcnt_tracker, 128, "dpll_device"); =20 return dpll; } @@ -346,6 +385,7 @@ dpll_device_alloc(const u64 clock_id, u32 device_idx, s= truct module *module) * @clock_id: clock_id of creator * @device_idx: idx given by device driver * @module: reference to registering module + * @tracker: tracking object for the acquired reference * * Get existing object of a dpll device, unique for given arguments. * Create new if doesn't exist yet. @@ -356,7 +396,8 @@ dpll_device_alloc(const u64 clock_id, u32 device_idx, s= truct module *module) * * ERR_PTR(X) - error */ struct dpll_device * -dpll_device_get(u64 clock_id, u32 device_idx, struct module *module) +dpll_device_get(u64 clock_id, u32 device_idx, struct module *module, + dpll_tracker *tracker) { struct dpll_device *dpll, *ret =3D NULL; unsigned long index; @@ -366,13 +407,17 @@ dpll_device_get(u64 clock_id, u32 device_idx, struct = module *module) if (dpll->clock_id =3D=3D clock_id && dpll->device_idx =3D=3D device_idx && dpll->module =3D=3D module) { - __dpll_device_hold(dpll); + __dpll_device_hold(dpll, tracker); ret =3D dpll; break; } } - if (!ret) + if (!ret) { ret =3D dpll_device_alloc(clock_id, device_idx, module); + if (!IS_ERR(ret)) + dpll_device_tracker_alloc(ret, tracker); + } + mutex_unlock(&dpll_lock); =20 return ret; @@ -382,15 +427,16 @@ EXPORT_SYMBOL_GPL(dpll_device_get); /** * dpll_device_put - decrease the refcount and free memory if possible * @dpll: dpll_device struct pointer + * @tracker: tracking object for the acquired reference * * Context: Acquires a lock (dpll_lock) * Drop reference for a dpll device, if all references are gone, delete * dpll device object. */ -void dpll_device_put(struct dpll_device *dpll) +void dpll_device_put(struct dpll_device *dpll, dpll_tracker *tracker) { mutex_lock(&dpll_lock); - __dpll_device_put(dpll); + __dpll_device_put(dpll, tracker); mutex_unlock(&dpll_lock); } EXPORT_SYMBOL_GPL(dpll_device_put); @@ -452,7 +498,7 @@ int dpll_device_register(struct dpll_device *dpll, enum= dpll_type type, reg->ops =3D ops; reg->priv =3D priv; dpll->type =3D type; - __dpll_device_hold(dpll); + __dpll_device_hold(dpll, ®->tracker); first_registration =3D list_empty(&dpll->registration_list); list_add_tail(®->list, &dpll->registration_list); if (!first_registration) { @@ -492,7 +538,7 @@ void dpll_device_unregister(struct dpll_device *dpll, return; } list_del(®->list); - __dpll_device_put(dpll); + __dpll_device_put(dpll, ®->tracker); kfree(reg); =20 if (!list_empty(&dpll->registration_list)) { @@ -622,6 +668,7 @@ dpll_pin_alloc(u64 clock_id, u32 pin_idx, struct module= *module, &dpll_pin_xa_id, GFP_KERNEL); if (ret < 0) goto err_xa_alloc; + ref_tracker_dir_init(&pin->refcnt_tracker, 128, "dpll_pin"); return pin; err_xa_alloc: xa_destroy(&pin->dpll_refs); @@ -683,6 +730,7 @@ EXPORT_SYMBOL_GPL(unregister_dpll_notifier); * @pin_idx: idx given by dev driver * @module: reference to registering module * @prop: dpll pin properties + * @tracker: tracking object for the acquired reference * * Get existing object of a pin (unique for given arguments) or create new * if doesn't exist yet. @@ -694,7 +742,7 @@ EXPORT_SYMBOL_GPL(unregister_dpll_notifier); */ struct dpll_pin * dpll_pin_get(u64 clock_id, u32 pin_idx, struct module *module, - const struct dpll_pin_properties *prop) + const struct dpll_pin_properties *prop, dpll_tracker *tracker) { struct dpll_pin *pos, *ret =3D NULL; unsigned long i; @@ -704,13 +752,16 @@ dpll_pin_get(u64 clock_id, u32 pin_idx, struct module= *module, if (pos->clock_id =3D=3D clock_id && pos->pin_idx =3D=3D pin_idx && pos->module =3D=3D module) { - __dpll_pin_hold(pos); + __dpll_pin_hold(pos, tracker); ret =3D pos; break; } } - if (!ret) + if (!ret) { ret =3D dpll_pin_alloc(clock_id, pin_idx, module, prop); + if (!IS_ERR(ret)) + dpll_pin_tracker_alloc(ret, tracker); + } mutex_unlock(&dpll_lock); =20 return ret; @@ -720,15 +771,16 @@ EXPORT_SYMBOL_GPL(dpll_pin_get); /** * dpll_pin_put - decrease the refcount and free memory if possible * @pin: pointer to a pin to be put + * @tracker: tracking object for the acquired reference * * Drop reference for a pin, if all references are gone, delete pin object. * * Context: Acquires a lock (dpll_lock) */ -void dpll_pin_put(struct dpll_pin *pin) +void dpll_pin_put(struct dpll_pin *pin, dpll_tracker *tracker) { mutex_lock(&dpll_lock); - __dpll_pin_put(pin); + __dpll_pin_put(pin, tracker); mutex_unlock(&dpll_lock); } EXPORT_SYMBOL_GPL(dpll_pin_put); @@ -752,6 +804,7 @@ EXPORT_SYMBOL_GPL(dpll_pin_fwnode_set); /** * fwnode_dpll_pin_find - find dpll pin by firmware node reference * @fwnode: reference to firmware node + * @tracker: tracking object for the acquired reference * * Get existing object of a pin that is associated with given firmware node * reference. @@ -761,7 +814,8 @@ EXPORT_SYMBOL_GPL(dpll_pin_fwnode_set); * * valid dpll_pin pointer on success * * NULL when no such pin exists */ -struct dpll_pin *fwnode_dpll_pin_find(struct fwnode_handle *fwnode) +struct dpll_pin *fwnode_dpll_pin_find(struct fwnode_handle *fwnode, + dpll_tracker *tracker) { struct dpll_pin *pin, *ret =3D NULL; unsigned long index; @@ -769,7 +823,7 @@ struct dpll_pin *fwnode_dpll_pin_find(struct fwnode_han= dle *fwnode) mutex_lock(&dpll_lock); xa_for_each(&dpll_pin_xa, index, pin) { if (pin->fwnode =3D=3D fwnode) { - __dpll_pin_hold(pin); + __dpll_pin_hold(pin, tracker); ret =3D pin; break; } diff --git a/drivers/dpll/dpll_core.h b/drivers/dpll/dpll_core.h index b7b4bb251f739..71ac88ef20172 100644 --- a/drivers/dpll/dpll_core.h +++ b/drivers/dpll/dpll_core.h @@ -10,6 +10,7 @@ #include #include #include +#include #include "dpll_nl.h" =20 #define DPLL_REGISTERED XA_MARK_1 @@ -23,6 +24,7 @@ * @type: type of a dpll * @pin_refs: stores pins registered within a dpll * @refcount: refcount + * @refcnt_tracker: ref_tracker directory for debugging reference leaks * @registration_list: list of registered ops and priv data of dpll owners **/ struct dpll_device { @@ -33,6 +35,7 @@ struct dpll_device { enum dpll_type type; struct xarray pin_refs; refcount_t refcount; + struct ref_tracker_dir refcnt_tracker; struct list_head registration_list; }; =20 @@ -48,6 +51,7 @@ struct dpll_device { * @ref_sync_pins: hold references to pins for Reference SYNC feature * @prop: pin properties copied from the registerer * @refcount: refcount + * @refcnt_tracker: ref_tracker directory for debugging reference leaks * @rcu: rcu_head for kfree_rcu() **/ struct dpll_pin { @@ -61,6 +65,7 @@ struct dpll_pin { struct xarray ref_sync_pins; struct dpll_pin_properties prop; refcount_t refcount; + struct ref_tracker_dir refcnt_tracker; struct rcu_head rcu; }; =20 diff --git a/drivers/dpll/zl3073x/dpll.c b/drivers/dpll/zl3073x/dpll.c index 9eed21088adac..8788bcab7ec53 100644 --- a/drivers/dpll/zl3073x/dpll.c +++ b/drivers/dpll/zl3073x/dpll.c @@ -1480,7 +1480,7 @@ zl3073x_dpll_pin_register(struct zl3073x_dpll_pin *pi= n, u32 index) =20 /* Create or get existing DPLL pin */ pin->dpll_pin =3D dpll_pin_get(zldpll->dev->clock_id, index, THIS_MODULE, - &props->dpll_props); + &props->dpll_props, NULL); if (IS_ERR(pin->dpll_pin)) { rc =3D PTR_ERR(pin->dpll_pin); goto err_pin_get; @@ -1503,7 +1503,7 @@ zl3073x_dpll_pin_register(struct zl3073x_dpll_pin *pi= n, u32 index) return 0; =20 err_register: - dpll_pin_put(pin->dpll_pin); + dpll_pin_put(pin->dpll_pin, NULL); err_prio_get: pin->dpll_pin =3D NULL; err_pin_get: @@ -1534,7 +1534,7 @@ zl3073x_dpll_pin_unregister(struct zl3073x_dpll_pin *= pin) /* Unregister the pin */ dpll_pin_unregister(zldpll->dpll_dev, pin->dpll_pin, ops, pin); =20 - dpll_pin_put(pin->dpll_pin); + dpll_pin_put(pin->dpll_pin, NULL); pin->dpll_pin =3D NULL; } =20 @@ -1708,7 +1708,7 @@ zl3073x_dpll_device_register(struct zl3073x_dpll *zld= pll) dpll_mode_refsel); =20 zldpll->dpll_dev =3D dpll_device_get(zldev->clock_id, zldpll->id, - THIS_MODULE); + THIS_MODULE, NULL); if (IS_ERR(zldpll->dpll_dev)) { rc =3D PTR_ERR(zldpll->dpll_dev); zldpll->dpll_dev =3D NULL; @@ -1720,7 +1720,7 @@ zl3073x_dpll_device_register(struct zl3073x_dpll *zld= pll) zl3073x_prop_dpll_type_get(zldev, zldpll->id), &zl3073x_dpll_device_ops, zldpll); if (rc) { - dpll_device_put(zldpll->dpll_dev); + dpll_device_put(zldpll->dpll_dev, NULL); zldpll->dpll_dev =3D NULL; } =20 @@ -1743,7 +1743,7 @@ zl3073x_dpll_device_unregister(struct zl3073x_dpll *z= ldpll) =20 dpll_device_unregister(zldpll->dpll_dev, &zl3073x_dpll_device_ops, zldpll); - dpll_device_put(zldpll->dpll_dev); + dpll_device_put(zldpll->dpll_dev, NULL); zldpll->dpll_dev =3D NULL; } =20 diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethern= et/intel/ice/ice_dpll.c index 53b54e395a2ed..64b7b045ecd58 100644 --- a/drivers/net/ethernet/intel/ice/ice_dpll.c +++ b/drivers/net/ethernet/intel/ice/ice_dpll.c @@ -2814,7 +2814,7 @@ static void ice_dpll_release_pins(struct ice_dpll_pin= *pins, int count) int i; =20 for (i =3D 0; i < count; i++) - dpll_pin_put(pins[i].pin); + dpll_pin_put(pins[i].pin, NULL); } =20 /** @@ -2840,7 +2840,7 @@ ice_dpll_get_pins(struct ice_pf *pf, struct ice_dpll_= pin *pins, =20 for (i =3D 0; i < count; i++) { pins[i].pin =3D dpll_pin_get(clock_id, i + start_idx, THIS_MODULE, - &pins[i].prop); + &pins[i].prop, NULL); if (IS_ERR(pins[i].pin)) { ret =3D PTR_ERR(pins[i].pin); goto release_pins; @@ -2851,7 +2851,7 @@ ice_dpll_get_pins(struct ice_pf *pf, struct ice_dpll_= pin *pins, =20 release_pins: while (--i >=3D 0) - dpll_pin_put(pins[i].pin); + dpll_pin_put(pins[i].pin, NULL); return ret; } =20 @@ -3037,7 +3037,7 @@ static void ice_dpll_deinit_rclk_pin(struct ice_pf *p= f) if (WARN_ON_ONCE(!vsi || !vsi->netdev)) return; dpll_netdev_pin_clear(vsi->netdev); - dpll_pin_put(rclk->pin); + dpll_pin_put(rclk->pin, NULL); } =20 /** @@ -3247,7 +3247,7 @@ ice_dpll_deinit_dpll(struct ice_pf *pf, struct ice_dp= ll *d, bool cgu) { if (cgu) dpll_device_unregister(d->dpll, d->ops, d); - dpll_device_put(d->dpll); + dpll_device_put(d->dpll, NULL); } =20 /** @@ -3271,7 +3271,7 @@ ice_dpll_init_dpll(struct ice_pf *pf, struct ice_dpll= *d, bool cgu, u64 clock_id =3D pf->dplls.clock_id; int ret; =20 - d->dpll =3D dpll_device_get(clock_id, d->dpll_idx, THIS_MODULE); + d->dpll =3D dpll_device_get(clock_id, d->dpll_idx, THIS_MODULE, NULL); if (IS_ERR(d->dpll)) { ret =3D PTR_ERR(d->dpll); dev_err(ice_pf_to_dev(pf), @@ -3287,7 +3287,7 @@ ice_dpll_init_dpll(struct ice_pf *pf, struct ice_dpll= *d, bool cgu, ice_dpll_update_state(pf, d, true); ret =3D dpll_device_register(d->dpll, type, ops, d); if (ret) { - dpll_device_put(d->dpll); + dpll_device_put(d->dpll, NULL); return ret; } d->ops =3D ops; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/dpll.c b/drivers/net/e= thernet/mellanox/mlx5/core/dpll.c index 3ea8a1766ae28..541d83e5d7183 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/dpll.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/dpll.c @@ -438,7 +438,7 @@ static int mlx5_dpll_probe(struct auxiliary_device *ade= v, auxiliary_set_drvdata(adev, mdpll); =20 /* Multiple mdev instances might share one DPLL device. */ - mdpll->dpll =3D dpll_device_get(clock_id, 0, THIS_MODULE); + mdpll->dpll =3D dpll_device_get(clock_id, 0, THIS_MODULE, NULL); if (IS_ERR(mdpll->dpll)) { err =3D PTR_ERR(mdpll->dpll); goto err_free_mdpll; @@ -451,7 +451,8 @@ static int mlx5_dpll_probe(struct auxiliary_device *ade= v, =20 /* Multiple mdev instances might share one DPLL pin. */ mdpll->dpll_pin =3D dpll_pin_get(clock_id, mlx5_get_dev_index(mdev), - THIS_MODULE, &mlx5_dpll_pin_properties); + THIS_MODULE, &mlx5_dpll_pin_properties, + NULL); if (IS_ERR(mdpll->dpll_pin)) { err =3D PTR_ERR(mdpll->dpll_pin); goto err_unregister_dpll_device; @@ -479,11 +480,11 @@ static int mlx5_dpll_probe(struct auxiliary_device *a= dev, dpll_pin_unregister(mdpll->dpll, mdpll->dpll_pin, &mlx5_dpll_pins_ops, mdpll); err_put_dpll_pin: - dpll_pin_put(mdpll->dpll_pin); + dpll_pin_put(mdpll->dpll_pin, NULL); err_unregister_dpll_device: dpll_device_unregister(mdpll->dpll, &mlx5_dpll_device_ops, mdpll); err_put_dpll_device: - dpll_device_put(mdpll->dpll); + dpll_device_put(mdpll->dpll, NULL); err_free_mdpll: kfree(mdpll); return err; @@ -499,9 +500,9 @@ static void mlx5_dpll_remove(struct auxiliary_device *a= dev) destroy_workqueue(mdpll->wq); dpll_pin_unregister(mdpll->dpll, mdpll->dpll_pin, &mlx5_dpll_pins_ops, mdpll); - dpll_pin_put(mdpll->dpll_pin); + dpll_pin_put(mdpll->dpll_pin, NULL); dpll_device_unregister(mdpll->dpll, &mlx5_dpll_device_ops, mdpll); - dpll_device_put(mdpll->dpll); + dpll_device_put(mdpll->dpll, NULL); kfree(mdpll); =20 mlx5_dpll_synce_status_set(mdev, diff --git a/drivers/ptp/ptp_ocp.c b/drivers/ptp/ptp_ocp.c index 65fe05cac8c42..f39b3966b3e8c 100644 --- a/drivers/ptp/ptp_ocp.c +++ b/drivers/ptp/ptp_ocp.c @@ -4788,7 +4788,7 @@ ptp_ocp_probe(struct pci_dev *pdev, const struct pci_= device_id *id) devlink_register(devlink); =20 clkid =3D pci_get_dsn(pdev); - bp->dpll =3D dpll_device_get(clkid, 0, THIS_MODULE); + bp->dpll =3D dpll_device_get(clkid, 0, THIS_MODULE, NULL); if (IS_ERR(bp->dpll)) { err =3D PTR_ERR(bp->dpll); dev_err(&pdev->dev, "dpll_device_alloc failed\n"); @@ -4800,7 +4800,8 @@ ptp_ocp_probe(struct pci_dev *pdev, const struct pci_= device_id *id) goto out; =20 for (i =3D 0; i < OCP_SMA_NUM; i++) { - bp->sma[i].dpll_pin =3D dpll_pin_get(clkid, i, THIS_MODULE, &bp->sma[i].= dpll_prop); + bp->sma[i].dpll_pin =3D dpll_pin_get(clkid, i, THIS_MODULE, + &bp->sma[i].dpll_prop, NULL); if (IS_ERR(bp->sma[i].dpll_pin)) { err =3D PTR_ERR(bp->sma[i].dpll_pin); goto out_dpll; @@ -4809,7 +4810,7 @@ ptp_ocp_probe(struct pci_dev *pdev, const struct pci_= device_id *id) err =3D dpll_pin_register(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]); if (err) { - dpll_pin_put(bp->sma[i].dpll_pin); + dpll_pin_put(bp->sma[i].dpll_pin, NULL); goto out_dpll; } } @@ -4819,9 +4820,9 @@ ptp_ocp_probe(struct pci_dev *pdev, const struct pci_= device_id *id) out_dpll: while (i--) { dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->= sma[i]); - dpll_pin_put(bp->sma[i].dpll_pin); + dpll_pin_put(bp->sma[i].dpll_pin, NULL); } - dpll_device_put(bp->dpll); + dpll_device_put(bp->dpll, NULL); out: ptp_ocp_detach(bp); out_disable: @@ -4842,11 +4843,11 @@ ptp_ocp_remove(struct pci_dev *pdev) for (i =3D 0; i < OCP_SMA_NUM; i++) { if (bp->sma[i].dpll_pin) { dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp-= >sma[i]); - dpll_pin_put(bp->sma[i].dpll_pin); + dpll_pin_put(bp->sma[i].dpll_pin, NULL); } } dpll_device_unregister(bp->dpll, &dpll_ops, bp); - dpll_device_put(bp->dpll); + dpll_device_put(bp->dpll, NULL); devlink_unregister(devlink); ptp_ocp_detach(bp); pci_disable_device(pdev); diff --git a/include/linux/dpll.h b/include/linux/dpll.h index 8fff048131f1d..2ce295b46b8cd 100644 --- a/include/linux/dpll.h +++ b/include/linux/dpll.h @@ -18,6 +18,7 @@ struct dpll_device; struct dpll_pin; struct dpll_pin_esync; struct fwnode_handle; +struct ref_tracker; =20 struct dpll_device_ops { int (*mode_get)(const struct dpll_device *dpll, void *dpll_priv, @@ -173,6 +174,12 @@ struct dpll_pin_properties { u32 phase_gran; }; =20 +#ifdef CONFIG_DPLL_REFCNT_TRACKER +typedef struct ref_tracker *dpll_tracker; +#else +typedef struct {} dpll_tracker; +#endif + #define DPLL_DEVICE_CREATED 1 #define DPLL_DEVICE_DELETED 2 #define DPLL_DEVICE_CHANGED 3 @@ -205,7 +212,8 @@ size_t dpll_netdev_pin_handle_size(const struct net_dev= ice *dev); int dpll_netdev_add_pin_handle(struct sk_buff *msg, const struct net_device *dev); =20 -struct dpll_pin *fwnode_dpll_pin_find(struct fwnode_handle *fwnode); +struct dpll_pin *fwnode_dpll_pin_find(struct fwnode_handle *fwnode, + dpll_tracker *tracker); #else static inline void dpll_netdev_pin_set(struct net_device *dev, struct dpll_pin *dpll_pin) { } @@ -223,16 +231,17 @@ dpll_netdev_add_pin_handle(struct sk_buff *msg, const= struct net_device *dev) } =20 static inline struct dpll_pin * -fwnode_dpll_pin_find(struct fwnode_handle *fwnode) +fwnode_dpll_pin_find(struct fwnode_handle *fwnode, dpll_tracker *tracker) { return NULL; } #endif =20 struct dpll_device * -dpll_device_get(u64 clock_id, u32 dev_driver_id, struct module *module); +dpll_device_get(u64 clock_id, u32 dev_driver_id, struct module *module, + dpll_tracker *tracker); =20 -void dpll_device_put(struct dpll_device *dpll); +void dpll_device_put(struct dpll_device *dpll, dpll_tracker *tracker); =20 int dpll_device_register(struct dpll_device *dpll, enum dpll_type type, const struct dpll_device_ops *ops, void *priv); @@ -244,7 +253,7 @@ void dpll_device_unregister(struct dpll_device *dpll, =20 struct dpll_pin * dpll_pin_get(u64 clock_id, u32 dev_driver_id, struct module *module, - const struct dpll_pin_properties *prop); + const struct dpll_pin_properties *prop, dpll_tracker *tracker); =20 int dpll_pin_register(struct dpll_device *dpll, struct dpll_pin *pin, const struct dpll_pin_ops *ops, void *priv); @@ -252,7 +261,7 @@ int dpll_pin_register(struct dpll_device *dpll, struct = dpll_pin *pin, void dpll_pin_unregister(struct dpll_device *dpll, struct dpll_pin *pin, const struct dpll_pin_ops *ops, void *priv); =20 -void dpll_pin_put(struct dpll_pin *pin); +void dpll_pin_put(struct dpll_pin *pin, dpll_tracker *tracker); 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Tue, 3 Feb 2026 17:41:02 +0000 (UTC) Received: from p16v.luc.cera.cz (unknown [10.45.224.28]) by mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id BDE353001DB7; Tue, 3 Feb 2026 17:40:56 +0000 (UTC) From: Ivan Vecera To: netdev@vger.kernel.org Cc: Aleksandr Loktionov , Alexander Lobakin , Andrew Lunn , Arkadiusz Kubalewski , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Jiri Pirko , Jonathan Lemon , Leon Romanovsky , Mark Bloch , Paolo Abeni , Prathosh Satish , Przemek Kitszel , Richard Cochran , Saeed Mahameed , Tariq Toukan , Tony Nguyen , Vadim Fedorenko , intel-wired-lan@lists.osuosl.org, linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org Subject: [PATCH net-next v5 8/9] drivers: Add support for DPLL reference count tracking Date: Tue, 3 Feb 2026 18:40:01 +0100 Message-ID: <20260203174002.705176-9-ivecera@redhat.com> In-Reply-To: <20260203174002.705176-1-ivecera@redhat.com> References: <20260203174002.705176-1-ivecera@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Content-Type: text/plain; charset="utf-8" Update existing DPLL drivers to utilize the DPLL reference count tracking infrastructure. Add dpll_tracker fields to the drivers' internal device and pin structures. Pass pointers to these trackers when calling dpll_device_get/put() and dpll_pin_get/put(). This allows developers to inspect the specific references held by this driver via debugfs when CONFIG_DPLL_REFCNT_TRACKER is enabled, aiding in the debugging of resource leaks. Reviewed-by: Aleksandr Loktionov Signed-off-by: Ivan Vecera --- drivers/dpll/zl3073x/dpll.c | 14 ++++++++------ drivers/dpll/zl3073x/dpll.h | 2 ++ drivers/net/ethernet/intel/ice/ice_dpll.c | 15 ++++++++------- drivers/net/ethernet/intel/ice/ice_dpll.h | 4 ++++ drivers/net/ethernet/mellanox/mlx5/core/dpll.c | 15 +++++++++------ drivers/ptp/ptp_ocp.c | 17 ++++++++++------- 6 files changed, 41 insertions(+), 26 deletions(-) diff --git a/drivers/dpll/zl3073x/dpll.c b/drivers/dpll/zl3073x/dpll.c index 8788bcab7ec53..a99d143a7acde 100644 --- a/drivers/dpll/zl3073x/dpll.c +++ b/drivers/dpll/zl3073x/dpll.c @@ -29,6 +29,7 @@ * @list: this DPLL pin list entry * @dpll: DPLL the pin is registered to * @dpll_pin: pointer to registered dpll_pin + * @tracker: tracking object for the acquired reference * @label: package label * @dir: pin direction * @id: pin id @@ -44,6 +45,7 @@ struct zl3073x_dpll_pin { struct list_head list; struct zl3073x_dpll *dpll; struct dpll_pin *dpll_pin; + dpll_tracker tracker; char label[8]; enum dpll_pin_direction dir; u8 id; @@ -1480,7 +1482,7 @@ zl3073x_dpll_pin_register(struct zl3073x_dpll_pin *pi= n, u32 index) =20 /* Create or get existing DPLL pin */ pin->dpll_pin =3D dpll_pin_get(zldpll->dev->clock_id, index, THIS_MODULE, - &props->dpll_props, NULL); + &props->dpll_props, &pin->tracker); if (IS_ERR(pin->dpll_pin)) { rc =3D PTR_ERR(pin->dpll_pin); goto err_pin_get; @@ -1503,7 +1505,7 @@ zl3073x_dpll_pin_register(struct zl3073x_dpll_pin *pi= n, u32 index) return 0; =20 err_register: - dpll_pin_put(pin->dpll_pin, NULL); + dpll_pin_put(pin->dpll_pin, &pin->tracker); err_prio_get: pin->dpll_pin =3D NULL; err_pin_get: @@ -1534,7 +1536,7 @@ zl3073x_dpll_pin_unregister(struct zl3073x_dpll_pin *= pin) /* Unregister the pin */ dpll_pin_unregister(zldpll->dpll_dev, pin->dpll_pin, ops, pin); =20 - dpll_pin_put(pin->dpll_pin, NULL); + dpll_pin_put(pin->dpll_pin, &pin->tracker); pin->dpll_pin =3D NULL; } =20 @@ -1708,7 +1710,7 @@ zl3073x_dpll_device_register(struct zl3073x_dpll *zld= pll) dpll_mode_refsel); =20 zldpll->dpll_dev =3D dpll_device_get(zldev->clock_id, zldpll->id, - THIS_MODULE, NULL); + THIS_MODULE, &zldpll->tracker); if (IS_ERR(zldpll->dpll_dev)) { rc =3D PTR_ERR(zldpll->dpll_dev); zldpll->dpll_dev =3D NULL; @@ -1720,7 +1722,7 @@ zl3073x_dpll_device_register(struct zl3073x_dpll *zld= pll) zl3073x_prop_dpll_type_get(zldev, zldpll->id), &zl3073x_dpll_device_ops, zldpll); if (rc) { - dpll_device_put(zldpll->dpll_dev, NULL); + dpll_device_put(zldpll->dpll_dev, &zldpll->tracker); zldpll->dpll_dev =3D NULL; } =20 @@ -1743,7 +1745,7 @@ zl3073x_dpll_device_unregister(struct zl3073x_dpll *z= ldpll) =20 dpll_device_unregister(zldpll->dpll_dev, &zl3073x_dpll_device_ops, zldpll); - dpll_device_put(zldpll->dpll_dev, NULL); + dpll_device_put(zldpll->dpll_dev, &zldpll->tracker); zldpll->dpll_dev =3D NULL; } =20 diff --git a/drivers/dpll/zl3073x/dpll.h b/drivers/dpll/zl3073x/dpll.h index e8c39b44b356c..c65c798c37927 100644 --- a/drivers/dpll/zl3073x/dpll.h +++ b/drivers/dpll/zl3073x/dpll.h @@ -18,6 +18,7 @@ * @check_count: periodic check counter * @phase_monitor: is phase offset monitor enabled * @dpll_dev: pointer to registered DPLL device + * @tracker: tracking object for the acquired reference * @lock_status: last saved DPLL lock status * @pins: list of pins * @change_work: device change notification work @@ -31,6 +32,7 @@ struct zl3073x_dpll { u8 check_count; bool phase_monitor; struct dpll_device *dpll_dev; + dpll_tracker tracker; enum dpll_lock_status lock_status; struct list_head pins; struct work_struct change_work; diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethern= et/intel/ice/ice_dpll.c index 64b7b045ecd58..4eca62688d834 100644 --- a/drivers/net/ethernet/intel/ice/ice_dpll.c +++ b/drivers/net/ethernet/intel/ice/ice_dpll.c @@ -2814,7 +2814,7 @@ static void ice_dpll_release_pins(struct ice_dpll_pin= *pins, int count) int i; =20 for (i =3D 0; i < count; i++) - dpll_pin_put(pins[i].pin, NULL); + dpll_pin_put(pins[i].pin, &pins[i].tracker); } =20 /** @@ -2840,7 +2840,7 @@ ice_dpll_get_pins(struct ice_pf *pf, struct ice_dpll_= pin *pins, =20 for (i =3D 0; i < count; i++) { pins[i].pin =3D dpll_pin_get(clock_id, i + start_idx, THIS_MODULE, - &pins[i].prop, NULL); + &pins[i].prop, &pins[i].tracker); if (IS_ERR(pins[i].pin)) { ret =3D PTR_ERR(pins[i].pin); goto release_pins; @@ -2851,7 +2851,7 @@ ice_dpll_get_pins(struct ice_pf *pf, struct ice_dpll_= pin *pins, =20 release_pins: while (--i >=3D 0) - dpll_pin_put(pins[i].pin, NULL); + dpll_pin_put(pins[i].pin, &pins[i].tracker); return ret; } =20 @@ -3037,7 +3037,7 @@ static void ice_dpll_deinit_rclk_pin(struct ice_pf *p= f) if (WARN_ON_ONCE(!vsi || !vsi->netdev)) return; dpll_netdev_pin_clear(vsi->netdev); - dpll_pin_put(rclk->pin, NULL); + dpll_pin_put(rclk->pin, &rclk->tracker); } =20 /** @@ -3247,7 +3247,7 @@ ice_dpll_deinit_dpll(struct ice_pf *pf, struct ice_dp= ll *d, bool cgu) { if (cgu) dpll_device_unregister(d->dpll, d->ops, d); - dpll_device_put(d->dpll, NULL); + dpll_device_put(d->dpll, &d->tracker); } =20 /** @@ -3271,7 +3271,8 @@ ice_dpll_init_dpll(struct ice_pf *pf, struct ice_dpll= *d, bool cgu, u64 clock_id =3D pf->dplls.clock_id; int ret; =20 - d->dpll =3D dpll_device_get(clock_id, d->dpll_idx, THIS_MODULE, NULL); + d->dpll =3D dpll_device_get(clock_id, d->dpll_idx, THIS_MODULE, + &d->tracker); if (IS_ERR(d->dpll)) { ret =3D PTR_ERR(d->dpll); dev_err(ice_pf_to_dev(pf), @@ -3287,7 +3288,7 @@ ice_dpll_init_dpll(struct ice_pf *pf, struct ice_dpll= *d, bool cgu, ice_dpll_update_state(pf, d, true); ret =3D dpll_device_register(d->dpll, type, ops, d); if (ret) { - dpll_device_put(d->dpll, NULL); + dpll_device_put(d->dpll, &d->tracker); return ret; } d->ops =3D ops; diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.h b/drivers/net/ethern= et/intel/ice/ice_dpll.h index c0da03384ce91..63fac6510df6e 100644 --- a/drivers/net/ethernet/intel/ice/ice_dpll.h +++ b/drivers/net/ethernet/intel/ice/ice_dpll.h @@ -23,6 +23,7 @@ enum ice_dpll_pin_sw { /** ice_dpll_pin - store info about pins * @pin: dpll pin structure * @pf: pointer to pf, which has registered the dpll_pin + * @tracker: reference count tracker * @idx: ice pin private idx * @num_parents: hols number of parent pins * @parent_idx: hold indexes of parent pins @@ -37,6 +38,7 @@ enum ice_dpll_pin_sw { struct ice_dpll_pin { struct dpll_pin *pin; struct ice_pf *pf; + dpll_tracker tracker; u8 idx; u8 num_parents; u8 parent_idx[ICE_DPLL_RCLK_NUM_MAX]; @@ -58,6 +60,7 @@ struct ice_dpll_pin { /** ice_dpll - store info required for DPLL control * @dpll: pointer to dpll dev * @pf: pointer to pf, which has registered the dpll_device + * @tracker: reference count tracker * @dpll_idx: index of dpll on the NIC * @input_idx: currently selected input index * @prev_input_idx: previously selected input index @@ -76,6 +79,7 @@ struct ice_dpll_pin { struct ice_dpll { struct dpll_device *dpll; struct ice_pf *pf; + dpll_tracker tracker; u8 dpll_idx; u8 input_idx; u8 prev_input_idx; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/dpll.c b/drivers/net/e= thernet/mellanox/mlx5/core/dpll.c index 541d83e5d7183..3981dd81d4c17 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/dpll.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/dpll.c @@ -9,7 +9,9 @@ */ struct mlx5_dpll { struct dpll_device *dpll; + dpll_tracker dpll_tracker; struct dpll_pin *dpll_pin; + dpll_tracker pin_tracker; struct mlx5_core_dev *mdev; struct workqueue_struct *wq; struct delayed_work work; @@ -438,7 +440,8 @@ static int mlx5_dpll_probe(struct auxiliary_device *ade= v, auxiliary_set_drvdata(adev, mdpll); =20 /* Multiple mdev instances might share one DPLL device. */ - mdpll->dpll =3D dpll_device_get(clock_id, 0, THIS_MODULE, NULL); + mdpll->dpll =3D dpll_device_get(clock_id, 0, THIS_MODULE, + &mdpll->dpll_tracker); if (IS_ERR(mdpll->dpll)) { err =3D PTR_ERR(mdpll->dpll); goto err_free_mdpll; @@ -452,7 +455,7 @@ static int mlx5_dpll_probe(struct auxiliary_device *ade= v, /* Multiple mdev instances might share one DPLL pin. */ mdpll->dpll_pin =3D dpll_pin_get(clock_id, mlx5_get_dev_index(mdev), THIS_MODULE, &mlx5_dpll_pin_properties, - NULL); + &mdpll->pin_tracker); if (IS_ERR(mdpll->dpll_pin)) { err =3D PTR_ERR(mdpll->dpll_pin); goto err_unregister_dpll_device; @@ -480,11 +483,11 @@ static int mlx5_dpll_probe(struct auxiliary_device *a= dev, dpll_pin_unregister(mdpll->dpll, mdpll->dpll_pin, &mlx5_dpll_pins_ops, mdpll); err_put_dpll_pin: - dpll_pin_put(mdpll->dpll_pin, NULL); + dpll_pin_put(mdpll->dpll_pin, &mdpll->pin_tracker); err_unregister_dpll_device: dpll_device_unregister(mdpll->dpll, &mlx5_dpll_device_ops, mdpll); err_put_dpll_device: - dpll_device_put(mdpll->dpll, NULL); + dpll_device_put(mdpll->dpll, &mdpll->dpll_tracker); err_free_mdpll: kfree(mdpll); return err; @@ -500,9 +503,9 @@ static void mlx5_dpll_remove(struct auxiliary_device *a= dev) destroy_workqueue(mdpll->wq); dpll_pin_unregister(mdpll->dpll, mdpll->dpll_pin, &mlx5_dpll_pins_ops, mdpll); - dpll_pin_put(mdpll->dpll_pin, NULL); + dpll_pin_put(mdpll->dpll_pin, &mdpll->pin_tracker); dpll_device_unregister(mdpll->dpll, &mlx5_dpll_device_ops, mdpll); - dpll_device_put(mdpll->dpll, NULL); + dpll_device_put(mdpll->dpll, &mdpll->dpll_tracker); kfree(mdpll); =20 mlx5_dpll_synce_status_set(mdev, diff --git a/drivers/ptp/ptp_ocp.c b/drivers/ptp/ptp_ocp.c index f39b3966b3e8c..1b16a9c3d7fdc 100644 --- a/drivers/ptp/ptp_ocp.c +++ b/drivers/ptp/ptp_ocp.c @@ -285,6 +285,7 @@ struct ptp_ocp_sma_connector { u8 default_fcn; struct dpll_pin *dpll_pin; struct dpll_pin_properties dpll_prop; + dpll_tracker tracker; }; =20 struct ocp_attr_group { @@ -383,6 +384,7 @@ struct ptp_ocp { struct ptp_ocp_sma_connector sma[OCP_SMA_NUM]; const struct ocp_sma_op *sma_op; struct dpll_device *dpll; + dpll_tracker tracker; int signals_nr; int freq_in_nr; }; @@ -4788,7 +4790,7 @@ ptp_ocp_probe(struct pci_dev *pdev, const struct pci_= device_id *id) devlink_register(devlink); =20 clkid =3D pci_get_dsn(pdev); - bp->dpll =3D dpll_device_get(clkid, 0, THIS_MODULE, NULL); + bp->dpll =3D dpll_device_get(clkid, 0, THIS_MODULE, &bp->tracker); if (IS_ERR(bp->dpll)) { err =3D PTR_ERR(bp->dpll); dev_err(&pdev->dev, "dpll_device_alloc failed\n"); @@ -4801,7 +4803,8 @@ ptp_ocp_probe(struct pci_dev *pdev, const struct pci_= device_id *id) =20 for (i =3D 0; i < OCP_SMA_NUM; i++) { bp->sma[i].dpll_pin =3D dpll_pin_get(clkid, i, THIS_MODULE, - &bp->sma[i].dpll_prop, NULL); + &bp->sma[i].dpll_prop, + &bp->sma[i].tracker); if (IS_ERR(bp->sma[i].dpll_pin)) { err =3D PTR_ERR(bp->sma[i].dpll_pin); goto out_dpll; @@ -4810,7 +4813,7 @@ ptp_ocp_probe(struct pci_dev *pdev, const struct pci_= device_id *id) err =3D dpll_pin_register(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]); if (err) { - dpll_pin_put(bp->sma[i].dpll_pin, NULL); + dpll_pin_put(bp->sma[i].dpll_pin, &bp->sma[i].tracker); goto out_dpll; } } @@ -4820,9 +4823,9 @@ ptp_ocp_probe(struct pci_dev *pdev, const struct pci_= device_id *id) out_dpll: while (i--) { dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->= sma[i]); - dpll_pin_put(bp->sma[i].dpll_pin, NULL); + dpll_pin_put(bp->sma[i].dpll_pin, &bp->sma[i].tracker); } - dpll_device_put(bp->dpll, NULL); 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Tue, 03 Feb 2026 12:41:13 -0500 X-MC-Unique: ROusL4uKMu69wuAUMDd67g-1 X-Mimecast-MFC-AGG-ID: ROusL4uKMu69wuAUMDd67g_1770140470 Received: from mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.4]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id A18751956052; Tue, 3 Feb 2026 17:41:10 +0000 (UTC) Received: from p16v.luc.cera.cz (unknown [10.45.224.28]) by mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 1D1ED30001A7; Tue, 3 Feb 2026 17:41:02 +0000 (UTC) From: Ivan Vecera To: netdev@vger.kernel.org Cc: Arkadiusz Kubalewski , Aleksandr Loktionov , Grzegorz Nitka , Alexander Lobakin , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Jiri Pirko , Jonathan Lemon , Leon Romanovsky , Mark Bloch , Paolo Abeni , Prathosh Satish , Przemek Kitszel , Richard Cochran , Saeed Mahameed , Tariq Toukan , Tony Nguyen , Vadim Fedorenko , intel-wired-lan@lists.osuosl.org, linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org Subject: [PATCH net-next v5 9/9] ice: dpll: Support E825-C SyncE and dynamic pin discovery Date: Tue, 3 Feb 2026 18:40:02 +0100 Message-ID: <20260203174002.705176-10-ivecera@redhat.com> In-Reply-To: <20260203174002.705176-1-ivecera@redhat.com> References: <20260203174002.705176-1-ivecera@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Content-Type: text/plain; charset="utf-8" From: Arkadiusz Kubalewski Implement SyncE support for the E825-C Ethernet controller using the DPLL subsystem. Unlike E810, the E825-C architecture relies on platform firmware (ACPI) to describe connections between the NIC's recovered clock outputs and external DPLL inputs. Implement the following mechanisms to support this architecture: 1. Discovery Mechanism: The driver parses the 'dpll-pins' and 'dpll-pin nam= es' firmware properties to identify the external DPLL pins (parents) corresponding to its RCLK outputs ("rclk0", "rclk1"). It uses fwnode_dpll_pin_find() to locate these parent pins in the DPLL core. 2. Asynchronous Registration: Since the platform DPLL driver (e.g. zl3073x) may probe independently of the network driver, utilize the DPLL notifier chain The driver listens for DPLL_PIN_CREATED events to detect when the parent MUX pins become available, then registers its own Recovered Clock (RCLK) pins as children of those parents. 3. Hardware Configuration: Implement the specific register access logic for E825-C CGU (Clock Generation Unit) registers (R10, R11). This includes configuring the bypass MUXes and clock dividers required to drive SyncE signals. 4. Split Initialization: Refactor `ice_dpll_init()` to separate the static initialization path of E810 from the dynamic, firmware-driven path required for E825-C. Reviewed-by: Aleksandr Loktionov Co-developed-by: Ivan Vecera Signed-off-by: Ivan Vecera Co-developed-by: Grzegorz Nitka Signed-off-by: Grzegorz Nitka Signed-off-by: Arkadiusz Kubalewski --- v5: * fixed typo: 'DPL' -> 'DPLL' * fixed loop counter corruption in ice_dpll_rclk_update() v3: * DPLL init check in ice_ptp_link_change() * using completion for dpll initization to avoid races with DPLL notifier scheduled works * added parsing of dpll-pin-names and dpll-pins properties v2: * fixed error path in ice_dpll_init_pins_e825() * fixed misleading comment referring 'device tree' --- drivers/net/ethernet/intel/ice/ice_dpll.c | 745 +++++++++++++++++--- drivers/net/ethernet/intel/ice/ice_dpll.h | 26 + drivers/net/ethernet/intel/ice/ice_lib.c | 3 + drivers/net/ethernet/intel/ice/ice_ptp.c | 32 + drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 9 +- drivers/net/ethernet/intel/ice/ice_tspll.c | 217 ++++++ drivers/net/ethernet/intel/ice/ice_tspll.h | 13 +- drivers/net/ethernet/intel/ice/ice_type.h | 6 + 8 files changed, 959 insertions(+), 92 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethern= et/intel/ice/ice_dpll.c index 4eca62688d834..baf02512d041a 100644 --- a/drivers/net/ethernet/intel/ice/ice_dpll.c +++ b/drivers/net/ethernet/intel/ice/ice_dpll.c @@ -5,6 +5,7 @@ #include "ice_lib.h" #include "ice_trace.h" #include +#include =20 #define ICE_CGU_STATE_ACQ_ERR_THRESHOLD 50 #define ICE_DPLL_PIN_IDX_INVALID 0xff @@ -528,6 +529,94 @@ ice_dpll_pin_disable(struct ice_hw *hw, struct ice_dpl= l_pin *pin, return ret; } =20 +/** + * ice_dpll_pin_store_state - updates the state of pin in SW bookkeeping + * @pin: pointer to a pin + * @parent: parent pin index + * @state: pin state (connected or disconnected) + */ +static void +ice_dpll_pin_store_state(struct ice_dpll_pin *pin, int parent, bool state) +{ + pin->state[parent] =3D state ? DPLL_PIN_STATE_CONNECTED : + DPLL_PIN_STATE_DISCONNECTED; +} + +/** + * ice_dpll_rclk_update_e825c - updates the state of rclk pin on e825c dev= ice + * @pf: private board struct + * @pin: pointer to a pin + * + * Update struct holding pin states info, states are separate for each par= ent + * + * Context: Called under pf->dplls.lock + * Return: + * * 0 - OK + * * negative - error + */ +static int ice_dpll_rclk_update_e825c(struct ice_pf *pf, + struct ice_dpll_pin *pin) +{ + u8 rclk_bits; + int err; + u32 reg; + + if (pf->dplls.rclk.num_parents > ICE_SYNCE_CLK_NUM) + return -EINVAL; + + err =3D ice_read_cgu_reg(&pf->hw, ICE_CGU_R10, ®); + if (err) + return err; + + rclk_bits =3D FIELD_GET(ICE_CGU_R10_SYNCE_S_REF_CLK, reg); + ice_dpll_pin_store_state(pin, ICE_SYNCE_CLK0, rclk_bits =3D=3D + (pf->ptp.port.port_num + ICE_CGU_BYPASS_MUX_OFFSET_E825C)); + + err =3D ice_read_cgu_reg(&pf->hw, ICE_CGU_R11, ®); + if (err) + return err; + + rclk_bits =3D FIELD_GET(ICE_CGU_R11_SYNCE_S_BYP_CLK, reg); + ice_dpll_pin_store_state(pin, ICE_SYNCE_CLK1, rclk_bits =3D=3D + (pf->ptp.port.port_num + ICE_CGU_BYPASS_MUX_OFFSET_E825C)); + + return 0; +} + +/** + * ice_dpll_rclk_update - updates the state of rclk pin on a device + * @pf: private board struct + * @pin: pointer to a pin + * @port_num: port number + * + * Update struct holding pin states info, states are separate for each par= ent + * + * Context: Called under pf->dplls.lock + * Return: + * * 0 - OK + * * negative - error + */ +static int ice_dpll_rclk_update(struct ice_pf *pf, struct ice_dpll_pin *pi= n, + u8 port_num) +{ + int ret; + + for (u8 parent =3D 0; parent < pf->dplls.rclk.num_parents; parent++) { + u8 p =3D parent; + + ret =3D ice_aq_get_phy_rec_clk_out(&pf->hw, &p, &port_num, + &pin->flags[parent], NULL); + if (ret) + return ret; + + ice_dpll_pin_store_state(pin, parent, + ICE_AQC_GET_PHY_REC_CLK_OUT_OUT_EN & + pin->flags[parent]); + } + + return 0; +} + /** * ice_dpll_sw_pins_update - update status of all SW pins * @pf: private board struct @@ -668,22 +757,14 @@ ice_dpll_pin_state_update(struct ice_pf *pf, struct i= ce_dpll_pin *pin, } break; case ICE_DPLL_PIN_TYPE_RCLK_INPUT: - for (parent =3D 0; parent < pf->dplls.rclk.num_parents; - parent++) { - u8 p =3D parent; - - ret =3D ice_aq_get_phy_rec_clk_out(&pf->hw, &p, - &port_num, - &pin->flags[parent], - NULL); + if (pf->hw.mac_type =3D=3D ICE_MAC_GENERIC_3K_E825) { + ret =3D ice_dpll_rclk_update_e825c(pf, pin); + if (ret) + goto err; + } else { + ret =3D ice_dpll_rclk_update(pf, pin, port_num); if (ret) goto err; - if (ICE_AQC_GET_PHY_REC_CLK_OUT_OUT_EN & - pin->flags[parent]) - pin->state[parent] =3D DPLL_PIN_STATE_CONNECTED; - else - pin->state[parent] =3D - DPLL_PIN_STATE_DISCONNECTED; } break; case ICE_DPLL_PIN_TYPE_SOFTWARE: @@ -1842,6 +1923,40 @@ ice_dpll_phase_offset_get(const struct dpll_pin *pin= , void *pin_priv, return 0; } =20 +/** + * ice_dpll_synce_update_e825c - setting PHY recovered clock pins on e825c + * @hw: Pointer to the HW struct + * @ena: true if enable, false in disable + * @port_num: port number + * @output: output pin, we have two in E825C + * + * DPLL subsystem callback. Set proper signals to recover clock from port. + * + * Context: Called under pf->dplls.lock + * Return: + * * 0 - success + * * negative - error + */ +static int ice_dpll_synce_update_e825c(struct ice_hw *hw, bool ena, + u32 port_num, enum ice_synce_clk output) +{ + int err; + + /* configure the mux to deliver proper signal to DPLL from the MUX */ + err =3D ice_tspll_cfg_bypass_mux_e825c(hw, ena, port_num, output); + if (err) + return err; + + err =3D ice_tspll_cfg_synce_ethdiv_e825c(hw, output); + if (err) + return err; + + dev_dbg(ice_hw_to_dev(hw), "CLK_SYNCE%u recovered clock: pin %s\n", + output, str_enabled_disabled(ena)); + + return 0; +} + /** * ice_dpll_output_esync_set - callback for setting embedded sync * @pin: pointer to a pin @@ -2263,6 +2378,28 @@ ice_dpll_sw_input_ref_sync_get(const struct dpll_pin= *pin, void *pin_priv, state, extack); } =20 +static int +ice_dpll_pin_get_parent_num(struct ice_dpll_pin *pin, + const struct dpll_pin *parent) +{ + int i; + + for (i =3D 0; i < pin->num_parents; i++) + if (pin->pf->dplls.inputs[pin->parent_idx[i]].pin =3D=3D parent) + return i; + + return -ENOENT; +} + +static int +ice_dpll_pin_get_parent_idx(struct ice_dpll_pin *pin, + const struct dpll_pin *parent) +{ + int num =3D ice_dpll_pin_get_parent_num(pin, parent); + + return num < 0 ? num : pin->parent_idx[num]; +} + /** * ice_dpll_rclk_state_on_pin_set - set a state on rclk pin * @pin: pointer to a pin @@ -2286,35 +2423,45 @@ ice_dpll_rclk_state_on_pin_set(const struct dpll_pi= n *pin, void *pin_priv, enum dpll_pin_state state, struct netlink_ext_ack *extack) { - struct ice_dpll_pin *p =3D pin_priv, *parent =3D parent_pin_priv; bool enable =3D state =3D=3D DPLL_PIN_STATE_CONNECTED; + struct ice_dpll_pin *p =3D pin_priv; struct ice_pf *pf =3D p->pf; + struct ice_hw *hw; int ret =3D -EINVAL; - u32 hw_idx; + int hw_idx; + + hw =3D &pf->hw; =20 if (ice_dpll_is_reset(pf, extack)) return -EBUSY; =20 mutex_lock(&pf->dplls.lock); - hw_idx =3D parent->idx - pf->dplls.base_rclk_idx; - if (hw_idx >=3D pf->dplls.num_inputs) + hw_idx =3D ice_dpll_pin_get_parent_idx(p, parent_pin); + if (hw_idx < 0) goto unlock; + hw_idx -=3D pf->dplls.base_rclk_idx; =20 if ((enable && p->state[hw_idx] =3D=3D DPLL_PIN_STATE_CONNECTED) || (!enable && p->state[hw_idx] =3D=3D DPLL_PIN_STATE_DISCONNECTED)) { NL_SET_ERR_MSG_FMT(extack, "pin:%u state:%u on parent:%u already set", - p->idx, state, parent->idx); + p->idx, state, + ice_dpll_pin_get_parent_num(p, parent_pin)); goto unlock; } - ret =3D ice_aq_set_phy_rec_clk_out(&pf->hw, hw_idx, enable, - &p->freq); + + ret =3D hw->mac_type =3D=3D ICE_MAC_GENERIC_3K_E825 ? + ice_dpll_synce_update_e825c(hw, enable, + pf->ptp.port.port_num, + (enum ice_synce_clk)hw_idx) : + ice_aq_set_phy_rec_clk_out(hw, hw_idx, enable, &p->freq); if (ret) NL_SET_ERR_MSG_FMT(extack, "err:%d %s failed to set pin state:%u for pin:%u on parent:%u", ret, - libie_aq_str(pf->hw.adminq.sq_last_status), - state, p->idx, parent->idx); + libie_aq_str(hw->adminq.sq_last_status), + state, p->idx, + ice_dpll_pin_get_parent_num(p, parent_pin)); unlock: mutex_unlock(&pf->dplls.lock); =20 @@ -2344,17 +2491,17 @@ ice_dpll_rclk_state_on_pin_get(const struct dpll_pi= n *pin, void *pin_priv, enum dpll_pin_state *state, struct netlink_ext_ack *extack) { - struct ice_dpll_pin *p =3D pin_priv, *parent =3D parent_pin_priv; + struct ice_dpll_pin *p =3D pin_priv; struct ice_pf *pf =3D p->pf; int ret =3D -EINVAL; - u32 hw_idx; + int hw_idx; =20 if (ice_dpll_is_reset(pf, extack)) return -EBUSY; =20 mutex_lock(&pf->dplls.lock); - hw_idx =3D parent->idx - pf->dplls.base_rclk_idx; - if (hw_idx >=3D pf->dplls.num_inputs) + hw_idx =3D ice_dpll_pin_get_parent_idx(p, parent_pin); + if (hw_idx < 0) goto unlock; =20 ret =3D ice_dpll_pin_state_update(pf, p, ICE_DPLL_PIN_TYPE_RCLK_INPUT, @@ -2814,7 +2961,8 @@ static void ice_dpll_release_pins(struct ice_dpll_pin= *pins, int count) int i; =20 for (i =3D 0; i < count; i++) - dpll_pin_put(pins[i].pin, &pins[i].tracker); + if (!IS_ERR_OR_NULL(pins[i].pin)) + dpll_pin_put(pins[i].pin, &pins[i].tracker); } =20 /** @@ -2836,10 +2984,14 @@ static int ice_dpll_get_pins(struct ice_pf *pf, struct ice_dpll_pin *pins, int start_idx, int count, u64 clock_id) { + u32 pin_index; int i, ret; =20 for (i =3D 0; i < count; i++) { - pins[i].pin =3D dpll_pin_get(clock_id, i + start_idx, THIS_MODULE, + pin_index =3D start_idx; + if (start_idx !=3D DPLL_PIN_IDX_UNSPEC) + pin_index +=3D i; + pins[i].pin =3D dpll_pin_get(clock_id, pin_index, THIS_MODULE, &pins[i].prop, &pins[i].tracker); if (IS_ERR(pins[i].pin)) { ret =3D PTR_ERR(pins[i].pin); @@ -2944,6 +3096,7 @@ ice_dpll_register_pins(struct dpll_device *dpll, stru= ct ice_dpll_pin *pins, =20 /** * ice_dpll_deinit_direct_pins - deinitialize direct pins + * @pf: board private structure * @cgu: if cgu is present and controlled by this NIC * @pins: pointer to pins array * @count: number of pins @@ -2955,7 +3108,8 @@ ice_dpll_register_pins(struct dpll_device *dpll, stru= ct ice_dpll_pin *pins, * Release pins resources to the dpll subsystem. */ static void -ice_dpll_deinit_direct_pins(bool cgu, struct ice_dpll_pin *pins, int count, +ice_dpll_deinit_direct_pins(struct ice_pf *pf, bool cgu, + struct ice_dpll_pin *pins, int count, const struct dpll_pin_ops *ops, struct dpll_device *first, struct dpll_device *second) @@ -3024,14 +3178,14 @@ static void ice_dpll_deinit_rclk_pin(struct ice_pf = *pf) { struct ice_dpll_pin *rclk =3D &pf->dplls.rclk; struct ice_vsi *vsi =3D ice_get_main_vsi(pf); - struct dpll_pin *parent; + struct ice_dpll_pin *parent; int i; =20 for (i =3D 0; i < rclk->num_parents; i++) { - parent =3D pf->dplls.inputs[rclk->parent_idx[i]].pin; - if (!parent) + parent =3D &pf->dplls.inputs[rclk->parent_idx[i]]; + if (IS_ERR_OR_NULL(parent->pin)) continue; - dpll_pin_on_pin_unregister(parent, rclk->pin, + dpll_pin_on_pin_unregister(parent->pin, rclk->pin, &ice_dpll_rclk_ops, rclk); } if (WARN_ON_ONCE(!vsi || !vsi->netdev)) @@ -3040,60 +3194,213 @@ static void ice_dpll_deinit_rclk_pin(struct ice_pf= *pf) dpll_pin_put(rclk->pin, &rclk->tracker); } =20 +static bool ice_dpll_is_fwnode_pin(struct ice_dpll_pin *pin) +{ + return !IS_ERR_OR_NULL(pin->fwnode); +} + +static void ice_dpll_pin_notify_work(struct work_struct *work) +{ + struct ice_dpll_pin_work *w =3D container_of(work, + struct ice_dpll_pin_work, + work); + struct ice_dpll_pin *pin, *parent =3D w->pin; + struct ice_pf *pf =3D parent->pf; + int ret; + + wait_for_completion(&pf->dplls.dpll_init); + if (!test_bit(ICE_FLAG_DPLL, pf->flags)) + goto out; /* DPLL initialization failed */ + + switch (w->action) { + case DPLL_PIN_CREATED: + if (!IS_ERR_OR_NULL(parent->pin)) { + /* We have already our pin registered */ + goto out; + } + + /* Grab reference on fwnode pin */ + parent->pin =3D fwnode_dpll_pin_find(parent->fwnode, + &parent->tracker); + if (IS_ERR_OR_NULL(parent->pin)) { + dev_err(ice_pf_to_dev(pf), + "Cannot get fwnode pin reference\n"); + goto out; + } + + /* Register rclk pin */ + pin =3D &pf->dplls.rclk; + ret =3D dpll_pin_on_pin_register(parent->pin, pin->pin, + &ice_dpll_rclk_ops, pin); + if (ret) { + dev_err(ice_pf_to_dev(pf), + "Failed to register pin: %pe\n", ERR_PTR(ret)); + dpll_pin_put(parent->pin, &parent->tracker); + parent->pin =3D NULL; + goto out; + } + break; + case DPLL_PIN_DELETED: + if (IS_ERR_OR_NULL(parent->pin)) { + /* We have already our pin unregistered */ + goto out; + } + + /* Unregister rclk pin */ + pin =3D &pf->dplls.rclk; + dpll_pin_on_pin_unregister(parent->pin, pin->pin, + &ice_dpll_rclk_ops, pin); + + /* Drop fwnode pin reference */ + dpll_pin_put(parent->pin, &parent->tracker); + parent->pin =3D NULL; + break; + default: + break; + } +out: + kfree(w); +} + +static int ice_dpll_pin_notify(struct notifier_block *nb, unsigned long ac= tion, + void *data) +{ + struct ice_dpll_pin *pin =3D container_of(nb, struct ice_dpll_pin, nb); + struct dpll_pin_notifier_info *info =3D data; + struct ice_dpll_pin_work *work; + + if (action !=3D DPLL_PIN_CREATED && action !=3D DPLL_PIN_DELETED) + return NOTIFY_DONE; + + /* Check if the reported pin is this one */ + if (pin->fwnode !=3D info->fwnode) + return NOTIFY_DONE; /* Not this pin */ + + work =3D kzalloc(sizeof(*work), GFP_KERNEL); + if (!work) + return NOTIFY_DONE; + + INIT_WORK(&work->work, ice_dpll_pin_notify_work); + work->action =3D action; + work->pin =3D pin; + + queue_work(pin->pf->dplls.wq, &work->work); + + return NOTIFY_OK; +} + /** - * ice_dpll_init_rclk_pins - initialize recovered clock pin + * ice_dpll_init_pin_common - initialize pin * @pf: board private structure * @pin: pin to register * @start_idx: on which index shall allocation start in dpll subsystem * @ops: callback ops registered with the pins * - * Allocate resource for recovered clock pin in dpll subsystem. Register t= he - * pin with the parents it has in the info. Register pin with the pf's mai= n vsi - * netdev. + * Allocate resource for given pin in dpll subsystem. Register the pin with + * the parents it has in the info. * * Return: * * 0 - success * * negative - registration failure reason */ static int -ice_dpll_init_rclk_pins(struct ice_pf *pf, struct ice_dpll_pin *pin, - int start_idx, const struct dpll_pin_ops *ops) +ice_dpll_init_pin_common(struct ice_pf *pf, struct ice_dpll_pin *pin, + int start_idx, const struct dpll_pin_ops *ops) { - struct ice_vsi *vsi =3D ice_get_main_vsi(pf); - struct dpll_pin *parent; + struct ice_dpll_pin *parent; int ret, i; =20 - if (WARN_ON((!vsi || !vsi->netdev))) - return -EINVAL; - ret =3D ice_dpll_get_pins(pf, pin, start_idx, ICE_DPLL_RCLK_NUM_PER_PF, - pf->dplls.clock_id); + ret =3D ice_dpll_get_pins(pf, pin, start_idx, 1, pf->dplls.clock_id); if (ret) return ret; - for (i =3D 0; i < pf->dplls.rclk.num_parents; i++) { - parent =3D pf->dplls.inputs[pf->dplls.rclk.parent_idx[i]].pin; - if (!parent) { - ret =3D -ENODEV; - goto unregister_pins; + + for (i =3D 0; i < pin->num_parents; i++) { + parent =3D &pf->dplls.inputs[pin->parent_idx[i]]; + if (IS_ERR_OR_NULL(parent->pin)) { + if (!ice_dpll_is_fwnode_pin(parent)) { + ret =3D -ENODEV; + goto unregister_pins; + } + parent->pin =3D fwnode_dpll_pin_find(parent->fwnode, + &parent->tracker); + if (IS_ERR_OR_NULL(parent->pin)) { + dev_info(ice_pf_to_dev(pf), + "Mux pin not registered yet\n"); + continue; + } } - ret =3D dpll_pin_on_pin_register(parent, pf->dplls.rclk.pin, - ops, &pf->dplls.rclk); + ret =3D dpll_pin_on_pin_register(parent->pin, pin->pin, ops, pin); if (ret) goto unregister_pins; } - dpll_netdev_pin_set(vsi->netdev, pf->dplls.rclk.pin); =20 return 0; =20 unregister_pins: while (i) { - parent =3D pf->dplls.inputs[pf->dplls.rclk.parent_idx[--i]].pin; - dpll_pin_on_pin_unregister(parent, pf->dplls.rclk.pin, - &ice_dpll_rclk_ops, &pf->dplls.rclk); + parent =3D &pf->dplls.inputs[pin->parent_idx[--i]]; + if (IS_ERR_OR_NULL(parent->pin)) + continue; + dpll_pin_on_pin_unregister(parent->pin, pin->pin, ops, pin); } - ice_dpll_release_pins(pin, ICE_DPLL_RCLK_NUM_PER_PF); + ice_dpll_release_pins(pin, 1); + return ret; } =20 +/** + * ice_dpll_init_rclk_pin - initialize recovered clock pin + * @pf: board private structure + * @start_idx: on which index shall allocation start in dpll subsystem + * @ops: callback ops registered with the pins + * + * Allocate resource for recovered clock pin in dpll subsystem. Register t= he + * pin with the parents it has in the info. + * + * Return: + * * 0 - success + * * negative - registration failure reason + */ +static int +ice_dpll_init_rclk_pin(struct ice_pf *pf, int start_idx, + const struct dpll_pin_ops *ops) +{ + struct ice_vsi *vsi =3D ice_get_main_vsi(pf); + int ret; + + ret =3D ice_dpll_init_pin_common(pf, &pf->dplls.rclk, start_idx, ops); + if (ret) + return ret; + + dpll_netdev_pin_set(vsi->netdev, pf->dplls.rclk.pin); + + return 0; +} + +static void +ice_dpll_deinit_fwnode_pin(struct ice_dpll_pin *pin) +{ + unregister_dpll_notifier(&pin->nb); + flush_workqueue(pin->pf->dplls.wq); + if (!IS_ERR_OR_NULL(pin->pin)) { + dpll_pin_put(pin->pin, &pin->tracker); + pin->pin =3D NULL; + } + fwnode_handle_put(pin->fwnode); + pin->fwnode =3D NULL; +} + +static void +ice_dpll_deinit_fwnode_pins(struct ice_pf *pf, struct ice_dpll_pin *pins, + int start_idx) +{ + int i; + + for (i =3D 0; i < pf->dplls.rclk.num_parents; i++) + ice_dpll_deinit_fwnode_pin(&pins[start_idx + i]); + destroy_workqueue(pf->dplls.wq); +} + /** * ice_dpll_deinit_pins - deinitialize direct pins * @pf: board private structure @@ -3113,6 +3420,8 @@ static void ice_dpll_deinit_pins(struct ice_pf *pf, b= ool cgu) struct ice_dpll *dp =3D &d->pps; =20 ice_dpll_deinit_rclk_pin(pf); + if (pf->hw.mac_type =3D=3D ICE_MAC_GENERIC_3K_E825) + ice_dpll_deinit_fwnode_pins(pf, pf->dplls.inputs, 0); if (cgu) { ice_dpll_unregister_pins(dp->dpll, inputs, &ice_dpll_input_ops, num_inputs); @@ -3127,12 +3436,12 @@ static void ice_dpll_deinit_pins(struct ice_pf *pf,= bool cgu) &ice_dpll_output_ops, num_outputs); ice_dpll_release_pins(outputs, num_outputs); if (!pf->dplls.generic) { - ice_dpll_deinit_direct_pins(cgu, pf->dplls.ufl, + ice_dpll_deinit_direct_pins(pf, cgu, pf->dplls.ufl, ICE_DPLL_PIN_SW_NUM, &ice_dpll_pin_ufl_ops, pf->dplls.pps.dpll, pf->dplls.eec.dpll); - ice_dpll_deinit_direct_pins(cgu, pf->dplls.sma, + ice_dpll_deinit_direct_pins(pf, cgu, pf->dplls.sma, ICE_DPLL_PIN_SW_NUM, &ice_dpll_pin_sma_ops, pf->dplls.pps.dpll, @@ -3141,6 +3450,141 @@ static void ice_dpll_deinit_pins(struct ice_pf *pf,= bool cgu) } } =20 +static struct fwnode_handle * +ice_dpll_pin_node_get(struct ice_pf *pf, const char *name) +{ + struct fwnode_handle *fwnode =3D dev_fwnode(ice_pf_to_dev(pf)); + int index; + + index =3D fwnode_property_match_string(fwnode, "dpll-pin-names", name); + if (index < 0) + return ERR_PTR(-ENOENT); + + return fwnode_find_reference(fwnode, "dpll-pins", index); +} + +static int +ice_dpll_init_fwnode_pin(struct ice_dpll_pin *pin, const char *name) +{ + struct ice_pf *pf =3D pin->pf; + int ret; + + pin->fwnode =3D ice_dpll_pin_node_get(pf, name); + if (IS_ERR(pin->fwnode)) { + dev_err(ice_pf_to_dev(pf), + "Failed to find %s firmware node: %pe\n", name, + pin->fwnode); + pin->fwnode =3D NULL; + return -ENODEV; + } + + dev_dbg(ice_pf_to_dev(pf), "Found fwnode node for %s\n", name); + + pin->pin =3D fwnode_dpll_pin_find(pin->fwnode, &pin->tracker); + if (IS_ERR_OR_NULL(pin->pin)) { + dev_info(ice_pf_to_dev(pf), + "DPLL pin for %pfwp not registered yet\n", + pin->fwnode); + pin->pin =3D NULL; + } + + pin->nb.notifier_call =3D ice_dpll_pin_notify; + ret =3D register_dpll_notifier(&pin->nb); + if (ret) { + dev_err(ice_pf_to_dev(pf), + "Failed to subscribe for DPLL notifications\n"); + + if (!IS_ERR_OR_NULL(pin->pin)) { + dpll_pin_put(pin->pin, &pin->tracker); + pin->pin =3D NULL; + } + fwnode_handle_put(pin->fwnode); + pin->fwnode =3D NULL; + + return ret; + } + + return ret; +} + +/** + * ice_dpll_init_fwnode_pins - initialize pins from device tree + * @pf: board private structure + * @pins: pointer to pins array + * @start_idx: starting index for pins + * @count: number of pins to initialize + * + * Initialize input pins for E825 RCLK support. The parent pins (rclk0, rc= lk1) + * are expected to be defined by the system firmware (ACPI). This function + * allocates them in the dpll subsystem and stores their indices for later + * registration with the rclk pin. + * + * Return: + * * 0 - success + * * negative - initialization failure reason + */ +static int +ice_dpll_init_fwnode_pins(struct ice_pf *pf, struct ice_dpll_pin *pins, + int start_idx) +{ + char pin_name[8]; + int i, ret; + + pf->dplls.wq =3D create_singlethread_workqueue("ice_dpll_wq"); + if (!pf->dplls.wq) + return -ENOMEM; + + for (i =3D 0; i < pf->dplls.rclk.num_parents; i++) { + pins[start_idx + i].pf =3D pf; + snprintf(pin_name, sizeof(pin_name), "rclk%u", i); + ret =3D ice_dpll_init_fwnode_pin(&pins[start_idx + i], pin_name); + if (ret) + goto error; + } + + return 0; +error: + while (i--) + ice_dpll_deinit_fwnode_pin(&pins[start_idx + i]); + + destroy_workqueue(pf->dplls.wq); + + return ret; +} + +/** + * ice_dpll_init_pins_e825 - init pins and register pins with a dplls + * @pf: board private structure + * @cgu: if cgu is present and controlled by this NIC + * + * Initialize directly connected pf's pins within pf's dplls in a Linux dp= ll + * subsystem. + * + * Return: + * * 0 - success + * * negative - initialization failure reason + */ +static int ice_dpll_init_pins_e825(struct ice_pf *pf) +{ + int ret; + + ret =3D ice_dpll_init_fwnode_pins(pf, pf->dplls.inputs, 0); + if (ret) + return ret; + + ret =3D ice_dpll_init_rclk_pin(pf, DPLL_PIN_IDX_UNSPEC, + &ice_dpll_rclk_ops); + if (ret) { + /* Inform DPLL notifier works that DPLL init was finished + * unsuccessfully (ICE_DPLL_FLAG not set). + */ + complete_all(&pf->dplls.dpll_init); + ice_dpll_deinit_fwnode_pins(pf, pf->dplls.inputs, 0); + } + + return ret; +} + /** * ice_dpll_init_pins - init pins and register pins with a dplls * @pf: board private structure @@ -3155,21 +3599,24 @@ static void ice_dpll_deinit_pins(struct ice_pf *pf,= bool cgu) */ static int ice_dpll_init_pins(struct ice_pf *pf, bool cgu) { + const struct dpll_pin_ops *output_ops; + const struct dpll_pin_ops *input_ops; int ret, count; =20 + input_ops =3D &ice_dpll_input_ops; + output_ops =3D &ice_dpll_output_ops; + ret =3D ice_dpll_init_direct_pins(pf, cgu, pf->dplls.inputs, 0, - pf->dplls.num_inputs, - &ice_dpll_input_ops, - pf->dplls.eec.dpll, pf->dplls.pps.dpll); + pf->dplls.num_inputs, input_ops, + pf->dplls.eec.dpll, + pf->dplls.pps.dpll); if (ret) return ret; count =3D pf->dplls.num_inputs; if (cgu) { ret =3D ice_dpll_init_direct_pins(pf, cgu, pf->dplls.outputs, - count, - pf->dplls.num_outputs, - &ice_dpll_output_ops, - pf->dplls.eec.dpll, + count, pf->dplls.num_outputs, + output_ops, pf->dplls.eec.dpll, pf->dplls.pps.dpll); if (ret) goto deinit_inputs; @@ -3205,30 +3652,30 @@ static int ice_dpll_init_pins(struct ice_pf *pf, bo= ol cgu) } else { count +=3D pf->dplls.num_outputs + 2 * ICE_DPLL_PIN_SW_NUM; } - ret =3D ice_dpll_init_rclk_pins(pf, &pf->dplls.rclk, count + pf->hw.pf_id, - &ice_dpll_rclk_ops); + + ret =3D ice_dpll_init_rclk_pin(pf, count + pf->ptp.port.port_num, + &ice_dpll_rclk_ops); if (ret) goto deinit_ufl; =20 return 0; deinit_ufl: - ice_dpll_deinit_direct_pins(cgu, pf->dplls.ufl, - ICE_DPLL_PIN_SW_NUM, - &ice_dpll_pin_ufl_ops, - pf->dplls.pps.dpll, pf->dplls.eec.dpll); + ice_dpll_deinit_direct_pins(pf, cgu, pf->dplls.ufl, ICE_DPLL_PIN_SW_NUM, + &ice_dpll_pin_ufl_ops, pf->dplls.pps.dpll, + pf->dplls.eec.dpll); deinit_sma: - ice_dpll_deinit_direct_pins(cgu, pf->dplls.sma, - ICE_DPLL_PIN_SW_NUM, - &ice_dpll_pin_sma_ops, - pf->dplls.pps.dpll, pf->dplls.eec.dpll); + ice_dpll_deinit_direct_pins(pf, cgu, pf->dplls.sma, ICE_DPLL_PIN_SW_NUM, + &ice_dpll_pin_sma_ops, pf->dplls.pps.dpll, + pf->dplls.eec.dpll); deinit_outputs: - ice_dpll_deinit_direct_pins(cgu, pf->dplls.outputs, + ice_dpll_deinit_direct_pins(pf, cgu, pf->dplls.outputs, pf->dplls.num_outputs, - &ice_dpll_output_ops, pf->dplls.pps.dpll, + output_ops, pf->dplls.pps.dpll, pf->dplls.eec.dpll); deinit_inputs: - ice_dpll_deinit_direct_pins(cgu, pf->dplls.inputs, pf->dplls.num_inputs, - &ice_dpll_input_ops, pf->dplls.pps.dpll, + ice_dpll_deinit_direct_pins(pf, cgu, pf->dplls.inputs, + pf->dplls.num_inputs, + input_ops, pf->dplls.pps.dpll, pf->dplls.eec.dpll); return ret; } @@ -3239,8 +3686,8 @@ static int ice_dpll_init_pins(struct ice_pf *pf, bool= cgu) * @d: pointer to ice_dpll * @cgu: if cgu is present and controlled by this NIC * - * If cgu is owned unregister the dpll from dpll subsystem. - * Release resources of dpll device from dpll subsystem. + * If cgu is owned, unregister the DPLL from DPLL subsystem. + * Release resources of DPLL device from DPLL subsystem. */ static void ice_dpll_deinit_dpll(struct ice_pf *pf, struct ice_dpll *d, bool cgu) @@ -3257,8 +3704,8 @@ ice_dpll_deinit_dpll(struct ice_pf *pf, struct ice_dp= ll *d, bool cgu) * @cgu: if cgu is present and controlled by this NIC * @type: type of dpll being initialized * - * Allocate dpll instance for this board in dpll subsystem, if cgu is cont= rolled - * by this NIC, register dpll with the callback ops. + * Allocate DPLL instance for this board in dpll subsystem, if cgu is cont= rolled + * by this NIC, register DPLL with the callback ops. * * Return: * * 0 - success @@ -3289,6 +3736,7 @@ ice_dpll_init_dpll(struct ice_pf *pf, struct ice_dpll= *d, bool cgu, ret =3D dpll_device_register(d->dpll, type, ops, d); if (ret) { dpll_device_put(d->dpll, &d->tracker); + d->dpll =3D NULL; return ret; } d->ops =3D ops; @@ -3506,6 +3954,26 @@ ice_dpll_init_info_direct_pins(struct ice_pf *pf, return ret; } =20 +/** + * ice_dpll_init_info_pin_on_pin_e825c - initializes rclk pin information + * @pf: board private structure + * + * Init information for rclk pin, cache them in pf->dplls.rclk. + * + * Return: + * * 0 - success + */ +static int ice_dpll_init_info_pin_on_pin_e825c(struct ice_pf *pf) +{ + struct ice_dpll_pin *rclk_pin =3D &pf->dplls.rclk; + + rclk_pin->prop.type =3D DPLL_PIN_TYPE_SYNCE_ETH_PORT; + rclk_pin->prop.capabilities |=3D DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE; + rclk_pin->pf =3D pf; + + return 0; +} + /** * ice_dpll_init_info_rclk_pin - initializes rclk pin information * @pf: board private structure @@ -3632,7 +4100,10 @@ ice_dpll_init_pins_info(struct ice_pf *pf, enum ice_= dpll_pin_type pin_type) case ICE_DPLL_PIN_TYPE_OUTPUT: return ice_dpll_init_info_direct_pins(pf, pin_type); case ICE_DPLL_PIN_TYPE_RCLK_INPUT: - return ice_dpll_init_info_rclk_pin(pf); + if (pf->hw.mac_type =3D=3D ICE_MAC_GENERIC_3K_E825) + return ice_dpll_init_info_pin_on_pin_e825c(pf); + else + return ice_dpll_init_info_rclk_pin(pf); case ICE_DPLL_PIN_TYPE_SOFTWARE: return ice_dpll_init_info_sw_pins(pf); default: @@ -3654,6 +4125,50 @@ static void ice_dpll_deinit_info(struct ice_pf *pf) kfree(pf->dplls.pps.input_prio); } =20 +/** + * ice_dpll_init_info_e825c - prepare pf's dpll information structure for = e825c + * device + * @pf: board private structure + * + * Acquire (from HW) and set basic DPLL information (on pf->dplls struct). + * + * Return: + * * 0 - success + * * negative - init failure reason + */ +static int ice_dpll_init_info_e825c(struct ice_pf *pf) +{ + struct ice_dplls *d =3D &pf->dplls; + int ret =3D 0; + int i; + + d->clock_id =3D ice_generate_clock_id(pf); + d->num_inputs =3D ICE_SYNCE_CLK_NUM; + + d->inputs =3D kcalloc(d->num_inputs, sizeof(*d->inputs), GFP_KERNEL); + if (!d->inputs) + return -ENOMEM; + + ret =3D ice_get_cgu_rclk_pin_info(&pf->hw, &d->base_rclk_idx, + &pf->dplls.rclk.num_parents); + if (ret) + goto deinit_info; + + for (i =3D 0; i < pf->dplls.rclk.num_parents; i++) + pf->dplls.rclk.parent_idx[i] =3D d->base_rclk_idx + i; + + ret =3D ice_dpll_init_pins_info(pf, ICE_DPLL_PIN_TYPE_RCLK_INPUT); + if (ret) + goto deinit_info; + dev_dbg(ice_pf_to_dev(pf), + "%s - success, inputs: %u, outputs: %u, rclk-parents: %u\n", + __func__, d->num_inputs, d->num_outputs, d->rclk.num_parents); + return 0; +deinit_info: + ice_dpll_deinit_info(pf); + return ret; +} + /** * ice_dpll_init_info - prepare pf's dpll information structure * @pf: board private structure @@ -3773,14 +4288,16 @@ void ice_dpll_deinit(struct ice_pf *pf) ice_dpll_deinit_worker(pf); =20 ice_dpll_deinit_pins(pf, cgu); - ice_dpll_deinit_dpll(pf, &pf->dplls.pps, cgu); - ice_dpll_deinit_dpll(pf, &pf->dplls.eec, cgu); + if (!IS_ERR_OR_NULL(pf->dplls.pps.dpll)) + ice_dpll_deinit_dpll(pf, &pf->dplls.pps, cgu); + if (!IS_ERR_OR_NULL(pf->dplls.eec.dpll)) + ice_dpll_deinit_dpll(pf, &pf->dplls.eec, cgu); ice_dpll_deinit_info(pf); mutex_destroy(&pf->dplls.lock); } =20 /** - * ice_dpll_init - initialize support for dpll subsystem + * ice_dpll_init_e825 - initialize support for dpll subsystem * @pf: board private structure * * Set up the device dplls, register them and pins connected within Linux = dpll @@ -3789,7 +4306,43 @@ void ice_dpll_deinit(struct ice_pf *pf) * * Context: Initializes pf->dplls.lock mutex. */ -void ice_dpll_init(struct ice_pf *pf) +static void ice_dpll_init_e825(struct ice_pf *pf) +{ + struct ice_dplls *d =3D &pf->dplls; + int err; + + mutex_init(&d->lock); + init_completion(&d->dpll_init); + + err =3D ice_dpll_init_info_e825c(pf); + if (err) + goto err_exit; + err =3D ice_dpll_init_pins_e825(pf); + if (err) + goto deinit_info; + set_bit(ICE_FLAG_DPLL, pf->flags); + complete_all(&d->dpll_init); + + return; + +deinit_info: + ice_dpll_deinit_info(pf); +err_exit: + mutex_destroy(&d->lock); + dev_warn(ice_pf_to_dev(pf), "DPLLs init failure err:%d\n", err); +} + +/** + * ice_dpll_init_e810 - initialize support for dpll subsystem + * @pf: board private structure + * + * Set up the device dplls, register them and pins connected within Linux = dpll + * subsystem. Allow userspace to obtain state of DPLL and handling of DPLL + * configuration requests. + * + * Context: Initializes pf->dplls.lock mutex. + */ +static void ice_dpll_init_e810(struct ice_pf *pf) { bool cgu =3D ice_is_feature_supported(pf, ICE_F_CGU); struct ice_dplls *d =3D &pf->dplls; @@ -3829,3 +4382,15 @@ void ice_dpll_init(struct ice_pf *pf) mutex_destroy(&d->lock); dev_warn(ice_pf_to_dev(pf), "DPLLs init failure err:%d\n", err); } + +void ice_dpll_init(struct ice_pf *pf) +{ + switch (pf->hw.mac_type) { + case ICE_MAC_GENERIC_3K_E825: + ice_dpll_init_e825(pf); + break; + default: + ice_dpll_init_e810(pf); + break; + } +} diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.h b/drivers/net/ethern= et/intel/ice/ice_dpll.h index 63fac6510df6e..ae42cdea0ee14 100644 --- a/drivers/net/ethernet/intel/ice/ice_dpll.h +++ b/drivers/net/ethernet/intel/ice/ice_dpll.h @@ -20,6 +20,12 @@ enum ice_dpll_pin_sw { ICE_DPLL_PIN_SW_NUM }; =20 +struct ice_dpll_pin_work { + struct work_struct work; + unsigned long action; + struct ice_dpll_pin *pin; +}; + /** ice_dpll_pin - store info about pins * @pin: dpll pin structure * @pf: pointer to pf, which has registered the dpll_pin @@ -39,6 +45,8 @@ struct ice_dpll_pin { struct dpll_pin *pin; struct ice_pf *pf; dpll_tracker tracker; + struct fwnode_handle *fwnode; + struct notifier_block nb; u8 idx; u8 num_parents; u8 parent_idx[ICE_DPLL_RCLK_NUM_MAX]; @@ -118,7 +126,9 @@ struct ice_dpll { struct ice_dplls { struct kthread_worker *kworker; struct kthread_delayed_work work; + struct workqueue_struct *wq; struct mutex lock; + struct completion dpll_init; struct ice_dpll eec; struct ice_dpll pps; struct ice_dpll_pin *inputs; @@ -147,3 +157,19 @@ static inline void ice_dpll_deinit(struct ice_pf *pf) = { } #endif =20 #endif + +#define ICE_CGU_R10 0x28 +#define ICE_CGU_R10_SYNCE_CLKO_SEL GENMASK(8, 5) +#define ICE_CGU_R10_SYNCE_CLKODIV_M1 GENMASK(13, 9) +#define ICE_CGU_R10_SYNCE_CLKODIV_LOAD BIT(14) +#define ICE_CGU_R10_SYNCE_DCK_RST BIT(15) +#define ICE_CGU_R10_SYNCE_ETHCLKO_SEL GENMASK(18, 16) +#define ICE_CGU_R10_SYNCE_ETHDIV_M1 GENMASK(23, 19) +#define ICE_CGU_R10_SYNCE_ETHDIV_LOAD BIT(24) +#define ICE_CGU_R10_SYNCE_DCK2_RST BIT(25) +#define ICE_CGU_R10_SYNCE_S_REF_CLK GENMASK(31, 27) + +#define ICE_CGU_R11 0x2C +#define ICE_CGU_R11_SYNCE_S_BYP_CLK GENMASK(6, 1) + +#define ICE_CGU_BYPASS_MUX_OFFSET_E825C 3 diff --git a/drivers/net/ethernet/intel/ice/ice_lib.c b/drivers/net/etherne= t/intel/ice/ice_lib.c index 2522ebdea9139..d921269e1fe71 100644 --- a/drivers/net/ethernet/intel/ice/ice_lib.c +++ b/drivers/net/ethernet/intel/ice/ice_lib.c @@ -3989,6 +3989,9 @@ void ice_init_feature_support(struct ice_pf *pf) break; } =20 + if (pf->hw.mac_type =3D=3D ICE_MAC_GENERIC_3K_E825) + ice_set_feature_support(pf, ICE_F_PHY_RCLK); + if (pf->hw.mac_type =3D=3D ICE_MAC_E830) { ice_set_feature_support(pf, ICE_F_MBX_LIMIT); ice_set_feature_support(pf, ICE_F_GCS); diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/etherne= t/intel/ice/ice_ptp.c index 4c8d20f2d2c0a..1d26be58e29a0 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp.c @@ -1341,6 +1341,38 @@ void ice_ptp_link_change(struct ice_pf *pf, bool lin= kup) if (pf->hw.reset_ongoing) return; =20 + if (hw->mac_type =3D=3D ICE_MAC_GENERIC_3K_E825) { + int pin, err; + + if (!test_bit(ICE_FLAG_DPLL, pf->flags)) + return; + + mutex_lock(&pf->dplls.lock); + for (pin =3D 0; pin < ICE_SYNCE_CLK_NUM; pin++) { + enum ice_synce_clk clk_pin; + bool active; + u8 port_num; + + port_num =3D ptp_port->port_num; + clk_pin =3D (enum ice_synce_clk)pin; + err =3D ice_tspll_bypass_mux_active_e825c(hw, + port_num, + &active, + clk_pin); + if (WARN_ON_ONCE(err)) { + mutex_unlock(&pf->dplls.lock); + return; + } + + err =3D ice_tspll_cfg_synce_ethdiv_e825c(hw, clk_pin); + if (active && WARN_ON_ONCE(err)) { + mutex_unlock(&pf->dplls.lock); + return; + } + } + mutex_unlock(&pf->dplls.lock); + } + switch (hw->mac_type) { case ICE_MAC_E810: case ICE_MAC_E830: diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethe= rnet/intel/ice/ice_ptp_hw.c index 35680dbe4a7f7..61c0a0d93ea89 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c @@ -5903,7 +5903,14 @@ int ice_get_cgu_rclk_pin_info(struct ice_hw *hw, u8 = *base_idx, u8 *pin_num) *base_idx =3D SI_REF1P; else ret =3D -ENODEV; - + break; + case ICE_DEV_ID_E825C_BACKPLANE: + case ICE_DEV_ID_E825C_QSFP: + case ICE_DEV_ID_E825C_SFP: + case ICE_DEV_ID_E825C_SGMII: + *pin_num =3D ICE_SYNCE_CLK_NUM; + *base_idx =3D 0; + ret =3D 0; break; default: ret =3D -ENODEV; diff --git a/drivers/net/ethernet/intel/ice/ice_tspll.c b/drivers/net/ether= net/intel/ice/ice_tspll.c index 66320a4ab86fd..fd4b58eb9bc00 100644 --- a/drivers/net/ethernet/intel/ice/ice_tspll.c +++ b/drivers/net/ethernet/intel/ice/ice_tspll.c @@ -624,3 +624,220 @@ int ice_tspll_init(struct ice_hw *hw) =20 return err; } + +/** + * ice_tspll_bypass_mux_active_e825c - check if the given port is set acti= ve + * @hw: Pointer to the HW struct + * @port: Number of the port + * @active: Output flag showing if port is active + * @output: Output pin, we have two in E825C + * + * Check if given port is selected as recovered clock source for given out= put. + * + * Return: + * * 0 - success + * * negative - error + */ +int ice_tspll_bypass_mux_active_e825c(struct ice_hw *hw, u8 port, bool *ac= tive, + enum ice_synce_clk output) +{ + u8 active_clk; + u32 val; + int err; + + switch (output) { + case ICE_SYNCE_CLK0: + err =3D ice_read_cgu_reg(hw, ICE_CGU_R10, &val); + if (err) + return err; + active_clk =3D FIELD_GET(ICE_CGU_R10_SYNCE_S_REF_CLK, val); + break; + case ICE_SYNCE_CLK1: + err =3D ice_read_cgu_reg(hw, ICE_CGU_R11, &val); + if (err) + return err; + active_clk =3D FIELD_GET(ICE_CGU_R11_SYNCE_S_BYP_CLK, val); + break; + default: + return -EINVAL; + } + + if (active_clk =3D=3D port % hw->ptp.ports_per_phy + + ICE_CGU_BYPASS_MUX_OFFSET_E825C) + *active =3D true; + else + *active =3D false; + + return 0; +} + +/** + * ice_tspll_cfg_bypass_mux_e825c - configure reference clock mux + * @hw: Pointer to the HW struct + * @ena: true to enable the reference, false if disable + * @port_num: Number of the port + * @output: Output pin, we have two in E825C + * + * Set reference clock source and output clock selection. + * + * Context: Called under pf->dplls.lock + * Return: + * * 0 - success + * * negative - error + */ +int ice_tspll_cfg_bypass_mux_e825c(struct ice_hw *hw, bool ena, u32 port_n= um, + enum ice_synce_clk output) +{ + u8 first_mux; + int err; + u32 r10; + + err =3D ice_read_cgu_reg(hw, ICE_CGU_R10, &r10); + if (err) + return err; + + if (!ena) + first_mux =3D ICE_CGU_NET_REF_CLK0; + else + first_mux =3D port_num + ICE_CGU_BYPASS_MUX_OFFSET_E825C; + + r10 &=3D ~(ICE_CGU_R10_SYNCE_DCK_RST | ICE_CGU_R10_SYNCE_DCK2_RST); + + switch (output) { + case ICE_SYNCE_CLK0: + r10 &=3D ~(ICE_CGU_R10_SYNCE_ETHCLKO_SEL | + ICE_CGU_R10_SYNCE_ETHDIV_LOAD | + ICE_CGU_R10_SYNCE_S_REF_CLK); + r10 |=3D FIELD_PREP(ICE_CGU_R10_SYNCE_S_REF_CLK, first_mux); + r10 |=3D FIELD_PREP(ICE_CGU_R10_SYNCE_ETHCLKO_SEL, + ICE_CGU_REF_CLK_BYP0_DIV); + break; + case ICE_SYNCE_CLK1: + { + u32 val; + + err =3D ice_read_cgu_reg(hw, ICE_CGU_R11, &val); + if (err) + return err; + val &=3D ~ICE_CGU_R11_SYNCE_S_BYP_CLK; + val |=3D FIELD_PREP(ICE_CGU_R11_SYNCE_S_BYP_CLK, first_mux); + err =3D ice_write_cgu_reg(hw, ICE_CGU_R11, val); + if (err) + return err; + r10 &=3D ~(ICE_CGU_R10_SYNCE_CLKODIV_LOAD | + ICE_CGU_R10_SYNCE_CLKO_SEL); + r10 |=3D FIELD_PREP(ICE_CGU_R10_SYNCE_CLKO_SEL, + ICE_CGU_REF_CLK_BYP1_DIV); + break; + } + default: + return -EINVAL; + } + + err =3D ice_write_cgu_reg(hw, ICE_CGU_R10, r10); + if (err) + return err; + + return 0; +} + +/** + * ice_tspll_get_div_e825c - get the divider for the given speed + * @link_speed: link speed of the port + * @divider: output value, calculated divider + * + * Get CGU divider value based on the link speed. + * + * Return: + * * 0 - success + * * negative - error + */ +static int ice_tspll_get_div_e825c(u16 link_speed, unsigned int *divider) +{ + switch (link_speed) { + case ICE_AQ_LINK_SPEED_100GB: + case ICE_AQ_LINK_SPEED_50GB: + case ICE_AQ_LINK_SPEED_25GB: + *divider =3D 10; + break; + case ICE_AQ_LINK_SPEED_40GB: + case ICE_AQ_LINK_SPEED_10GB: + *divider =3D 4; + break; + case ICE_AQ_LINK_SPEED_5GB: + case ICE_AQ_LINK_SPEED_2500MB: + case ICE_AQ_LINK_SPEED_1000MB: + *divider =3D 2; + break; + case ICE_AQ_LINK_SPEED_100MB: + *divider =3D 1; + break; + default: + return -EOPNOTSUPP; + } + + return 0; +} + +/** + * ice_tspll_cfg_synce_ethdiv_e825c - set the divider on the mux + * @hw: Pointer to the HW struct + * @output: Output pin, we have two in E825C + * + * Set the correct CGU divider for RCLKA or RCLKB. + * + * Context: Called under pf->dplls.lock + * Return: + * * 0 - success + * * negative - error + */ +int ice_tspll_cfg_synce_ethdiv_e825c(struct ice_hw *hw, + enum ice_synce_clk output) +{ + unsigned int divider; + u16 link_speed; + u32 val; + int err; + + link_speed =3D hw->port_info->phy.link_info.link_speed; + if (!link_speed) + return 0; + + err =3D ice_tspll_get_div_e825c(link_speed, ÷r); + if (err) + return err; + + err =3D ice_read_cgu_reg(hw, ICE_CGU_R10, &val); + if (err) + return err; + + /* programmable divider value (from 2 to 16) minus 1 for ETHCLKOUT */ + switch (output) { + case ICE_SYNCE_CLK0: + val &=3D ~(ICE_CGU_R10_SYNCE_ETHDIV_M1 | + ICE_CGU_R10_SYNCE_ETHDIV_LOAD); + val |=3D FIELD_PREP(ICE_CGU_R10_SYNCE_ETHDIV_M1, divider - 1); + err =3D ice_write_cgu_reg(hw, ICE_CGU_R10, val); + if (err) + return err; + val |=3D ICE_CGU_R10_SYNCE_ETHDIV_LOAD; + break; + case ICE_SYNCE_CLK1: + val &=3D ~(ICE_CGU_R10_SYNCE_CLKODIV_M1 | + ICE_CGU_R10_SYNCE_CLKODIV_LOAD); + val |=3D FIELD_PREP(ICE_CGU_R10_SYNCE_CLKODIV_M1, divider - 1); + err =3D ice_write_cgu_reg(hw, ICE_CGU_R10, val); + if (err) + return err; + val |=3D ICE_CGU_R10_SYNCE_CLKODIV_LOAD; + break; + default: + return -EINVAL; + } + + err =3D ice_write_cgu_reg(hw, ICE_CGU_R10, val); + if (err) + return err; + + return 0; +} diff --git a/drivers/net/ethernet/intel/ice/ice_tspll.h b/drivers/net/ether= net/intel/ice/ice_tspll.h index c0b1232cc07c3..d650867004d1f 100644 --- a/drivers/net/ethernet/intel/ice/ice_tspll.h +++ b/drivers/net/ethernet/intel/ice/ice_tspll.h @@ -21,11 +21,22 @@ struct ice_tspll_params_e82x { u32 frac_n_div; }; =20 +#define ICE_CGU_NET_REF_CLK0 0x0 +#define ICE_CGU_REF_CLK_BYP0 0x5 +#define ICE_CGU_REF_CLK_BYP0_DIV 0x0 +#define ICE_CGU_REF_CLK_BYP1 0x4 +#define ICE_CGU_REF_CLK_BYP1_DIV 0x1 + #define ICE_TSPLL_CK_REFCLKFREQ_E825 0x1F #define ICE_TSPLL_NDIVRATIO_E825 5 #define ICE_TSPLL_FBDIV_INTGR_E825 256 =20 int ice_tspll_cfg_pps_out_e825c(struct ice_hw *hw, bool enable); int ice_tspll_init(struct ice_hw *hw); - +int ice_tspll_bypass_mux_active_e825c(struct ice_hw *hw, u8 port, bool *ac= tive, + enum ice_synce_clk output); +int ice_tspll_cfg_bypass_mux_e825c(struct ice_hw *hw, bool ena, u32 port_n= um, + enum ice_synce_clk output); +int ice_tspll_cfg_synce_ethdiv_e825c(struct ice_hw *hw, + enum ice_synce_clk output); #endif /* _ICE_TSPLL_H_ */ diff --git a/drivers/net/ethernet/intel/ice/ice_type.h b/drivers/net/ethern= et/intel/ice/ice_type.h index 6a2ec8389a8f3..1e82f4c40b326 100644 --- a/drivers/net/ethernet/intel/ice/ice_type.h +++ b/drivers/net/ethernet/intel/ice/ice_type.h @@ -349,6 +349,12 @@ enum ice_clk_src { NUM_ICE_CLK_SRC }; =20 +enum ice_synce_clk { + ICE_SYNCE_CLK0, + ICE_SYNCE_CLK1, + ICE_SYNCE_CLK_NUM +}; + struct ice_ts_func_info { /* Function specific info */ enum ice_tspll_freq time_ref; --=20 2.52.0