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Tue, 03 Feb 2026 05:10:54 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Linus Walleij Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 05/10] pinctrl: renesas: rzg2l: Add OEN support for RZ/G3L Date: Tue, 3 Feb 2026 13:10:28 +0000 Message-ID: <20260203131048.421708-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260203131048.421708-1-biju.das.jz@bp.renesas.com> References: <20260203131048.421708-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add support for configuring the ETH_MODE register on the RZ/G3L SoC to enable output-enable control for specific pins. On this SoC, certain pins such as P{B,E}1_ISO need to support switching between input and output modes depending on the PHY interface mode (e.g., RMII vs RGMII). This functionality maps to the 'output-enable' property in the device tree and requires explicit control via the ETH_MODE register. Signed-off-by: Biju Das --- v1->v2: * No change --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index cf7f9c2e37f8..5e3e56e32cea 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1198,6 +1198,23 @@ static int rzg2l_write_oen(struct rzg2l_pinctrl *pct= rl, unsigned int _pin, u8 oe return 0; } =20 +static int rzg3l_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int = _pin) +{ + u64 *pin_data =3D pctrl->desc.pins[_pin].drv_data; + u8 port, pin; + + if (*pin_data & RZG2L_SINGLE_PIN) + return -EINVAL; + + pin =3D RZG2L_PIN_ID_TO_PIN(_pin); + if (pin !=3D pctrl->data->hwcfg->oen_max_pin) + return -EINVAL; + + port =3D RZG2L_PIN_ID_TO_PORT(_pin); + + return (port =3D=3D pctrl->data->hwcfg->oen_max_port) ? 1 : 0; +} + static int rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int = _pin) { u64 *pin_data =3D pctrl->desc.pins[_pin].drv_data; --=20 2.43.0