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Tue, 03 Feb 2026 05:10:54 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Linus Walleij Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 04/10] pinctrl: renesas: rzg2l: Add support for selecting power source for {WDT,AWO,ISO} Date: Tue, 3 Feb 2026 13:10:27 +0000 Message-ID: <20260203131048.421708-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260203131048.421708-1-biju.das.jz@bp.renesas.com> References: <20260203131048.421708-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The RZ/G3L SoC has support for setting power source that are not controlled by the following voltage control registers: - SD_CH{0,1,2}_POC, XSPI_POC, ETH{0,1}_POC, I3C_SET.POC Add support for selecting voltages using OTHER_POC register for setting I/O domain voltage for WDT, ISO and AWO. Signed-off-by: Biju Das --- v1->v2: * No change --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 40 +++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 863e779dda02..cf7f9c2e37f8 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -63,10 +63,18 @@ #define PIN_CFG_SMT BIT(16) /* Schmitt-trigger input control */ #define PIN_CFG_ELC BIT(17) #define PIN_CFG_IOLH_RZV2H BIT(18) +#define PIN_CFG_PVDD1833_OTH_AWO_POC BIT(19) /* known on RZ/G3L only */ +#define PIN_CFG_PVDD1833_OTH_ISO_POC BIT(20) /* known on RZ/G3L only */ +#define PIN_CFG_WDTOVF_N_POC BIT(21) /* known on RZ/G3L only */ =20 #define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */ #define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */ =20 +#define PIN_CFG_OTHER_POC_MASK \ + (PIN_CFG_PVDD1833_OTH_AWO_POC | \ + PIN_CFG_PVDD1833_OTH_ISO_POC | \ + PIN_CFG_WDTOVF_N_POC) + #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \ (PIN_CFG_IOLH_##group | \ PIN_CFG_PUPD | \ @@ -146,6 +154,7 @@ #define SD_CH(off, ch) ((off) + (ch) * 4) #define ETH_POC(off, ch) ((off) + (ch) * 4) #define QSPI (0x3008) +#define OTHER_POC (0x3028) /* known on RZ/G3L only */ =20 #define PVDD_2500 2 /* I/O domain voltage 2.5V */ #define PVDD_1800 1 /* I/O domain voltage <=3D 1.8V */ @@ -906,6 +915,12 @@ static int rzg2l_caps_to_pwr_reg(const struct rzg2l_re= gister_offsets *regs, u32 return ETH_POC(regs->eth_poc, 1); if (caps & PIN_CFG_IO_VMC_QSPI) return QSPI; + if (caps & PIN_CFG_PVDD1833_OTH_AWO_POC) + return OTHER_POC; + if (caps & PIN_CFG_PVDD1833_OTH_ISO_POC) + return OTHER_POC; + if (caps & PIN_CFG_WDTOVF_N_POC) + return OTHER_POC; =20 return -EINVAL; } @@ -925,6 +940,13 @@ static int rzg2l_get_power_source(struct rzg2l_pinctrl= *pctrl, u32 pin, u32 caps return pwr_reg; =20 val =3D readb(pctrl->base + pwr_reg); + if (pwr_reg =3D=3D OTHER_POC) { + u32 poc =3D FIELD_GET(PIN_CFG_OTHER_POC_MASK, caps); + u8 offs =3D ffs(poc) - 1; + + val =3D (val >> offs) & 0x1; + } + switch (val) { case PVDD_1800: return 1800; @@ -943,6 +965,7 @@ static int rzg2l_set_power_source(struct rzg2l_pinctrl = *pctrl, u32 pin, u32 caps const struct rzg2l_hwcfg *hwcfg =3D pctrl->data->hwcfg; const struct rzg2l_register_offsets *regs =3D &hwcfg->regs; int pwr_reg; + u8 poc_val; u8 val; =20 if (caps & PIN_CFG_SOFT_PS) { @@ -952,15 +975,15 @@ static int rzg2l_set_power_source(struct rzg2l_pinctr= l *pctrl, u32 pin, u32 caps =20 switch (ps) { case 1800: - val =3D PVDD_1800; + poc_val =3D PVDD_1800; break; case 2500: if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1))) return -EINVAL; - val =3D PVDD_2500; + poc_val =3D PVDD_2500; break; case 3300: - val =3D PVDD_3300; + poc_val =3D PVDD_3300; break; default: return -EINVAL; @@ -970,6 +993,17 @@ static int rzg2l_set_power_source(struct rzg2l_pinctrl= *pctrl, u32 pin, u32 caps if (pwr_reg < 0) return pwr_reg; =20 + if (pwr_reg =3D=3D OTHER_POC) { + u32 poc =3D FIELD_GET(PIN_CFG_OTHER_POC_MASK, caps); + u8 offs =3D ffs(poc) - 1; + + val =3D readb(pctrl->base + pwr_reg); + val &=3D ~BIT(offs); + val |=3D (poc_val << offs); + } else { + val =3D poc_val; + } + writeb(val, pctrl->base + pwr_reg); pctrl->settings[pin].power_source =3D ps; =20 --=20 2.43.0