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Tue, 03 Feb 2026 05:10:52 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: Biju Das , Lad Prabhakar , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das , Conor Dooley Subject: [PATCH v2 01/10] dt-bindings: pinctrl: renesas: Document reset-names Date: Tue, 3 Feb 2026 13:10:24 +0000 Message-ID: <20260203131048.421708-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260203131048.421708-1-biju.das.jz@bp.renesas.com> References: <20260203131048.421708-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das All SoCs has multiple resets. Document reset-names property. Signed-off-by: Biju Das Acked-by: Conor Dooley --- v1-.v2: * Split DTSI patches from bindings * Fix typo maxItems->minItems * Collected tag --- .../bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.ya= ml index 00c05243b9a4..1a94e396b1b0 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -78,6 +78,16 @@ properties: - description: PFC main reset - description: Reset for the control register related to WDTUDFC= A and WDTUDFFCM pins =20 + reset-names: + oneOf: + - items: + - const: rstn + - const: port + - const: spare + - items: + - const: main + - const: error + additionalProperties: anyOf: - type: object @@ -152,10 +162,14 @@ allOf: properties: resets: maxItems: 2 + reset-names: + maxItems: 2 else: properties: resets: minItems: 3 + reset-names: + minItems: 3 =20 required: - compatible @@ -187,6 +201,7 @@ examples: resets =3D <&cpg R9A07G044_GPIO_RSTN>, <&cpg R9A07G044_GPIO_PORT_RESETN>, <&cpg R9A07G044_GPIO_SPARE_RESETN>; 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Tue, 03 Feb 2026 05:10:53 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: Biju Das , Lad Prabhakar , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das , Conor Dooley Subject: [PATCH v2 02/10] dt-bindings: pinctrl: renesas: Document RZ/G3L SoC Date: Tue, 3 Feb 2026 13:10:25 +0000 Message-ID: <20260203131048.421708-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260203131048.421708-1-biju.das.jz@bp.renesas.com> References: <20260203131048.421708-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add documentation for the pin controller found on the Renesas RZ/G3L (R9A08G046) SoC. The RZ/G3L PFC is similar to the RZ/G3S SoC but has more pins. Also add header file similar to RZ/G3E and RZ/V2H as it has alpha numeric ports. Signed-off-by: Biju Das Acked-by: Conor Dooley --- v1->v2: * Collected tag --- .../pinctrl/renesas,rzg2l-pinctrl.yaml | 1 + .../pinctrl/renesas,r9a08g046-pinctrl.h | 39 +++++++++++++++++++ 2 files changed, 40 insertions(+) create mode 100644 include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.ya= ml index 1a94e396b1b0..c276e3dcf616 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -26,6 +26,7 @@ properties: - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/= Five - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} - renesas,r9a08g045-pinctrl # RZ/G3S + - renesas,r9a08g046-pinctrl # RZ/G3L - renesas,r9a09g047-pinctrl # RZ/G3E - renesas,r9a09g056-pinctrl # RZ/V2N - renesas,r9a09g057-pinctrl # RZ/V2H(P) diff --git a/include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h b/incl= ude/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h new file mode 100644 index 000000000000..660c26477d42 --- /dev/null +++ b/include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * This header provides constants for Renesas RZ/G3L family pinctrl bindin= gs. + * + * Copyright (C) 2026 Renesas Electronics Corp. + * + */ + +#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A08G046_PINCTRL_H__ +#define __DT_BINDINGS_PINCTRL_RENESAS_R9A08G046_PINCTRL_H__ + +#include + +/* RZG3L_Px =3D Offset address of PFC_P_mn - 0x22 */ +#define RZG3L_P2 2 +#define RZG3L_P3 3 +#define RZG3L_P4 4 +#define RZG3L_P5 5 +#define RZG3L_P6 6 +#define RZG3L_P7 7 +#define RZG3L_P8 8 +#define RZG3L_PA 10 +#define RZG3L_PB 11 +#define RZG3L_PC 12 +#define RZG3L_PD 13 +#define RZG3L_PE 14 +#define RZG3L_PF 15 +#define RZG3L_PG 16 +#define RZG3L_PH 17 +#define RZG3L_PJ 19 +#define RZG3L_PK 20 +#define RZG3L_PL 21 +#define RZG3L_PM 22 +#define RZG3L_PS 28 + +#define RZG3L_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZG3L_P##b, p, f) +#define RZG3L_GPIO(port, pin) RZG2L_GPIO(RZG3L_P##port, pin) + +#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A08G046_PINCTRL_H__ */ --=20 2.43.0 From nobody Mon Feb 9 11:08:05 2026 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A23CD34F486 for ; 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charset="utf-8" From: Biju Das Add GPIO clock and reset entries. Signed-off-by: Biju Das --- v1->v2: * No change --- drivers/clk/renesas/r9a08g046-cpg.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a0= 8g046-cpg.c index a2856d8fa95b..795dc700bdaa 100644 --- a/drivers/clk/renesas/r9a08g046-cpg.c +++ b/drivers/clk/renesas/r9a08g046-cpg.c @@ -174,6 +174,7 @@ static const struct cpg_core_clk r9a08g046_core_clks[] = __initconst =3D { DEF_FIXED("ETHRM1", R9A08G046_CLK_ETHRM1, CLK_ETH1_RM, 1, 1), DEF_FIXED("ETHTX12", R9A08G046_CLK_ETHTX12, CLK_SEL_ETH1_TX, 1, 1), DEF_FIXED("ETHRX12", R9A08G046_CLK_ETHRX12, CLK_SEL_ETH1_RX, 1, 1), + DEF_FIXED("OSCCLK", R9A08G046_OSCCLK, CLK_EXTAL, 1, 1), }; =20 static const struct rzg2l_mod_clk r9a08g046_mod_clks[] =3D { @@ -229,6 +230,8 @@ static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = =3D { MSTOP(BUS_PERI_COM, BIT(3))), DEF_MOD("scif0_clk_pck", R9A08G046_SCIF0_CLK_PCK, R9A08G046_CLK_P0, 0x584= , 0, MSTOP(BUS_MCPU2, BIT(1))), + DEF_MOD("gpio_hclk", R9A08G046_GPIO_HCLK, R9A08G046_OSCCLK, 0x598, 0, + MSTOP(BUS_PERI_CPU, BIT(6))), }; =20 static const struct rzg2l_reset r9a08g046_resets[] =3D { @@ -240,6 +243,9 @@ static const struct rzg2l_reset r9a08g046_resets[] =3D { DEF_RST(R9A08G046_ETH0_ARESET_N, 0x87c, 0), DEF_RST(R9A08G046_ETH1_ARESET_N, 0x87c, 1), DEF_RST(R9A08G046_SCIF0_RST_SYSTEM_N, 0x884, 0), + DEF_RST(R9A08G046_GPIO_RSTN, 0x898, 0), + DEF_RST(R9A08G046_GPIO_PORT_RESETN, 0x898, 1), + DEF_RST(R9A08G046_GPIO_SPARE_RESETN, 0x898, 2), }; =20 static const unsigned int r9a08g046_crit_mod_clks[] __initconst =3D { --=20 2.43.0 From nobody Mon Feb 9 11:08:05 2026 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8094D34F494 for ; Tue, 3 Feb 2026 13:10:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770124258; 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Tue, 03 Feb 2026 05:10:54 -0800 (PST) Received: from biju.lan ([2a00:23c4:a758:8a01:9cd9:f748:166d:55fc]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4830512ddd0sm63662185e9.9.2026.02.03.05.10.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Feb 2026 05:10:54 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Linus Walleij Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 04/10] pinctrl: renesas: rzg2l: Add support for selecting power source for {WDT,AWO,ISO} Date: Tue, 3 Feb 2026 13:10:27 +0000 Message-ID: <20260203131048.421708-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260203131048.421708-1-biju.das.jz@bp.renesas.com> References: <20260203131048.421708-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The RZ/G3L SoC has support for setting power source that are not controlled by the following voltage control registers: - SD_CH{0,1,2}_POC, XSPI_POC, ETH{0,1}_POC, I3C_SET.POC Add support for selecting voltages using OTHER_POC register for setting I/O domain voltage for WDT, ISO and AWO. Signed-off-by: Biju Das --- v1->v2: * No change --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 40 +++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 863e779dda02..cf7f9c2e37f8 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -63,10 +63,18 @@ #define PIN_CFG_SMT BIT(16) /* Schmitt-trigger input control */ #define PIN_CFG_ELC BIT(17) #define PIN_CFG_IOLH_RZV2H BIT(18) +#define PIN_CFG_PVDD1833_OTH_AWO_POC BIT(19) /* known on RZ/G3L only */ +#define PIN_CFG_PVDD1833_OTH_ISO_POC BIT(20) /* known on RZ/G3L only */ +#define PIN_CFG_WDTOVF_N_POC BIT(21) /* known on RZ/G3L only */ =20 #define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */ #define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */ =20 +#define PIN_CFG_OTHER_POC_MASK \ + (PIN_CFG_PVDD1833_OTH_AWO_POC | \ + PIN_CFG_PVDD1833_OTH_ISO_POC | \ + PIN_CFG_WDTOVF_N_POC) + #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \ (PIN_CFG_IOLH_##group | \ PIN_CFG_PUPD | \ @@ -146,6 +154,7 @@ #define SD_CH(off, ch) ((off) + (ch) * 4) #define ETH_POC(off, ch) ((off) + (ch) * 4) #define QSPI (0x3008) +#define OTHER_POC (0x3028) /* known on RZ/G3L only */ =20 #define PVDD_2500 2 /* I/O domain voltage 2.5V */ #define PVDD_1800 1 /* I/O domain voltage <=3D 1.8V */ @@ -906,6 +915,12 @@ static int rzg2l_caps_to_pwr_reg(const struct rzg2l_re= gister_offsets *regs, u32 return ETH_POC(regs->eth_poc, 1); if (caps & PIN_CFG_IO_VMC_QSPI) return QSPI; + if (caps & PIN_CFG_PVDD1833_OTH_AWO_POC) + return OTHER_POC; + if (caps & PIN_CFG_PVDD1833_OTH_ISO_POC) + return OTHER_POC; + if (caps & PIN_CFG_WDTOVF_N_POC) + return OTHER_POC; =20 return -EINVAL; } @@ -925,6 +940,13 @@ static int rzg2l_get_power_source(struct rzg2l_pinctrl= *pctrl, u32 pin, u32 caps return pwr_reg; =20 val =3D readb(pctrl->base + pwr_reg); + if (pwr_reg =3D=3D OTHER_POC) { + u32 poc =3D FIELD_GET(PIN_CFG_OTHER_POC_MASK, caps); + u8 offs =3D ffs(poc) - 1; + + val =3D (val >> offs) & 0x1; + } + switch (val) { case PVDD_1800: return 1800; @@ -943,6 +965,7 @@ static int rzg2l_set_power_source(struct rzg2l_pinctrl = *pctrl, u32 pin, u32 caps const struct rzg2l_hwcfg *hwcfg =3D pctrl->data->hwcfg; const struct rzg2l_register_offsets *regs =3D &hwcfg->regs; int pwr_reg; + u8 poc_val; u8 val; =20 if (caps & PIN_CFG_SOFT_PS) { @@ -952,15 +975,15 @@ static int rzg2l_set_power_source(struct rzg2l_pinctr= l *pctrl, u32 pin, u32 caps =20 switch (ps) { case 1800: - val =3D PVDD_1800; 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Tue, 03 Feb 2026 05:10:55 -0800 (PST) Received: from biju.lan ([2a00:23c4:a758:8a01:9cd9:f748:166d:55fc]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4830512ddd0sm63662185e9.9.2026.02.03.05.10.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Feb 2026 05:10:54 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Linus Walleij Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 05/10] pinctrl: renesas: rzg2l: Add OEN support for RZ/G3L Date: Tue, 3 Feb 2026 13:10:28 +0000 Message-ID: <20260203131048.421708-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260203131048.421708-1-biju.das.jz@bp.renesas.com> References: <20260203131048.421708-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add support for configuring the ETH_MODE register on the RZ/G3L SoC to enable output-enable control for specific pins. On this SoC, certain pins such as P{B,E}1_ISO need to support switching between input and output modes depending on the PHY interface mode (e.g., RMII vs RGMII). This functionality maps to the 'output-enable' property in the device tree and requires explicit control via the ETH_MODE register. Signed-off-by: Biju Das --- v1->v2: * No change --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index cf7f9c2e37f8..5e3e56e32cea 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1198,6 +1198,23 @@ static int rzg2l_write_oen(struct rzg2l_pinctrl *pct= rl, unsigned int _pin, u8 oe return 0; } =20 +static int rzg3l_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int = _pin) +{ + u64 *pin_data =3D pctrl->desc.pins[_pin].drv_data; + u8 port, pin; + + if (*pin_data & RZG2L_SINGLE_PIN) + return -EINVAL; + + pin =3D RZG2L_PIN_ID_TO_PIN(_pin); + if (pin !=3D pctrl->data->hwcfg->oen_max_pin) + return -EINVAL; + + port =3D RZG2L_PIN_ID_TO_PORT(_pin); + + return (port =3D=3D pctrl->data->hwcfg->oen_max_port) ? 1 : 0; +} + static int rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int = _pin) { u64 *pin_data =3D pctrl->desc.pins[_pin].drv_data; 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Tue, 03 Feb 2026 05:10:55 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Linus Walleij , Magnus Damm Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 06/10] pinctrl: renesas: rzg2l: Add support for RZ/G3L SoC Date: Tue, 3 Feb 2026 13:10:29 +0000 Message-ID: <20260203131048.421708-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260203131048.421708-1-biju.das.jz@bp.renesas.com> References: <20260203131048.421708-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add pinctrl driver support for RZ/G3L SoC. Signed-off-by: Biju Das --- v1->v2: * No change --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 228 ++++++++++++++++++++++++ 1 file changed, 228 insertions(+) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 5e3e56e32cea..e45282afcf86 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -26,6 +26,7 @@ #include #include =20 +#include #include #include #include @@ -93,6 +94,17 @@ =20 #define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | PIN_CFG_NF) =20 +#define RZG3L_MPXED_ETH_PIN_FUNCS(ether) \ + (PIN_CFG_IO_VMC_##ether | \ + PIN_CFG_IOLH_C | \ + PIN_CFG_NF) + +#define RZG3L_MPXED_PIN_FUNCS(group) (RZG2L_MPXED_COMMON_PIN_FUNCS(group) = | \ + PIN_CFG_SOFT_PS) + +#define RZG3L_MPXED_PIN_FUNCS_POC(grp, poc) (RZG3L_MPXED_PIN_FUNCS(grp) | \ + PIN_CFG_PVDD1833_OTH_##poc##_POC) + #define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(61, 54) #define PIN_CFG_PIN_REG_MASK GENMASK_ULL(53, 46) #define PIN_CFG_MASK GENMASK_ULL(31, 0) @@ -229,12 +241,14 @@ static const struct pin_config_item renesas_rzv2h_con= f_items[] =3D { * @sd_ch: SD_CH register offset * @eth_poc: ETH_POC register offset * @oen: OEN register offset + * @other_poc: OTHER_POC register offset */ struct rzg2l_register_offsets { u16 pwpr; u16 sd_ch; u16 eth_poc; u16 oen; + u16 other_poc; }; =20 /** @@ -333,6 +347,7 @@ struct rzg2l_pinctrl_pin_settings { * @smt: SMT registers cache * @sd_ch: SD_CH registers cache * @eth_poc: ET_POC registers cache + * @other_poc: OTHER_POC register cache * @oen: Output Enable register cache * @qspi: QSPI registers cache */ @@ -348,6 +363,7 @@ struct rzg2l_pinctrl_reg_cache { u8 sd_ch[2]; u8 eth_poc[2]; u8 oen; + u8 other_poc; u8 qspi; }; =20 @@ -397,6 +413,60 @@ static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct r= zg2l_pinctrl *pctrl, return 0; } =20 +static const u64 r9a08g046_variable_pin_cfg[] =3D { + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 0, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0) = | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 1, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 2, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 3, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 4, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0) = | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 0, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 1, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0) = | PIN_CFG_OEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 2, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 3, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 4, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 0, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1) = | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 1, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 2, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 3, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 4, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 0, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 1, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1) = | PIN_CFG_OEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 2, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 3, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 4, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 0, RZG3L_MPXED_PIN_FUNCS(B)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 1, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 2, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 3, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 4, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 5, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 6, RZG3L_MPXED_PIN_FUNCS_POC(B, ISO= )), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 7, RZG3L_MPXED_PIN_FUNCS_POC(B, ISO= )), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 0, RZG3L_MPXED_PIN_FUNCS(B)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 1, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 2, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 3, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 4, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 5, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 0, RZG3L_MPXED_PIN_FUNCS(A) | PIN_C= FG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 1, RZG3L_MPXED_PIN_FUNCS(A)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 2, RZG3L_MPXED_PIN_FUNCS(A)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 3, RZG3L_MPXED_PIN_FUNCS(A)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 4, RZG3L_MPXED_PIN_FUNCS(A)), +}; + static const u64 r9a09g047_variable_pin_cfg[] =3D { RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_= IEN), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 1, RZV2H_MPXED_PIN_FUNCS), @@ -2141,6 +2211,70 @@ static const u64 r9a09g047_gpio_configs[] =3D { RZG2L_GPIO_PORT_PACK(4, 0x3c, RZV2H_MPXED_PIN_FUNCS), /* PS */ }; =20 +static const char * const rzg3l_gpio_names[] =3D { + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27", + "P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37", + "", "", "", "", "", "", "", "", + "P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57", + "P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67", + "P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77", + "P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87", + "", "", "", "", "", "", "", "", + "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", + "PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7", + "PC0", "PC1", "PC2", "PC3", "PC4", "PC5", "PC6", "PC7", + "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", + "PE0", "PE1", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", + "PF0", "PF1", "PF2", "PF3", "PF4", "PF5", "PF6", "PF7", + "PG0", "PG1", "PG2", "PG3", "PG4", "PG5", "PG6", "PG7", + "PH0", "PH1", "PH2", "PH3", "PH4", "PH5", "PH6", "PH7", + "", "", "", "", "", "", "", "", + "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", "PJ5", "PJ6", "PJ7", + "PK0", "PK1", "PK2", "PK3", "PK4", "PK5", "PK6", "PK7", + "PL0", "PL1", "PL2", "PL3", "PL4", "PL5", "PL6", "PL7", + "PM0", "PM1", "PM2", "PM3", "PM4", "PM5", "PM6", "PM7", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "PS0", "PS1", "PS2", "PS3", "PS4", "PS5", "PS6", "PS7", +}; + +static const u64 r9a08g046_gpio_configs[] =3D { + 0x0, + 0x0, + RZG2L_GPIO_PORT_PACK(2, 0x22, PIN_CFG_NF | PIN_CFG_IEN), /* P2 */ + RZG2L_GPIO_PORT_PACK(7, 0x23, RZG3L_MPXED_PIN_FUNCS_POC(A, AWO)), /* P3 */ + 0x0, + RZG2L_GPIO_PORT_PACK(7, 0x25, RZG3L_MPXED_PIN_FUNCS_POC(A, AWO)), /* P5 */ + RZG2L_GPIO_PORT_PACK(7, 0x26, RZG3L_MPXED_PIN_FUNCS_POC(A, AWO)), /* P6 */ + RZG2L_GPIO_PORT_PACK(8, 0x27, RZG3L_MPXED_PIN_FUNCS_POC(A, AWO)), /* P7 */ + RZG2L_GPIO_PORT_PACK(6, 0x28, RZG3L_MPXED_PIN_FUNCS_POC(A, AWO)), /* P8 */ + 0x0, + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2a), /* PA */ + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2b), /* PB */ + RZG2L_GPIO_PORT_PACK(3, 0x2c, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), /* PC */ + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2d), /* PD */ + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2e), /* PE */ + RZG2L_GPIO_PORT_PACK(3, 0x2f, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), /* PF */ + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x30), /* PG */ + RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x31), /* PH */ + 0x0, + RZG2L_GPIO_PORT_PACK_VARIABLE(5, 0x33), /* PJ */ + RZG2L_GPIO_PORT_PACK(4, 0x34, RZG3L_MPXED_PIN_FUNCS_POC(B, AWO)), /* PK */ + RZG2L_GPIO_PORT_PACK(5, 0x35, RZG3L_MPXED_PIN_FUNCS(C)), /* PL */ + RZG2L_GPIO_PORT_PACK(8, 0x36, RZG3L_MPXED_PIN_FUNCS(C)), /* PM */ + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + RZG2L_GPIO_PORT_PACK(2, 0x3c, RZG3L_MPXED_PIN_FUNCS(A)), /* PS */ +}; + static const char * const rzv2h_gpio_names[] =3D { "P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07", "P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17", @@ -2479,6 +2613,37 @@ static struct rzg2l_dedicated_configs rzg3e_dedicate= d_pins[] =3D { (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, }; =20 +static const struct rzg2l_dedicated_configs rzg3l_dedicated_pins[] =3D { + { "WDTOVF_N", RZG2L_SINGLE_PIN_PACK(0x5, 0, + (PIN_CFG_IOLH_A | PIN_CFG_WDTOVF_N_POC)) }, + { "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0, + (PIN_CFG_IOLH_A | PIN_CFG_PUPD | PIN_CFG_PVDD1833_OTH_AWO_POC)) }, + { "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, + (PIN_CFG_IOLH_A | PIN_CFG_PUPD | PIN_CFG_PVDD1833_OTH_AWO_POC)) }, + { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, PIN_CFG_IOLH_B) }, + { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x9, 2, PIN_CFG_IOLH_B) }, + { "SD0_DS", RZG2L_SINGLE_PIN_PACK(0x9, 5, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x0a, 0, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x0a, 1, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x0a, 2, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x0a, 3, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x0a, 4, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x0a, 5, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x0a, 6, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x0a, 7, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, +}; + static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl = *pctrl) { const struct pinctrl_pin_desc *pin_desc =3D &pctrl->desc.pins[virq]; @@ -3007,6 +3172,9 @@ static int rzg2l_pinctrl_probe(struct platform_device= *pdev) BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT > ARRAY_SIZE(rzg2l_gpio_names)); =20 + BUILD_BUG_ON(ARRAY_SIZE(r9a08g046_gpio_configs) * RZG2L_PINS_PER_PORT > + ARRAY_SIZE(rzg3l_gpio_names)); + BUILD_BUG_ON(ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT > ARRAY_SIZE(rzg3e_gpio_names)); =20 @@ -3254,6 +3422,8 @@ static int rzg2l_pinctrl_suspend_noirq(struct device = *dev) =20 cache->qspi =3D readb(pctrl->base + QSPI); cache->oen =3D readb(pctrl->base + pctrl->data->hwcfg->regs.oen); + if (regs->other_poc) + cache->other_poc =3D readb(pctrl->base + regs->other_poc); =20 if (!atomic_read(&pctrl->wakeup_path)) clk_disable_unprepare(pctrl->clk); @@ -3279,6 +3449,8 @@ static int rzg2l_pinctrl_resume_noirq(struct device *= dev) } =20 writeb(cache->qspi, pctrl->base + QSPI); + if (regs->other_poc) + writeb(cache->other_poc, pctrl->base + regs->other_poc); =20 raw_spin_lock_irqsave(&pctrl->lock, flags); rzg2l_oen_write_with_pwpr(pctrl, cache->oen); @@ -3380,6 +3552,41 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg =3D { .oen_max_port =3D 7, /* P7_1 is the maximum OEN port. */ }; =20 +static const struct rzg2l_hwcfg rzg3l_hwcfg =3D { + .regs =3D { + .pwpr =3D 0x3000, + .sd_ch =3D 0x3004, + .eth_poc =3D 0x3010, + .oen =3D 0x3018, + .other_poc =3D 0x3028, + }, + .iolh_groupa_ua =3D { + /* 1v8 power source */ + [RZG2L_IOLH_IDX_1V8] =3D 2200, 4400, 9000, 10000, + /* 3v3 power source */ + [RZG2L_IOLH_IDX_3V3] =3D 1900, 4000, 8000, 9000, + }, + .iolh_groupb_ua =3D { + /* 1v8 power source */ + [RZG2L_IOLH_IDX_1V8] =3D 7000, 8000, 9000, 10000, + /* 3v3 power source */ + [RZG2L_IOLH_IDX_3V3] =3D 4000, 6000, 8000, 9000, + }, + .iolh_groupc_ua =3D { + /* 1v8 power source */ + [RZG2L_IOLH_IDX_1V8] =3D 5200, 6000, 6550, 6800, + /* 2v5 source */ + [RZG2L_IOLH_IDX_2V5] =3D 4700, 5300, 5800, 6100, + /* 3v3 power source */ + [RZG2L_IOLH_IDX_3V3] =3D 4500, 5200, 5700, 6050, + }, + .tint_start_index =3D 17, + .drive_strength_ua =3D true, + .func_base =3D 0, + .oen_max_pin =3D 1, /* Pin 1 of PE1_ISO is the maximum OEN pin. */ + .oen_max_port =3D 14, /* PE1_ISO is the maximum OEN port. */ +}; + static const struct rzg2l_hwcfg rzv2h_hwcfg =3D { .regs =3D { .pwpr =3D 0x3c04, @@ -3439,6 +3646,23 @@ static struct rzg2l_pinctrl_data r9a08g045_data =3D { .bias_param_to_hw =3D &rzg2l_bias_param_to_hw, }; =20 +static struct rzg2l_pinctrl_data r9a08g046_data =3D { + .port_pins =3D rzg3l_gpio_names, + .port_pin_configs =3D r9a08g046_gpio_configs, + .n_ports =3D ARRAY_SIZE(r9a08g046_gpio_configs), + .variable_pin_cfg =3D r9a08g046_variable_pin_cfg, + .n_variable_pin_cfg =3D ARRAY_SIZE(r9a08g046_variable_pin_cfg), + .dedicated_pins =3D rzg3l_dedicated_pins, + .n_port_pins =3D ARRAY_SIZE(r9a08g046_gpio_configs) * RZG2L_PINS_PER_PORT, + .n_dedicated_pins =3D ARRAY_SIZE(rzg3l_dedicated_pins), + .hwcfg =3D &rzg3l_hwcfg, + .pwpr_pfc_lock_unlock =3D &rzg2l_pwpr_pfc_lock_unlock, + .pmc_writeb =3D &rzg2l_pmc_writeb, + .pin_to_oen_bit =3D &rzg3l_pin_to_oen_bit, + .hw_to_bias_param =3D &rzg2l_hw_to_bias_param, + .bias_param_to_hw =3D &rzg2l_bias_param_to_hw, +}; + static struct rzg2l_pinctrl_data r9a09g047_data =3D { .port_pins =3D rzg3e_gpio_names, .port_pin_configs =3D r9a09g047_gpio_configs, @@ -3519,6 +3743,10 @@ static const struct of_device_id rzg2l_pinctrl_of_ta= ble[] =3D { .compatible =3D "renesas,r9a08g045-pinctrl", .data =3D &r9a08g045_data, }, + { + .compatible =3D "renesas,r9a08g046-pinctrl", + .data =3D &r9a08g046_data, + }, { .compatible =3D "renesas,r9a09g047-pinctrl", .data =3D &r9a09g047_data, --=20 2.43.0 From nobody Mon Feb 9 11:08:05 2026 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6413B350A04 for ; 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Tue, 03 Feb 2026 05:10:56 -0800 (PST) Received: from biju.lan ([2a00:23c4:a758:8a01:9cd9:f748:166d:55fc]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4830512ddd0sm63662185e9.9.2026.02.03.05.10.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Feb 2026 05:10:56 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 07/10] arm64: dts: renesas: Add reset-names for RZ/G2L and RZ/V2H family SoCs Date: Tue, 3 Feb 2026 13:10:30 +0000 Message-ID: <20260203131048.421708-8-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260203131048.421708-1-biju.das.jz@bp.renesas.com> References: <20260203131048.421708-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add reset-names for RZ/{G2L,G2UL,G3S} and RZ/{V2L,V2H,V2N} SoCs. Signed-off-by: Biju Das --- v2: * New patch --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 1 + 7 files changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/d= ts/renesas/r9a07g043.dtsi index 593c66b27ad1..ded4f1f11d60 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -604,6 +604,7 @@ pinctrl: pinctrl@11030000 { resets =3D <&cpg R9A07G043_GPIO_RSTN>, <&cpg R9A07G043_GPIO_PORT_RESETN>, <&cpg R9A07G043_GPIO_SPARE_RESETN>; + reset-names =3D "rstn", "port", "spare"; }; =20 dmac: dma-controller@11820000 { diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/d= ts/renesas/r9a07g044.dtsi index 29273da81995..cb0c9550aa03 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -1017,6 +1017,7 @@ pinctrl: pinctrl@11030000 { resets =3D <&cpg R9A07G044_GPIO_RSTN>, <&cpg R9A07G044_GPIO_PORT_RESETN>, <&cpg R9A07G044_GPIO_SPARE_RESETN>; + reset-names =3D "rstn", "port", "spare"; }; =20 irqc: interrupt-controller@110a0000 { diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/d= ts/renesas/r9a07g054.dtsi index 0dee48c4f1e4..7a3e5b6a685f 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -1025,6 +1025,7 @@ pinctrl: pinctrl@11030000 { resets =3D <&cpg R9A07G054_GPIO_RSTN>, <&cpg R9A07G054_GPIO_PORT_RESETN>, <&cpg R9A07G054_GPIO_SPARE_RESETN>; + reset-names =3D "rstn", "port", "spare"; }; =20 irqc: interrupt-controller@110a0000 { diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g045.dtsi index 997e6cf0bb82..3a69bb246bab 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -533,6 +533,7 @@ pinctrl: pinctrl@11030000 { resets =3D <&cpg R9A08G045_GPIO_RSTN>, <&cpg R9A08G045_GPIO_PORT_RESETN>, <&cpg R9A08G045_GPIO_SPARE_RESETN>; + reset-names =3D "rstn", "port", "spare"; }; =20 irqc: interrupt-controller@11050000 { diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g047.dtsi index cbb48ff5028f..66f40cb1464d 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -265,6 +265,7 @@ pinctrl: pinctrl@10410000 { interrupt-parent =3D <&icu>; power-domains =3D <&cpg>; resets =3D <&cpg 0xa5>, <&cpg 0xa6>; + reset-names =3D "main", "error"; }; =20 cpg: clock-controller@10420000 { diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g056.dtsi index 9fb15ca24984..e85daef4e42d 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -288,6 +288,7 @@ pinctrl: pinctrl@10410000 { gpio-ranges =3D <&pinctrl 0 0 96>; power-domains =3D <&cpg>; resets =3D <&cpg 0xa5>, <&cpg 0xa6>; + reset-names =3D "main", "error"; }; =20 cpg: clock-controller@10420000 { diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g057.dtsi index 80cba9fcfe7b..38793b948c02 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -270,6 +270,7 @@ pinctrl: pinctrl@10410000 { interrupt-parent =3D <&icu>; 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Tue, 03 Feb 2026 05:10:56 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 08/10] arm64: dts: renesas: r9a08g046: Add pincontrol node Date: Tue, 3 Feb 2026 13:10:31 +0000 Message-ID: <20260203131048.421708-9-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260203131048.421708-1-biju.das.jz@bp.renesas.com> References: <20260203131048.421708-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add pincontrol node to RZ/G3L ("R9A08G046") SoC DTSI. Signed-off-by: Biju Das --- v1->v2: * No change --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g046.dtsi index df61a3b77368..a92a4e07cc10 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -181,9 +181,19 @@ sysc: system-controller@11020000 { }; =20 pinctrl: pinctrl@11030000 { + compatible =3D "renesas,r9a08g046-pinctrl"; reg =3D <0 0x11030000 0 0x10000>; gpio-controller; #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl 0 0 232>; + interrupt-controller; + #interrupt-cells =3D <2>; + clocks =3D <&cpg CPG_MOD R9A08G046_GPIO_HCLK>; + power-domains =3D <&cpg>; + resets =3D <&cpg R9A08G046_GPIO_RSTN>, + <&cpg R9A08G046_GPIO_PORT_RESETN>, + <&cpg R9A08G046_GPIO_SPARE_RESETN>; + reset-names =3D "rstn", "port", "spare"; }; =20 dmac: dma-controller@11820000 { --=20 2.43.0 From nobody Mon Feb 9 11:08:05 2026 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D5AC350D5A for ; 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Tue, 03 Feb 2026 05:10:57 -0800 (PST) Received: from biju.lan ([2a00:23c4:a758:8a01:9cd9:f748:166d:55fc]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4830512ddd0sm63662185e9.9.2026.02.03.05.10.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Feb 2026 05:10:57 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 09/10] arm64: dts: renesas: r9a08g046l48-smarc: Add SCIF0 pincontrol Date: Tue, 3 Feb 2026 13:10:32 +0000 Message-ID: <20260203131048.421708-10-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260203131048.421708-1-biju.das.jz@bp.renesas.com> References: <20260203131048.421708-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add device node for SCIF0 pincontrol. Signed-off-by: Biju Das --- v1->v2: * No change --- arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm6= 4/boot/dts/renesas/r9a08g046l48-smarc.dts index 86db86335d5e..2f918830b8f1 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts @@ -35,3 +35,15 @@ &keys { /delete-node/ key-2; /delete-node/ key-3; }; + +&pinctrl { + scif0_pins: scif0 { + pins =3D "SCIF_TXD", "SCIF_RXD"; + power-source =3D <1800>; + }; +}; + +&scif0 { + pinctrl-0 =3D <&scif0_pins>; + pinctrl-names =3D "default"; +}; --=20 2.43.0 From nobody Mon Feb 9 11:08:05 2026 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51C19350D7C for ; Tue, 3 Feb 2026 13:11:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 03 Feb 2026 05:10:58 -0800 (PST) Received: from biju.lan ([2a00:23c4:a758:8a01:9cd9:f748:166d:55fc]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4830512ddd0sm63662185e9.9.2026.02.03.05.10.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Feb 2026 05:10:57 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 10/10] arm64: dts: renesas: rzg3l-smarc-som: Enable eth1 (GBETH1) interface Date: Tue, 3 Feb 2026 13:10:33 +0000 Message-ID: <20260203131048.421708-11-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260203131048.421708-1-biju.das.jz@bp.renesas.com> References: <20260203131048.421708-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Enable the Gigabit Ethernet Interface (GBETH1) populated on the RZ/G3L SMARC EVK. Also add pincontrol definitions for GBETH{0,1}. Signed-off-by: Biju Das --- v1->v2: * No change --- .../boot/dts/renesas/r9a08g046l48-smarc.dts | 1 + .../boot/dts/renesas/rzg3l-smarc-som.dtsi | 92 +++++++++++++++++++ 2 files changed, 93 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm6= 4/boot/dts/renesas/r9a08g046l48-smarc.dts index 2f918830b8f1..58733016b66b 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts @@ -14,6 +14,7 @@ =20 #include #include +#include #include "r9a08g046l48.dtsi" #include "rzg3l-smarc-som.dtsi" #include "renesas-smarc2.dtsi" diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3l-smarc-som.dtsi index f52af01a7eff..0b9bb073c282 100644 --- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi @@ -10,6 +10,7 @@ / { =20 aliases { ethernet0 =3D ð0; + ethernet1 =3D ð1; }; =20 memory@48000000 { @@ -23,6 +24,8 @@ ð0 { phy-handle =3D <&phy0>; phy-mode =3D "rgmii-id"; =20 + pinctrl-0 =3D <ð0_pins>; + pinctrl-names =3D "default"; status =3D "okay"; }; =20 @@ -30,6 +33,19 @@ ð0_rxc_rx_clk { clock-frequency =3D <125000000>; }; =20 +ð1 { + phy-handle =3D <&phy1>; + phy-mode =3D "rgmii-id"; + + pinctrl-0 =3D <ð1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +ð1_rxc_rx_clk { + clock-frequency =3D <125000000>; +}; + &extal_clk { clock-frequency =3D <24000000>; }; @@ -53,3 +69,79 @@ phy0: ethernet-phy@7 { txd3-skew-psec =3D <0>; }; }; + +&mdio1 { + phy1: ethernet-phy@7 { + compatible =3D "ethernet-phy-id0022.1640", + "ethernet-phy-ieee802.3-c22"; + reg =3D <7>; + rxc-skew-psec =3D <1400>; + txc-skew-psec =3D <1400>; + rxdv-skew-psec =3D <0>; + txdv-skew-psec =3D <0>; + rxd0-skew-psec =3D <0>; + rxd1-skew-psec =3D <0>; + rxd2-skew-psec =3D <0>; + rxd3-skew-psec =3D <0>; + txd0-skew-psec =3D <0>; + txd1-skew-psec =3D <0>; + txd2-skew-psec =3D <0>; + txd3-skew-psec =3D <0>; + }; +}; + +&pinctrl { + eth0_pins: eth0 { + txc { + pinmux =3D ; /* ETH0_TXC_REF_CLK */ + power-source =3D <1800>; + output-enable; + drive-strength-microamp =3D <5200>; + }; + + ctrl { + pinmux =3D , /* MDC */ + , /* MDIO */ + , /* PHY_INTR */ + , /* RXD3 */ + , /* RXD2 */ + , /* RXD1 */ + , /* RXD0 */ + , /* RXC */ + , /* RX_CTL */ + , /* TXD3 */ + , /* TXD2 */ + , /* TXD1 */ + , /* TXD0 */ + ; /* TX_CTL */ + power-source =3D <1800>; + }; + }; + + eth1_pins: eth1 { + txc { + pinmux =3D ; /* ETH1_TXC_REF_CLK */ + power-source =3D <1800>; + output-enable; + drive-strength-microamp =3D <5200>; + }; + + ctrl { + pinmux =3D , /* MDC */ + , /* MDIO */ + , /* PHY_INTR */ + , /* RXD3 */ + , /* RXD2 */ + , /* RXD1 */ + , /* RXD0 */ + , /* RXC */ + , /* RX_CTL */ + , /* TXD3 */ + , /* TXD2 */ + , /* TXD1 */ + , /* TXD0 */ + ; /* TX_CTL */ + power-source =3D <1800>; + }; + }; +}; --=20 2.43.0