From nobody Tue Feb 10 04:17:24 2026 Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2BF8131D750 for ; Tue, 3 Feb 2026 10:30:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770114643; cv=none; b=iqt5IROW1LYs1/6Aa4Hwk0Rv1MEdoEwrmddmqwLFff5E54CZv6HqBApXqZeqEq8YzgDa7NDej1MPQTiY0cz4S/kr+0jDPM2cwAF9ZRwxdoIGCdRa8QJqp58t8yKp7dePABANPAdubrRe9dT00xPTSW59KCrLyWR3dEBWa+5kigs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770114643; c=relaxed/simple; bh=nqmViFdlK42egAFk21RI6YJ93SMnNNtye7DqWuUewbQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nIYAkuQUxohnPnFx7YYA9pfXcSa06jidWpM1KmTxfGfwOru5u4g3bfWhmB83UUkriM3nHCrPQ7YCbENWX/8TNQf1oc9rnJxlcY5SFubNTyphUr0FrgNMsorU2mARR4QF+zEMRCV9GcO9ZvsZ3R4EjGG0I+F5vBaTPaQTbT55g0Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=HHPjp2MF; arc=none smtp.client-ip=209.85.221.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="HHPjp2MF" Received: by mail-wr1-f51.google.com with SMTP id ffacd0b85a97d-43591b55727so4782388f8f.3 for ; Tue, 03 Feb 2026 02:30:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770114637; x=1770719437; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Fmzs8IPde+eTGNnjrRCkZOQdZ8/wWeNdZ8L5PAnUMI4=; b=HHPjp2MFhO9BsOd9LGb/TnpzxV7eJFB+nOHY0HIiSsRjAcn7DwN7UbAQtxcDgZUw1Z bCq76Sd49AGv0e5Qudsa6VCnJLwv/w8zHQ1i6ZT+C3ZHAdPFMZwxLuTrylFl5/kfvWCx qUHDbQPgr/bQCiNAQoZfCdIzUpyT0n1UxdD4QvBTBSSy+hhusDaDl+etpGCOW5MDoX9M fbLOKuQJ+o2TbdIrU+xfriaUDjkR0rAKobFNRddJsQ0HwtO9CxFGvD+epP8FOK5I1eCa wYa2tevjq3kiR6/MoqMJyGfDXBaUoHdYQ8vZWlgfwVEsZo7WORMIe+bjuYkpKVZsbaRV Faew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770114637; x=1770719437; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=Fmzs8IPde+eTGNnjrRCkZOQdZ8/wWeNdZ8L5PAnUMI4=; b=b92lOGKuGdtv0SxKa8+D8c0v4IfzN4qixAluf6yowos89nATS9TliThFy3nz1YD2aK +iG+8BkGTX+0+RgBg9VxwJLhnDH3MLtvOhTJavazt0dpncOPpK8puA6GHzusHwKHEuMt bhK9WILFaomNvji99H0I+l8pdGfz4LKNsslrDC7AkKTWEwwCgjmgNZDYpv0+qQU1i70v RRaGKla8SyQL2YePPl5QX2PvnMkQq5dXc1uCFGJXBb33N3ei+W2wTmw7t9DGf/4zmWK0 fpPY3fGUfCBMmyj0jTZhiO/rVAff6EeKW1/MS1kZE81VfmYrM6wFX9O4HoFKbt223xdm OocQ== X-Forwarded-Encrypted: i=1; AJvYcCXTieB1X/H5K4Pm7qmQL9LHEP202guUnaBuVpkoju0v7/ndm/3/ww4NDaK8Vqch4PDD6/LJmfHLFScwxn0=@vger.kernel.org X-Gm-Message-State: AOJu0YzmLfgv1OEOKf/4PVVi5AApywXgr/o4XhtGAnURZSsQUwlBHdLl Sbacrsve4mD53+q2iJjjSFiOT1g9bnFTBrI6UBJ1rCqWN2Ew67xu5/oN X-Gm-Gg: AZuq6aJeYETrP7YWE655ndcg9LvX7PsT3bIMx+c06wDN4K9W4IfB9VaIaX8IPKAp8Pj Gv5KWZEUjaAEzGccBTSTre2x+4qzTM9elSsH4Q+a27MYfAWK7VYj+yhWt1UCdxTAFRrjO8ZVeen rR8TZvtVrbSWX+ILafvZu0Q9ob2NSmuWqrd7a/BGAR46meariCe7fJji/7rP4oEUQJObhH/3a0m dsk7f056aC1fz13DPSyI0RXT2Xb8+pOD4vJht/OPjU4SPrFggEVTcJNyJnFMGpfiWBfSpSYArWI 8sUzDVm/YUP3Ii7HyUmgr9ZRe9xwtjUU9Af7+FZZy/VjOjMlsEnPR3lMCHLrHyUD4dGomltG/UK IdhqydjEvL0svSGjf3grbg8JyvpUIpbV3XGn/+h0+jHsxVsNEvJ1VxBst9gVeRxzPpckN0bZNZU /iMo9GZ6272YEDa1SjKQ== X-Received: by 2002:a5d:64e6:0:b0:435:9223:bfd6 with SMTP id ffacd0b85a97d-435f3a7bc25mr24116805f8f.25.1770114637295; Tue, 03 Feb 2026 02:30:37 -0800 (PST) Received: from biju.lan ([2a00:23c4:a758:8a01:9cd9:f748:166d:55fc]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e1323034sm53160961f8f.35.2026.02.03.02.30.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Feb 2026 02:30:37 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Magnus Damm Cc: Biju Das , linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v3 06/10] clk: renesas: Add support for RZ/G3L SoC Date: Tue, 3 Feb 2026 10:30:14 +0000 Message-ID: <20260203103031.247435-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260203103031.247435-1-biju.das.jz@bp.renesas.com> References: <20260203103031.247435-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The clock structure for RZ/G3L is almost identical to RZ/G3S SoC with more IP blocks such as LCDC, CRU, LVDS and GPU. Add minimal clock and reset entries required to boot the system on Renesas RZ/G3L SMARC EVK and binds it with the RZ/G2L CPG core driver. Signed-off-by: Biju Das --- v2->v3: * No change. v1->v2: * Added CLK_ETH{0,1}_TXC_TX_CLK_IN and CLK_ETH{0,1}_RXC_RX_CLK_IN clocks. * Dropped R9A08G046_IA55_PCLK from critical clock list. --- drivers/clk/renesas/Kconfig | 7 +- drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r9a08g046-cpg.c | 144 ++++++++++++++++++++++++++++ drivers/clk/renesas/rzg2l-cpg.c | 6 ++ drivers/clk/renesas/rzg2l-cpg.h | 1 + 5 files changed, 158 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/renesas/r9a08g046-cpg.c diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 6a5a04664990..0203ecbb3882 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -39,6 +39,7 @@ config CLK_RENESAS select CLK_R9A07G044 if ARCH_R9A07G044 select CLK_R9A07G054 if ARCH_R9A07G054 select CLK_R9A08G045 if ARCH_R9A08G045 + select CLK_R9A08G046 if ARCH_R9A08G046 select CLK_R9A09G011 if ARCH_R9A09G011 select CLK_R9A09G047 if ARCH_R9A09G047 select CLK_R9A09G056 if ARCH_R9A09G056 @@ -194,6 +195,10 @@ config CLK_R9A08G045 bool "RZ/G3S clock support" if COMPILE_TEST select CLK_RZG2L =20 +config CLK_R9A08G046 + bool "RZ/G3L clock support" if COMPILE_TEST + select CLK_RZG2L + config CLK_R9A09G011 bool "RZ/V2M clock support" if COMPILE_TEST select CLK_RZG2L @@ -250,7 +255,7 @@ config CLK_RCAR_USB2_CLOCK_SEL This is a driver for R-Car USB2 clock selector =20 config CLK_RZG2L - bool "RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST + bool "RZ/{G2{L,UL},G3{S,L},V2L} family clock support" if COMPILE_TEST select RESET_CONTROLLER =20 config CLK_RZV2H diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index d28eb276a153..bd2bed91ab29 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_CLK_R9A07G043) +=3D r9a07g043-cpg.o obj-$(CONFIG_CLK_R9A07G044) +=3D r9a07g044-cpg.o obj-$(CONFIG_CLK_R9A07G054) +=3D r9a07g044-cpg.o obj-$(CONFIG_CLK_R9A08G045) +=3D r9a08g045-cpg.o +obj-$(CONFIG_CLK_R9A08G046) +=3D r9a08g046-cpg.o obj-$(CONFIG_CLK_R9A09G011) +=3D r9a09g011-cpg.o obj-$(CONFIG_CLK_R9A09G047) +=3D r9a09g047-cpg.o obj-$(CONFIG_CLK_R9A09G056) +=3D r9a09g056-cpg.o diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a0= 8g046-cpg.c new file mode 100644 index 000000000000..d77934872cf4 --- /dev/null +++ b/drivers/clk/renesas/r9a08g046-cpg.c @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/G3L CPG driver + * + * Copyright (C) 2026 Renesas Electronics Corp. + */ + +#include +#include +#include +#include + +#include + +#include "rzg2l-cpg.h" + +/* RZ/G3L Specific registers. */ +#define G3L_CPG_PL2_DDIV (0x204) +#define G3L_CPG_PL3_DDIV (0x208) +#define G3L_CLKDIVSTATUS (0x280) + +/* RZ/G3L Specific division configuration. */ +#define G3L_DIVPL2A DDIV_PACK(G3L_CPG_PL2_DDIV, 0, 2) +#define G3L_DIVPL2B DDIV_PACK(G3L_CPG_PL2_DDIV, 4, 2) +#define G3L_DIVPL3A DDIV_PACK(G3L_CPG_PL3_DDIV, 0, 2) + +/* RZ/G3L Clock status configuration. */ +#define G3L_DIVPL2A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 4, 1) +#define G3L_DIVPL2B_STS DDIV_PACK(G3L_CLKDIVSTATUS, 5, 1) +#define G3L_DIVPL3A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 8, 1) + +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK =3D R9A08G046_CLK_P4_DIV2, + + /* External Input Clocks */ + CLK_EXTAL, + CLK_ETH0_TXC_TX_CLK_IN, + CLK_ETH0_RXC_RX_CLK_IN, + CLK_ETH1_TXC_TX_CLK_IN, + CLK_ETH1_RXC_RX_CLK_IN, + + /* Internal Core Clocks */ + CLK_PLL2, + CLK_PLL2_DIV2, + CLK_PLL3, + CLK_PLL3_DIV2, + + /* Module Clocks */ + MOD_CLK_BASE, +}; + +/* Divider tables */ +static const struct clk_div_table dtable_4_128[] =3D { + { 0, 4 }, + { 1, 2 }, + { 2, 16 }, + { 3, 128 }, + { 0, 0 }, +}; + +static const struct clk_div_table dtable_8_256[] =3D { + { 0, 8 }, + { 1, 16 }, + { 2, 32 }, + { 3, 256 }, + { 0, 0 }, +}; + +static const struct cpg_core_clk r9a08g046_core_clks[] __initconst =3D { + /* External Clock Inputs */ + DEF_INPUT("extal", CLK_EXTAL), + DEF_INPUT("eth0_txc_tx_clk", CLK_ETH0_TXC_TX_CLK_IN), + DEF_INPUT("eth0_rxc_rx_clk", CLK_ETH0_RXC_RX_CLK_IN), + DEF_INPUT("eth1_txc_tx_clk", CLK_ETH1_TXC_TX_CLK_IN), + DEF_INPUT("eth1_rxc_rx_clk", CLK_ETH1_RXC_RX_CLK_IN), + + /* Internal Core Clocks */ + DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3), + DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3), + DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), + DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), + + /* Core output clk */ + DEF_G3S_DIV("P0", R9A08G046_CLK_P0, CLK_PLL2_DIV2, G3L_DIVPL2B, G3L_DIVPL= 2B_STS, + dtable_8_256, 0, 0, 0, NULL), + DEF_G3S_DIV("P1", R9A08G046_CLK_P1, CLK_PLL3_DIV2, G3L_DIVPL3A, G3L_DIVPL= 3A_STS, + dtable_4_128, 0, 0, 0, NULL), + DEF_G3S_DIV("P3", R9A08G046_CLK_P3, CLK_PLL2_DIV2, G3L_DIVPL2A, G3L_DIVPL= 2A_STS, + dtable_4_128, 0, 0, 0, NULL), +}; + +static const struct rzg2l_mod_clk r9a08g046_mod_clks[] =3D { + DEF_MOD("gic_gicclk", R9A08G046_GIC600_GICCLK, R9A08G046_CLK_P1, 0x514, = 0, + MSTOP(BUS_PERI_COM, BIT(12))), + DEF_MOD("ia55_pclk", R9A08G046_IA55_PCLK, R9A08G046_CLK_P0, 0x518, 0, + MSTOP(BUS_PERI_CPU, BIT(13))), + DEF_MOD("ia55_clk", R9A08G046_IA55_CLK, R9A08G046_CLK_P1, 0x518, 1, + MSTOP(BUS_PERI_CPU, BIT(13))), + DEF_MOD("dmac_aclk", R9A08G046_DMAC_ACLK, R9A08G046_CLK_P3, 0x52c, 0, + MSTOP(BUS_REG1, BIT(2))), + DEF_MOD("dmac_pclk", R9A08G046_DMAC_PCLK, R9A08G046_CLK_P3, 0x52c, 1, + MSTOP(BUS_REG1, BIT(3))), + DEF_MOD("scif0_clk_pck", R9A08G046_SCIF0_CLK_PCK, R9A08G046_CLK_P0, 0x584= , 0, + MSTOP(BUS_MCPU2, BIT(1))), +}; + +static const struct rzg2l_reset r9a08g046_resets[] =3D { + DEF_RST(R9A08G046_GIC600_GICRESET_N, 0x814, 0), + DEF_RST(R9A08G046_GIC600_DBG_GICRESET_N, 0x814, 1), + DEF_RST(R9A08G046_IA55_RESETN, 0x818, 0), + DEF_RST(R9A08G046_DMAC_ARESETN, 0x82c, 0), + DEF_RST(R9A08G046_DMAC_RST_ASYNC, 0x82c, 1), + DEF_RST(R9A08G046_SCIF0_RST_SYSTEM_N, 0x884, 0), +}; + +static const unsigned int r9a08g046_crit_mod_clks[] __initconst =3D { + MOD_CLK_BASE + R9A08G046_GIC600_GICCLK, + MOD_CLK_BASE + R9A08G046_IA55_CLK, + MOD_CLK_BASE + R9A08G046_DMAC_ACLK, +}; + +const struct rzg2l_cpg_info r9a08g046_cpg_info =3D { + /* Core Clocks */ + .core_clks =3D r9a08g046_core_clks, + .num_core_clks =3D ARRAY_SIZE(r9a08g046_core_clks), + .last_dt_core_clk =3D LAST_DT_CORE_CLK, + .num_total_core_clks =3D MOD_CLK_BASE, + + /* Critical Module Clocks */ + .crit_mod_clks =3D r9a08g046_crit_mod_clks, + .num_crit_mod_clks =3D ARRAY_SIZE(r9a08g046_crit_mod_clks), + + /* Module Clocks */ + .mod_clks =3D r9a08g046_mod_clks, + .num_mod_clks =3D ARRAY_SIZE(r9a08g046_mod_clks), + .num_hw_mod_clks =3D R9A08G046_BSC_X_BCK_BSC + 1, + + /* Resets */ + .resets =3D r9a08g046_resets, + .num_resets =3D R9A08G046_LVDS_RESET_N + 1, /* Last reset ID + 1 */ + + .has_clk_mon_regs =3D true, +}; diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cp= g.c index c0584bab58a3..f4deb5d3b837 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -2093,6 +2093,12 @@ static const struct of_device_id rzg2l_cpg_match[] = =3D { .data =3D &r9a08g045_cpg_info, }, #endif +#ifdef CONFIG_CLK_R9A08G046 + { + .compatible =3D "renesas,r9a08g046-cpg", + .data =3D &r9a08g046_cpg_info, + }, +#endif #ifdef CONFIG_CLK_R9A09G011 { .compatible =3D "renesas,r9a09g011-cpg", diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cp= g.h index 55e815be16c8..1db413bb433d 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -309,6 +309,7 @@ extern const struct rzg2l_cpg_info r9a07g043_cpg_info; extern const struct rzg2l_cpg_info r9a07g044_cpg_info; extern const struct rzg2l_cpg_info r9a07g054_cpg_info; extern const struct rzg2l_cpg_info r9a08g045_cpg_info; +extern const struct rzg2l_cpg_info r9a08g046_cpg_info; extern const struct rzg2l_cpg_info r9a09g011_cpg_info; =20 int rzg2l_cpg_sd_clk_mux_notifier(struct notifier_block *nb, unsigned long= event, void *data); --=20 2.43.0