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Tue, 3 Feb 2026 02:24:28 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Moshe Shemesh , Or Har-Toov , Jiri Pirko , Parav Pandit Subject: [PATCH net-next] net/mlx5: Support devlink port state for host PF Date: Tue, 3 Feb 2026 12:24:02 +0200 Message-ID: <20260203102402.1712218-1-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00022572:EE_|IA0PR12MB7650:EE_ X-MS-Office365-Filtering-Correlation-Id: afa2b08a-2b13-4a7d-8d2c-08de630e7596 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?utf-8?B?dzcxTEg2MEZjZTB5b0o2SGNuT280a2l2TjJDV3cxM2lsanhzSHJtNkxwUVpz?= =?utf-8?B?Wmo1UWE4cU1meUJ2L0xPekZ6ak1Nc3hQNFlCdWZlcTl3ZDRyTE1FNFhyZ1F6?= =?utf-8?B?dFBCWkJpSVd4QzRoNVlOc2M3Vis5ODFuOWhqTjBSbjBVK0NVeTlNSWoxWXln?= =?utf-8?B?dDhoU05NWktSakNwSWNLLzZMeDBWMWVvKzZGMkJNeEwwMW91TmtWVU5xMzQy?= =?utf-8?B?UE1xWjl0ZzE0YjUxQUxCTUdKOGljckwxMmpRTXphQmpDRWpERTNZWVBHUWMy?= =?utf-8?B?ZDNiVG9KakphOHZLV3hTL2JodjlodHdkTTZ2cmRYQkVWRUJndHBrdXNzZTEw?= =?utf-8?B?TkI1Z0JxVFN5Vnp0NjFnRXFYRUlhYlEvZzduQnJ6bERMaG1LRmZXTXFQdDUw?= =?utf-8?B?N3VYQUhWNmc2MXA5V1pycngvZHpDZGxVZW1mL3llU1F3ZGNQUmRmWjM4WkxS?= =?utf-8?B?ZDlOMHJZUUtXUXF5MkhLQ3A1bzZEcER3QmZxSDdkOU9WRis5K0RrY1djckRR?= =?utf-8?B?Ny9mWEh6R0lJYXRhek5HYmgwN3V4U1FYY25QVTJXdHNwS2dyUEI2SG1Jd1FN?= =?utf-8?B?OWdxLytBREpubVJ6ajE1amx5WHJoRllqcyt3WGg2SFlVVXJjc3hlK2RETHph?= =?utf-8?B?VXhvMnJHU0xKZG5EZnhYQVN2T09RMXU4aHhkVGo5ZWxwRWQ4QWJmNmJSNXAw?= =?utf-8?B?K0tIQ013OUdtMVRGNWRFNU9iSkIvYlRqWjB2M2s5dmVWVVZDdlM4clY3U0pE?= =?utf-8?B?NmEvZTBlWW5DZ2pPRllzcWI3OFk4clNrWmdyeDhHMzRhTjV4allvSUN6SlQ5?= =?utf-8?B?dXpIRTZ1YkVPdnJZOEVsT05YWjZlNEFyZmZqeGh5aE9SaVBWUlFhQS9Ed2Yr?= =?utf-8?B?MW4rQlcvUzZaT2JWS2FIVDRZL0FMVVI3UjE2VzlKeitucVBoRGRWa3ZZU3JT?= =?utf-8?B?R0QvWit4VW5JQkNPSzhMV2J2K1hZNFRWMWdQTkE1ZDh0cTdIUmFnZ2lpZ1h3?= =?utf-8?B?MnVqdXo5VTlDSXhWSUpxSThpdXBLdmpWREhuSHdSWDNUYnFSbmg3dkNuS3Ey?= =?utf-8?B?VHA3WDNxa0Rka1lvQVg4VzUzN1REWVN4d2RMYy83WncyMGFEQkVOR2Z5TENo?= =?utf-8?B?VHE4WW9Ydy9jOEIxOGxJZDQ1WCtkcFB0NHpmblBWT25HOHRaUktEbWpsNGNL?= =?utf-8?B?M3AxUm5KS29JK0pQSGtsMk1XV1M2enJqTElqOG5JYWV1cEx1Q1E4bTZKTTBu?= =?utf-8?B?cE1DSDhMOG4zZVA1aStLNEhDY3VvTUM1ellSSmVRNklJaW43RG5Ncy8xNTJo?= =?utf-8?B?eUU1dGwwNTNpQktyWjdYU3d5UDNGaU05UmwvcmFibDVRQ3JGaWpkYUF2K1Ew?= =?utf-8?B?TzU4MEpQbnIraDJ2b0xBQ2dwYmVtY3VDOEkwaFlCUkN4Y2VGdlROelp3M2cw?= =?utf-8?B?YzJIaDJSNlNoKzZ5bU5KeTRRR0xUSmZJS21iQkRMR0t6Uk9Vd1NodmhxbEJT?= =?utf-8?B?Rys2bFE4ZW1ZV1dhdkx0b2RVVFYvTUxUQ01BbkROMCtUWUx4QXBSZHFSb1pk?= =?utf-8?B?NHdyWHNJS2NBL3psaW1WaDVuamYvUzkvUzJUN1l4QndpOVhSaXVDbjNOUXZX?= =?utf-8?B?TEdlWWw2UlpQVENlNXlYT2Nma2l5QmhmTDJGc3IvYkVMMk4yb3d0YWFPUzl1?= =?utf-8?B?Z3BtdldWTHA0WFZpUklSdDlwMFFNdHdEa0JickpFSmJveTl2K2RqZmhCd0xN?= =?utf-8?B?ZFJ3TnUwSmhuV2gzTXBZTTMxL2g4UGZLWStoZzBWemdZMkdrNWpBL0pHeU0x?= =?utf-8?B?OGlpbjYwRVJWMHgvbHRoM1JWS1dBVHlOVVVEb0l1eExrYjBoNjBTcUd5ZWtk?= =?utf-8?B?WkVQeGZqUVRSQUhBOFJWMjVVZUxQSW5USGptSThzR0oxRXpFdERwSXY2SEFz?= =?utf-8?B?V1VWVGVSeEpYNDNyRWE3Mm5jT1loeGdKMW9pbFNhSFRmUVkvVXZJQ2tzUURh?= =?utf-8?B?b2NhOFBsSStwMEYyOE1Zb0t1clQ2L0pZUjlEZmoxNTVPeDc4LzhnVkFEL1kw?= =?utf-8?B?N0d0dVFQRXg4MllydUhEMzlKRkhqUVBSRC9vaXZaMXRtQlRjelBNVHIzb29C?= =?utf-8?B?MFVRZU1HdzJIaWc5WWowcFJnNWk0ZkJ4bFJhdUlWRDRkSGYvQzU4U2syZ2Jr?= =?utf-8?B?bFZIV3UySU5vT2lUNW14OWNxeWZybDA1WHU2NTRKcmYzUUNUcEdpNTRQdE1u?= =?utf-8?B?Wm1Od1ZwK01HYUdkdi9ZcHdqeU5RPT0=?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: s6rCk0vOu997jU0Ez5Dp3IPH+SoyCrpQL7116Ldug+jd6rZ05uXZlU2YRLBDeW3gxYg1sjq0zRjvDkiUmHwa58JaQ7IXL55ZZLDwkjDJJGwduj3Y8PhWkm0H8ImZRUJ/X1L94Uf/xaqyb7f1iugr57dt8g3G+QxW/b9tF7ImacmYvKKxk8NKpKnk0s3aGTLaeDAdLZjp8tqWqTGLcyemLfm0QKLYlCS5sVNwWiPZLpqXoOQiraOUIe1egDl4mh0V2/EQESRTZRckwejUKcjikW9mIdrbR75FWCVWP0jAzmxSFdQH/Xb7ZoIHNQk2bhEgcCPS0A+mJudWIcX7hxjofdH2aNEmzK920ARTWUk7287HjY3+dQFAe27WuzdC1RVJaNqJ/EJNGwNDFGi6K89EX21FSEnN6br8wlfBKQFrx7qBNFvofImXUAT+JBzx3iyC X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2026 10:24:48.4883 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: afa2b08a-2b13-4a7d-8d2c-08de630e7596 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00022572.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7650 From: Moshe Shemesh Add support for devlink port function state get/set operations for the host physical function (PF). Until now, mlx5 only allowed state get/set for subfunctions (SFs) ports. This change enables an administrator with eSwitch manager privileges to query or modify the host PF=E2=80=99s function state, allowing it to be explicitly inactivated or activated. While inactivated, the administrator can modify the functions attributes, such as enable/disable roce. $ devlink port show pci/0000:03:00.0/196608 pci/0000:03:00.0/196608: type eth netdev eth1 flavour pcipf controller 1 pf= num 0 external true splittable false function: hw_addr a0:88:c2:45:17:7c state active opstate attached roce enable max= _io_eqs 120 $ devlink port function set pci/0000:03:00.0/196608 state inactive $ devlink port show pci/0000:03:00.0/196608 pci/0000:03:00.0/196608: type eth netdev eth1 flavour pcipf controller 1 pf= num 0 external true splittable false function: hw_addr a0:88:c2:45:17:7c state inactive opstate detached roce enable m= ax_io_eqs 120 Signed-off-by: Moshe Shemesh Reviewed-by: Mark Bloch Reviewed-by: Parav Pandit Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/ecpf.c | 5 +- .../mellanox/mlx5/core/esw/devlink_port.c | 2 + .../net/ethernet/mellanox/mlx5/core/eswitch.c | 48 ++++++++++++---- .../net/ethernet/mellanox/mlx5/core/eswitch.h | 10 ++++ .../mellanox/mlx5/core/eswitch_offloads.c | 55 +++++++++++++++++++ 5 files changed, 108 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/ecpf.c b/drivers/net/e= thernet/mellanox/mlx5/core/ecpf.c index d000236ddbac..15cb27aea2c9 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/ecpf.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/ecpf.c @@ -2,6 +2,7 @@ /* Copyright (c) 2019 Mellanox Technologies. */ =20 #include "ecpf.h" +#include "eswitch.h" =20 bool mlx5_read_embedded_cpu(struct mlx5_core_dev *dev) { @@ -49,7 +50,7 @@ static int mlx5_host_pf_init(struct mlx5_core_dev *dev) /* ECPF shall enable HCA for host PF in the same way a PF * does this for its VFs when ECPF is not a eswitch manager. */ - err =3D mlx5_cmd_host_pf_enable_hca(dev); + err =3D mlx5_esw_host_pf_enable_hca(dev); if (err) mlx5_core_err(dev, "Failed to enable external host PF HCA err(%d)\n", er= r); =20 @@ -63,7 +64,7 @@ static void mlx5_host_pf_cleanup(struct mlx5_core_dev *de= v) if (mlx5_ecpf_esw_admins_host_pf(dev)) return; =20 - err =3D mlx5_cmd_host_pf_disable_hca(dev); + err =3D mlx5_esw_host_pf_disable_hca(dev); if (err) { mlx5_core_err(dev, "Failed to disable external host PF HCA err(%d)\n", e= rr); return; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c b/d= rivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c index 89a58dee50b3..cd60bc500ec5 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c @@ -99,6 +99,8 @@ static const struct devlink_port_ops mlx5_esw_pf_vf_dl_po= rt_ops =3D { .port_fn_roce_set =3D mlx5_devlink_port_fn_roce_set, .port_fn_migratable_get =3D mlx5_devlink_port_fn_migratable_get, .port_fn_migratable_set =3D mlx5_devlink_port_fn_migratable_set, + .port_fn_state_get =3D mlx5_devlink_pf_port_fn_state_get, + .port_fn_state_set =3D mlx5_devlink_pf_port_fn_state_set, #ifdef CONFIG_XFRM_OFFLOAD .port_fn_ipsec_crypto_get =3D mlx5_devlink_port_fn_ipsec_crypto_get, .port_fn_ipsec_crypto_set =3D mlx5_devlink_port_fn_ipsec_crypto_set, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.c index 4b7a1ce7f406..5fbfabe28bdb 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c @@ -1304,24 +1304,52 @@ static int mlx5_eswitch_load_ec_vf_vports(struct ml= x5_eswitch *esw, u16 num_ec_v return err; } =20 -static int host_pf_enable_hca(struct mlx5_core_dev *dev) +int mlx5_esw_host_pf_enable_hca(struct mlx5_core_dev *dev) { - if (!mlx5_core_is_ecpf(dev)) + struct mlx5_eswitch *esw =3D dev->priv.eswitch; + struct mlx5_vport *vport; + int err; + + if (!mlx5_core_is_ecpf(dev) || !mlx5_esw_allowed(esw)) return 0; =20 + vport =3D mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF); + if (IS_ERR(vport)) + return PTR_ERR(vport); + /* Once vport and representor are ready, take out the external host PF * out of initializing state. Enabling HCA clears the iser->initializing * bit and host PF driver loading can progress. */ - return mlx5_cmd_host_pf_enable_hca(dev); + err =3D mlx5_cmd_host_pf_enable_hca(dev); + if (err) + return err; + + vport->pf_activated =3D true; + + return 0; } =20 -static void host_pf_disable_hca(struct mlx5_core_dev *dev) +int mlx5_esw_host_pf_disable_hca(struct mlx5_core_dev *dev) { - if (!mlx5_core_is_ecpf(dev)) - return; + struct mlx5_eswitch *esw =3D dev->priv.eswitch; + struct mlx5_vport *vport; + int err; =20 - mlx5_cmd_host_pf_disable_hca(dev); + if (!mlx5_core_is_ecpf(dev) || !mlx5_esw_allowed(esw)) + return 0; + + vport =3D mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF); + if (IS_ERR(vport)) + return PTR_ERR(vport); + + err =3D mlx5_cmd_host_pf_disable_hca(dev); + if (err) + return err; + + vport->pf_activated =3D false; + + return 0; } =20 /* mlx5_eswitch_enable_pf_vf_vports() enables vports of PF, ECPF and VFs @@ -1347,7 +1375,7 @@ mlx5_eswitch_enable_pf_vf_vports(struct mlx5_eswitch = *esw, =20 if (mlx5_esw_host_functions_enabled(esw->dev)) { /* Enable external host PF HCA */ - ret =3D host_pf_enable_hca(esw->dev); + ret =3D mlx5_esw_host_pf_enable_hca(esw->dev); if (ret) goto pf_hca_err; } @@ -1391,7 +1419,7 @@ mlx5_eswitch_enable_pf_vf_vports(struct mlx5_eswitch = *esw, mlx5_eswitch_unload_pf_vf_vport(esw, MLX5_VPORT_ECPF); ecpf_err: if (mlx5_esw_host_functions_enabled(esw->dev)) - host_pf_disable_hca(esw->dev); + mlx5_esw_host_pf_disable_hca(esw->dev); pf_hca_err: if (pf_needed && mlx5_esw_host_functions_enabled(esw->dev)) mlx5_eswitch_unload_pf_vf_vport(esw, MLX5_VPORT_PF); @@ -1416,7 +1444,7 @@ void mlx5_eswitch_disable_pf_vf_vports(struct mlx5_es= witch *esw) } =20 if (mlx5_esw_host_functions_enabled(esw->dev)) - host_pf_disable_hca(esw->dev); + mlx5_esw_host_pf_disable_hca(esw->dev); =20 if ((mlx5_core_is_ecpf_esw_manager(esw->dev) || esw->mode =3D=3D MLX5_ESWITCH_LEGACY) && diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.h index 714ad28e8445..6841caef02d1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -243,6 +243,7 @@ struct mlx5_vport { u16 vport; bool enabled; bool max_eqs_set; + bool pf_activated; enum mlx5_eswitch_vport_event enabled_events; int index; struct mlx5_devlink_port *dl_port; @@ -587,6 +588,13 @@ int mlx5_devlink_port_fn_migratable_get(struct devlink= _port *port, bool *is_enab struct netlink_ext_ack *extack); int mlx5_devlink_port_fn_migratable_set(struct devlink_port *port, bool en= able, struct netlink_ext_ack *extack); +int mlx5_devlink_pf_port_fn_state_get(struct devlink_port *port, + enum devlink_port_fn_state *state, + enum devlink_port_fn_opstate *opstate, + struct netlink_ext_ack *extack); +int mlx5_devlink_pf_port_fn_state_set(struct devlink_port *port, + enum devlink_port_fn_state state, + struct netlink_ext_ack *extack); #ifdef CONFIG_XFRM_OFFLOAD int mlx5_devlink_port_fn_ipsec_crypto_get(struct devlink_port *port, bool = *is_enabled, struct netlink_ext_ack *extack); @@ -634,6 +642,8 @@ bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *de= v0, struct mlx5_core_dev *dev1); =20 const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev); +int mlx5_esw_host_pf_enable_hca(struct mlx5_core_dev *dev); +int mlx5_esw_host_pf_disable_hca(struct mlx5_core_dev *dev); =20 void mlx5_esw_adjacent_vhcas_setup(struct mlx5_eswitch *esw); void mlx5_esw_adjacent_vhcas_cleanup(struct mlx5_eswitch *esw); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/d= rivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index 02b7e474586d..1b439cef3719 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -4696,6 +4696,61 @@ int mlx5_devlink_port_fn_roce_set(struct devlink_por= t *port, bool enable, return err; } =20 +int mlx5_devlink_pf_port_fn_state_get(struct devlink_port *port, + enum devlink_port_fn_state *state, + enum devlink_port_fn_opstate *opstate, + struct netlink_ext_ack *extack) +{ + struct mlx5_vport *vport =3D mlx5_devlink_port_vport_get(port); + const u32 *query_out; + bool pf_disabled; + + if (vport->vport !=3D MLX5_VPORT_PF) { + NL_SET_ERR_MSG_MOD(extack, "State get is not supported for VF"); + return -EOPNOTSUPP; + } + + *state =3D vport->pf_activated ? + DEVLINK_PORT_FN_STATE_ACTIVE : DEVLINK_PORT_FN_STATE_INACTIVE; + + query_out =3D mlx5_esw_query_functions(vport->dev); + if (IS_ERR(query_out)) + return PTR_ERR(query_out); + + pf_disabled =3D MLX5_GET(query_esw_functions_out, query_out, + host_params_context.host_pf_disabled); + + *opstate =3D pf_disabled ? DEVLINK_PORT_FN_OPSTATE_DETACHED : + DEVLINK_PORT_FN_OPSTATE_ATTACHED; + + kvfree(query_out); + return 0; +} + +int mlx5_devlink_pf_port_fn_state_set(struct devlink_port *port, + enum devlink_port_fn_state state, + struct netlink_ext_ack *extack) +{ + struct mlx5_vport *vport =3D mlx5_devlink_port_vport_get(port); + struct mlx5_core_dev *dev; + + if (vport->vport !=3D MLX5_VPORT_PF) { + NL_SET_ERR_MSG_MOD(extack, "State set is not supported for VF"); + return -EOPNOTSUPP; + } + + dev =3D vport->dev; + + switch (state) { + case DEVLINK_PORT_FN_STATE_ACTIVE: + return mlx5_esw_host_pf_enable_hca(dev); + case DEVLINK_PORT_FN_STATE_INACTIVE: + return mlx5_esw_host_pf_disable_hca(dev); + default: + return -EOPNOTSUPP; + } +} + int mlx5_eswitch_restore_ipsec_rule(struct mlx5_eswitch *esw, struct mlx5_flow= _handle *rule, struct mlx5_esw_flow_attr *esw_attr, int attr_idx) base-commit: fae1c659d7bd5640012be21b5b5d6490b83c0df8 --=20 2.44.0