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Mon, 2 Feb 2026 23:30:41 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Moshe Shemesh , Alexei Lazar , Dragos Tatulea Subject: [PATCH net-next] net/mlx5e: Extend TC max ratelimit Date: Tue, 3 Feb 2026 09:30:20 +0200 Message-ID: <20260203073021.1710806-1-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA4C:EE_|CY8PR12MB8241:EE_ X-MS-Office365-Filtering-Correlation-Id: 40abe4b3-fcd4-49b3-3bab-08de62f62e93 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?y7VDyG0NcrK5l3Mi8rTcanz0ehBtHk/Kp7yez+K3gmb9TxPJyi2vy3rbMHka?= =?us-ascii?Q?aeBRzgQE/C+zBZ8bH0DgAHR3xOw7amlTXFw6EeAgE43+9iAZMy4bpT0oTM5r?= =?us-ascii?Q?JgJxJ/VP6XZnfngB60Q3dca8EEuzV/AY/gx0OuU6cgp+yU7IB1iczYiJohU5?= =?us-ascii?Q?wypKH8G35iMJdgexWgoX13udAeEpfhoHtWfzzI0utOoc2GRjNFjVoCunKaeS?= =?us-ascii?Q?hmVVoUPU5rV8nMzkQ4Xy3bRLhxk9kmOhZWwb3e06k0f5gx/cgCQaQBIa5dey?= =?us-ascii?Q?ysTfUPCUN55b+9cfnUDnqH41Zspmw+puqeXsxw562d4K0TT6hJ27zJRGigHe?= =?us-ascii?Q?yxkRuahzSW+PyXmd8U4+yTYXVQ+Lr5FFh6or0N3bdJI4EGp3CWvIz+k58heO?= =?us-ascii?Q?lutwjLbelpQWonz1xMys7VUw2uS2lH5lKed7t3qqdxOXwyTRjF0U2OKekmEd?= =?us-ascii?Q?eNfMuCQrM2zOes1H3bagStp9dAuzvZM7Nt7z+WCmj919oVHAjNxa6noqF2Hk?= =?us-ascii?Q?lY5qFNqllOiaJvcNUl3i4woX5+xrmKkpgq6PNxZd3h6DNyuqbN4G76W5XJFL?= =?us-ascii?Q?hWvWMrN3bpRs1VRH3mEQWB3ZT/U67Yl33Q6nCoiAOU/O3B9SAlbSUowRuEyH?= =?us-ascii?Q?DJI/+haZz/G3vlJGhA/dbU4OqVeEXdUmeqHC77DiZ7z+LVeAvNmYcGgd0ORv?= =?us-ascii?Q?6cdxE/4urbuDhd8kHsmHlcN/DtVfIdDQh2CKObNfVMUGU2lsc/k/UG/E8eef?= =?us-ascii?Q?0V5Z7Y2XDKEpef+Fb1RiFIxAZooJkX8YTvLbyAw3pdIdxtPVPQZ1UfKuoRyZ?= =?us-ascii?Q?hTG6/Z/ggC3wHnLelW0jXtsJ9lunUKmpKWV1ykMGqGZnTGFmk56XZ1I+IoYr?= =?us-ascii?Q?KyzAdA0s7MEOVoTnj5gNP5Ec0SkQJiRRnfVYAHGJC9hj+966Xvdk0fZlZUcA?= =?us-ascii?Q?7ySG57zrnUZPIn6jLCba4KggQJbEmk/2j29KDHIO0k0A80nSeQdcH+z4JZH1?= =?us-ascii?Q?JJi/j6NZVvHCMHjkoF5pZkZVlvvt3rpdo0opw1jPPyb8y6mPHkZAARKDcJ+A?= =?us-ascii?Q?oLWRM/+k3J0lsie2UEFJ5KVd88PWVqU9mPIf7fI3WGbCQM8V4kk4Xzt77IKs?= =?us-ascii?Q?V1NqgvGaSd3Lm3+IQe6JspoohinOMzCz7lQGGRFLuaMsLKtCaLd/4ekG/7wL?= =?us-ascii?Q?PXKTwavVoUvIdL8Qy0Qmt+5bplGk6WL48XjXOvt0uTW/OFvEHUOYPjFv8BFr?= =?us-ascii?Q?v+QNrIIawb2xKuWO1IRaPs1pk1T9Znqog2dlkI8DlUxfA6IZxa6WfZypQ/EK?= =?us-ascii?Q?FSc/ldawWH7UKwieCI8jeyQ+0DUEmod7i65N+uy3ycpHySg5DkAQKIVicSMk?= =?us-ascii?Q?1v8mCjvfmD20WkHe5BLXklWAoN2YXO7yPNtmN2u7MbcR0HeTQSn9K0gMl7Tk?= =?us-ascii?Q?guU+kVmqYb7XCI3PU7u2oy9kMH9nPLIo3ZvfUjNEzU1GTJQUjpkkNiwrJhHX?= =?us-ascii?Q?iiG1EXMTMdDXF1LVGELC/akDyKX610JQO7uc4dVDGMRefiThyMddCDE7Y9Xy?= =?us-ascii?Q?QUTx/3zydgi6X0IsJ8VUMdaKJCS8ClGDSzel/Ril5pALJUX98jk+EMBWNF9i?= =?us-ascii?Q?4LUlWy4anGZdiqIfhBuMuBJFkMsUMXyehIJCk06Dme/sMO9rGNGR9rX2m5xS?= =?us-ascii?Q?/nCD3Q=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: nShIYW4BXMh/oitAXKlD+UcOGcH5tBTd7WIyeswomSdzxudE+cZWYQr+2tr78jcDVDKYW3jrLnpTNnAkU834OdkTBQFrYV+O6P0IV9GwHh8uRkVWqZ9qbTm1zNoqP8WjVp9j0DMASA7N+MDCxaPZM7x5Nfn65FV5NY19lYM9Guw1qrCMm8jnRmY+enVUa6oPuigpwHUCey/B4CqBgdUv7i0RQGrIe6B/a1PEQ7nr1yhcZrUhheFgEsfSpjDBk/YswrSfudqZ1u7acM5iRWgUN9Ip8dei8GBA16MRnj14hFxDzXQueaLQ/pYzMe8mw8uWiu5DFp02yiuX/MDc7QQ1g/SZj0oTwTY4yBUdR25HfYYUeiDKxMMxLjxLUXPbagPdL512Haj6b1F27U8MoQdHjgPCDiX32Lm9FTtAG8cXoEyo5HHxBky2YMpAIkqa46CS X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2026 07:31:01.4644 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 40abe4b3-fcd4-49b3-3bab-08de62f62e93 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA4C.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8241 Content-Type: text/plain; charset="utf-8" From: Alexei Lazar The per-TC rate limit was restricted to 255 Gbps due to the 8-bit max_bw_value field in the QETC register. This limit is insufficient for newer, higher-bandwidth NICs. Extend the rate limit by using the full 16-bit max_bw_value field. This allows the finer 100Mbps granularity to be used for rates up to ~6.5 Tbps, instead of switching to 1Gbps granularity at higher rates. The extended range is only used when the device advertises support via the qetcr_qshr_max_bw_val_msb capability bit in the QCAM register. Signed-off-by: Alexei Lazar Reviewed-by: Dragos Tatulea Reviewed-by: Gal Pressman Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/en/dcbnl.h | 4 ++ .../ethernet/mellanox/mlx5/core/en_dcbnl.c | 66 ++++++++++--------- .../ethernet/mellanox/mlx5/core/mlx5_core.h | 4 +- .../net/ethernet/mellanox/mlx5/core/port.c | 4 +- 4 files changed, 44 insertions(+), 34 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/dcbnl.h b/drivers/n= et/ethernet/mellanox/mlx5/core/en/dcbnl.h index 2c98a5299df3..6bd959f9083d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/dcbnl.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/dcbnl.h @@ -29,6 +29,10 @@ struct mlx5e_dcbx { u32 cable_len; u32 xoff; u16 port_buff_cell_sz; + + /* Upper limit for 100Mbps and 1Gbps in Kbps units */ + u64 upper_limit_100mbps; + u64 upper_limit_gbps; }; =20 #define MLX5E_MAX_DSCP (64) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c b/drivers/n= et/ethernet/mellanox/mlx5/core/en_dcbnl.c index fddf7c207f8e..4b86df6d5b9e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c @@ -58,6 +58,20 @@ enum { MLX5_DCB_CHG_NO_RESET, }; =20 +static const struct { + int scale; + const char *units_str; +} mlx5e_bw_units[] =3D { + [MLX5_100_MBPS_UNIT] =3D { + .scale =3D 100, + .units_str =3D "Mbps", + }, + [MLX5_GBPS_UNIT] =3D { + .scale =3D 1, + .units_str =3D "Gbps", + }, +}; + #define MLX5_DSCP_SUPPORTED(mdev) (MLX5_CAP_GEN(mdev, qcam_reg) && \ MLX5_CAP_QCAM_REG(mdev, qpts) && \ MLX5_CAP_QCAM_REG(mdev, qpdpm)) @@ -559,7 +573,7 @@ static int mlx5e_dcbnl_ieee_getmaxrate(struct net_devic= e *netdev, { struct mlx5e_priv *priv =3D netdev_priv(netdev); struct mlx5_core_dev *mdev =3D priv->mdev; - u8 max_bw_value[IEEE_8021QAZ_MAX_TCS]; + u16 max_bw_value[IEEE_8021QAZ_MAX_TCS]; u8 max_bw_unit[IEEE_8021QAZ_MAX_TCS]; int err; int i; @@ -594,57 +608,41 @@ static int mlx5e_dcbnl_ieee_setmaxrate(struct net_dev= ice *netdev, { struct mlx5e_priv *priv =3D netdev_priv(netdev); struct mlx5_core_dev *mdev =3D priv->mdev; - u8 max_bw_value[IEEE_8021QAZ_MAX_TCS]; + u16 max_bw_value[IEEE_8021QAZ_MAX_TCS]; u8 max_bw_unit[IEEE_8021QAZ_MAX_TCS]; - u64 upper_limit_100mbps; - u64 upper_limit_gbps; int i; - struct { - int scale; - const char *units_str; - } units[] =3D { - [MLX5_100_MBPS_UNIT] =3D { - .scale =3D 100, - .units_str =3D "Mbps", - }, - [MLX5_GBPS_UNIT] =3D { - .scale =3D 1, - .units_str =3D "Gbps", - }, - }; =20 memset(max_bw_value, 0, sizeof(max_bw_value)); memset(max_bw_unit, 0, sizeof(max_bw_unit)); - upper_limit_100mbps =3D U8_MAX * MLX5E_100MB_TO_KB; - upper_limit_gbps =3D U8_MAX * MLX5E_1GB_TO_KB; =20 for (i =3D 0; i <=3D mlx5_max_tc(mdev); i++) { - if (!maxrate->tc_maxrate[i]) { + u64 rate =3D maxrate->tc_maxrate[i]; + + if (!rate) { max_bw_unit[i] =3D MLX5_BW_NO_LIMIT; continue; } - if (maxrate->tc_maxrate[i] <=3D upper_limit_100mbps) { - max_bw_value[i] =3D div_u64(maxrate->tc_maxrate[i], - MLX5E_100MB_TO_KB); + if (rate <=3D priv->dcbx.upper_limit_100mbps) { + max_bw_value[i] =3D div_u64(rate, MLX5E_100MB_TO_KB); max_bw_value[i] =3D max_bw_value[i] ? max_bw_value[i] : 1; max_bw_unit[i] =3D MLX5_100_MBPS_UNIT; - } else if (maxrate->tc_maxrate[i] <=3D upper_limit_gbps) { - max_bw_value[i] =3D div_u64(maxrate->tc_maxrate[i], - MLX5E_1GB_TO_KB); + } else if (rate <=3D priv->dcbx.upper_limit_gbps) { + max_bw_value[i] =3D div_u64(rate, MLX5E_1GB_TO_KB); max_bw_unit[i] =3D MLX5_GBPS_UNIT; } else { netdev_err(netdev, "tc_%d maxrate %llu Kbps exceeds limit %llu\n", - i, maxrate->tc_maxrate[i], - upper_limit_gbps); + i, rate, priv->dcbx.upper_limit_gbps); return -EINVAL; } } =20 for (i =3D 0; i < IEEE_8021QAZ_MAX_TCS; i++) { + u8 unit =3D max_bw_unit[i]; + netdev_dbg(netdev, "%s: tc_%d <=3D> max_bw %u %s\n", __func__, i, - max_bw_value[i] * units[max_bw_unit[i]].scale, - units[max_bw_unit[i]].units_str); + max_bw_value[i] * mlx5e_bw_units[unit].scale, + mlx5e_bw_units[unit].units_str); } =20 return mlx5_modify_port_ets_rate_limit(mdev, max_bw_value, max_bw_unit); @@ -1268,6 +1266,8 @@ static u16 mlx5e_query_port_buffers_cell_size(struct = mlx5e_priv *priv) void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv) { struct mlx5e_dcbx *dcbx =3D &priv->dcbx; + bool max_bw_msb_supported; + u16 type_max; =20 mlx5e_trust_initialize(priv); =20 @@ -1285,5 +1285,11 @@ void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv) priv->dcbx.port_buff_cell_sz =3D mlx5e_query_port_buffers_cell_size(priv); priv->dcbx.cable_len =3D MLX5E_DEFAULT_CABLE_LEN; =20 + max_bw_msb_supported =3D MLX5_CAP_QCAM_FEATURE(priv->mdev, + qetcr_qshr_max_bw_val_msb); + type_max =3D max_bw_msb_supported ? U16_MAX : U8_MAX; + priv->dcbx.upper_limit_100mbps =3D type_max * MLX5E_100MB_TO_KB; + priv->dcbx.upper_limit_gbps =3D type_max * MLX5E_1GB_TO_KB; + mlx5e_ets_init(priv); } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h b/drivers/= net/ethernet/mellanox/mlx5/core/mlx5_core.h index e4b0aa16c1d2..b635b423d972 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h @@ -345,10 +345,10 @@ int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *m= dev, u8 *tc_bw); int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 tc, u8 *bw_pct); int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev, - u8 *max_bw_value, + u16 *max_bw_value, u8 *max_bw_unit); int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev, - u8 *max_bw_value, + u16 *max_bw_value, u8 *max_bw_unit); int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode); int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/port.c b/drivers/net/e= thernet/mellanox/mlx5/core/port.c index e8a0884ea477..9fca591652f2 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/port.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/port.c @@ -773,7 +773,7 @@ int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *m= dev, } =20 int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev, - u8 *max_bw_value, + u16 *max_bw_value, u8 *max_bw_units) { u32 in[MLX5_ST_SZ_DW(qetc_reg)] =3D {0}; @@ -796,7 +796,7 @@ int mlx5_modify_port_ets_rate_limit(struct mlx5_core_de= v *mdev, } =20 int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev, - u8 *max_bw_value, + u16 *max_bw_value, u8 *max_bw_units) { u32 out[MLX5_ST_SZ_DW(qetc_reg)]; base-commit: a22f57757f7e88c890499265c383ecb32900b645 --=20 2.44.0