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charset="utf-8" CXL virtual hierarchy (VH) RAS handling for CXL Port devices will be added soon. This requires a notification mechanism for the AER driver to share the AER interrupt with the CXL driver. The notification will be used as an indication for the CXL drivers to handle and log the CXL RAS errors. Note, 'CXL protocol error' terminology will refer to CXL VH and not CXL RCH errors unless specifically noted going forward. Introduce a new file in the AER driver to handle the CXL protocol errors named pci/pcie/aer_cxl_vh.c. Add a kfifo work queue to be used by the AER and CXL drivers. The AER driver will be the sole kfifo producer adding work and the cxl_core will be the sole kfifo consumer removing work. Add the boilerplate kfifo support. Encapsulate the kfifo, RW semaphore, and work pointer in a single structure. Add CXL work queue handler registration functions in the AER driver. Export the functions allowing CXL driver to access. Implement registration functions for the CXL driver to assign or clear the work handler function. Synchronize accesses using the RW semaphore. Introduce 'struct cxl_proto_err_work_data' to serve as the kfifo work data. This will contain a reference to the PCI error source device and the error severity. This will be used when the work is dequeued by the cxl_core drive= r. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang Reviewed-by: Dan Williams --- Changes in v14->v15: - Moved pci_dev_get() call to this patch (Dave) Changes in v13 -> v14: - Replaced workqueue_types.h include with 'struct work_struct' predeclaration (Bjorn) - Update error message (Bjorn) - Reordered 'struct cxl_proto_err_work_data' (Bjorn) - Remove export of cxl_error_is_native() here (Bjorn) Changes in v12->v13: - Added Dave Jiang's review-by - Update error message (Ben) Changes in v11->v12: - None Changes in v10->v11: - cxl_error_detected() - Change handlers' scoped_guard() to guard() (Jonath= an) - cxl_error_detected() - Remove extra line (Shiju) - Changes moved to core/ras.c (Terry) - cxl_error_detected(), remove 'ue' and return with function call. (Jonatha= n) - Remove extra space in documentation for PCI_ERS_RESULT_PANIC definition - Move #include "pci.h from cxl.h to core.h (Terry) - Remove unnecessary includes of cxl.h and core.h in mem.c (Terry) --- drivers/pci/pcie/Makefile | 1 + drivers/pci/pcie/aer.c | 15 ++----- drivers/pci/pcie/aer_cxl_vh.c | 79 +++++++++++++++++++++++++++++++++++ drivers/pci/pcie/portdrv.h | 4 ++ include/linux/aer.h | 22 ++++++++++ 5 files changed, 110 insertions(+), 11 deletions(-) create mode 100644 drivers/pci/pcie/aer_cxl_vh.c diff --git a/drivers/pci/pcie/Makefile b/drivers/pci/pcie/Makefile index b0b43a18c304..62d3d3c69a5d 100644 --- a/drivers/pci/pcie/Makefile +++ b/drivers/pci/pcie/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_PCIEPORTBUS) +=3D pcieportdrv.o bwctrl.o obj-y +=3D aspm.o obj-$(CONFIG_PCIEAER) +=3D aer.o err.o tlp.o obj-$(CONFIG_CXL_RAS) +=3D aer_cxl_rch.o +obj-$(CONFIG_CXL_RAS) +=3D aer_cxl_vh.o obj-$(CONFIG_PCIEAER_INJECT) +=3D aer_inject.o obj-$(CONFIG_PCIE_PME) +=3D pme.o obj-$(CONFIG_PCIE_DPC) +=3D dpc.o diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 49a4bd13c2d2..7af10a74da34 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1155,16 +1155,6 @@ void pci_aer_unmask_internal_errors(struct pci_dev *= dev) */ EXPORT_SYMBOL_FOR_MODULES(pci_aer_unmask_internal_errors, "cxl_core"); =20 -#ifdef CONFIG_CXL_RAS -bool is_aer_internal_error(struct aer_err_info *info) -{ - if (info->severity =3D=3D AER_CORRECTABLE) - return info->status & PCI_ERR_COR_INTERNAL; - - return info->status & PCI_ERR_UNC_INTN; -} -#endif - /** * pci_aer_handle_error - handle logging error into an event log * @dev: pointer to pci_dev data structure of error source device @@ -1201,7 +1191,10 @@ static void pci_aer_handle_error(struct pci_dev *dev= , struct aer_err_info *info) static void handle_error_source(struct pci_dev *dev, struct aer_err_info *= info) { cxl_rch_handle_error(dev, info); - pci_aer_handle_error(dev, info); + if (is_cxl_error(dev, info)) + cxl_forward_error(dev, info); + else + pci_aer_handle_error(dev, info); pci_dev_put(dev); } =20 diff --git a/drivers/pci/pcie/aer_cxl_vh.c b/drivers/pci/pcie/aer_cxl_vh.c new file mode 100644 index 000000000000..de8bca383159 --- /dev/null +++ b/drivers/pci/pcie/aer_cxl_vh.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright(c) 2025 AMD Corporation. All rights reserved. */ + +#include +#include +#include +#include +#include "../pci.h" +#include "portdrv.h" + +#define CXL_ERROR_SOURCES_MAX 128 + +struct cxl_proto_err_kfifo { + struct work_struct *work; + struct rw_semaphore rw_sema; + DECLARE_KFIFO(fifo, struct cxl_proto_err_work_data, + CXL_ERROR_SOURCES_MAX); +}; + +static struct cxl_proto_err_kfifo cxl_proto_err_kfifo =3D { + .rw_sema =3D __RWSEM_INITIALIZER(cxl_proto_err_kfifo.rw_sema) +}; + +bool is_aer_internal_error(struct aer_err_info *info) +{ + if (info->severity =3D=3D AER_CORRECTABLE) + return info->status & PCI_ERR_COR_INTERNAL; + + return info->status & PCI_ERR_UNC_INTN; +} + +bool is_cxl_error(struct pci_dev *pdev, struct aer_err_info *info) +{ + if (!info || !info->is_cxl) + return false; + + if (pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_ENDPOINT) + return false; + + return is_aer_internal_error(info); +} + +void cxl_forward_error(struct pci_dev *pdev, struct aer_err_info *info) +{ + struct cxl_proto_err_work_data wd =3D (struct cxl_proto_err_work_data) { + .severity =3D info->severity, + .pdev =3D pdev + }; + + guard(rwsem_read)(&cxl_proto_err_kfifo.rw_sema); + pci_dev_get(pdev); + if (!cxl_proto_err_kfifo.work || !kfifo_put(&cxl_proto_err_kfifo.fifo, wd= )) { + dev_err_ratelimited(&pdev->dev, "AER-CXL kfifo error"); + return; + } + + schedule_work(cxl_proto_err_kfifo.work); +} + +void cxl_register_proto_err_work(struct work_struct *work) +{ + guard(rwsem_write)(&cxl_proto_err_kfifo.rw_sema); + cxl_proto_err_kfifo.work =3D work; +} +EXPORT_SYMBOL_NS_GPL(cxl_register_proto_err_work, "CXL"); + +void cxl_unregister_proto_err_work(void) +{ + guard(rwsem_write)(&cxl_proto_err_kfifo.rw_sema); + cxl_proto_err_kfifo.work =3D NULL; +} +EXPORT_SYMBOL_NS_GPL(cxl_unregister_proto_err_work, "CXL"); + +int cxl_proto_err_kfifo_get(struct cxl_proto_err_work_data *wd) +{ + guard(rwsem_read)(&cxl_proto_err_kfifo.rw_sema); + return kfifo_get(&cxl_proto_err_kfifo.fifo, wd); +} +EXPORT_SYMBOL_NS_GPL(cxl_proto_err_kfifo_get, "CXL"); diff --git a/drivers/pci/pcie/portdrv.h b/drivers/pci/pcie/portdrv.h index cc58bf2f2c84..66a6b8099c96 100644 --- a/drivers/pci/pcie/portdrv.h +++ b/drivers/pci/pcie/portdrv.h @@ -130,9 +130,13 @@ struct aer_err_info; bool is_aer_internal_error(struct aer_err_info *info); void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info); void cxl_rch_enable_rcec(struct pci_dev *rcec); +bool is_cxl_error(struct pci_dev *pdev, struct aer_err_info *info); +void cxl_forward_error(struct pci_dev *pdev, struct aer_err_info *info); #else static inline bool is_aer_internal_error(struct aer_err_info *info) { retu= rn false; } static inline void cxl_rch_handle_error(struct pci_dev *dev, struct aer_er= r_info *info) { } static inline void cxl_rch_enable_rcec(struct pci_dev *rcec) { } +static inline bool is_cxl_error(struct pci_dev *pdev, struct aer_err_info = *info) { return false; } +static inline void cxl_forward_error(struct pci_dev *pdev, struct aer_err_= info *info) { } #endif /* CONFIG_CXL_RAS */ #endif /* _PORTDRV_H_ */ diff --git a/include/linux/aer.h b/include/linux/aer.h index df0f5c382286..f351e41dd979 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -53,6 +53,16 @@ struct aer_capability_regs { u16 uncor_err_source; }; =20 +/** + * struct cxl_proto_err_work_data - Error information used in CXL error ha= ndling + * @pdev: PCI device detecting the error + * @severity: AER severity + */ +struct cxl_proto_err_work_data { + struct pci_dev *pdev; + int severity; +}; + #if defined(CONFIG_PCIEAER) int pci_aer_clear_nonfatal_status(struct pci_dev *dev); int pcie_aer_is_native(struct pci_dev *dev); @@ -66,6 +76,18 @@ static inline int pcie_aer_is_native(struct pci_dev *dev= ) { return 0; } static inline void pci_aer_unmask_internal_errors(struct pci_dev *dev) { } #endif =20 +struct work_struct; + +#ifdef CONFIG_CXL_RAS +int cxl_proto_err_kfifo_get(struct cxl_proto_err_work_data *wd); +void cxl_register_proto_err_work(struct work_struct *work); +void cxl_unregister_proto_err_work(void); +#else +static inline int cxl_proto_err_kfifo_get(struct cxl_proto_err_work_data *= wd) { return 0; } +static inline void cxl_register_proto_err_work(struct work_struct *work) {= } +static inline void cxl_unregister_proto_err_work(void) { } +#endif + void pci_print_aer(struct pci_dev *dev, int aer_severity, struct aer_capability_regs *aer); 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charset="utf-8" CXL protocol error handling will be expanded to soon include CXL Port support along with existing Endpoint support. 2 updates are needed first: - Update calling interfaces to use 'struct device*' - Log endpoint serial number Add serial number parameter to the trace logging. This is used for EPs and 0 is provided for CXL port devices without a serial number. Leave the correctable and uncorrectable trace routines' TP_STRUCT__entry() unchanged with respect to member data types and order. Below is output of correctable and uncorrectable protocol error logging. CXL Root Port and CXL Endpoint examples are included below. The tracing support for CXL Port devices and Endpoints is already implement= ed. Update cxl_handle_ras() & cxl_handle_cor_ras() to also call the CXL trace routines. Root Port: cxl_port_aer_correctable_error: device=3D0000:0c:00.0 host=3Dpci0000:0c ser= ial: 0 status=3D'CRC Threshold Hit' cxl_port_aer_uncorrectable_error: device=3D0000:0c:00.0 host=3Dpci0000:0c s= erial: 0 status: 'Cache Byte Enable Parity Error' first_error: 'Cache Byte = Enable Parity Error' Endpoint: cxl_aer_correctable_error: memdev=3Dmem3 host=3D0000:0f:00.0 serial=3D0 sta= tus=3D'CRC Threshold Hit' cxl_aer_uncorrectable_error: memdev=3Dmem3 host=3D0000:0f:00.0 serial: 0 st= atus: 'Cache Byte Enable Parity Error' first_error: 'Cache Byte Enable Pari= ty Error' Signed-off-by: Terry Bowman Reviewed-by: Shiju Jose Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang Reviewed-by: Dan Williams --- Changes in v14->v15: - Update commit message. - Moved cxl_handle_ras/cxl_handle_cor_ras() changes to future patch (terry) Changes in v13->v14: - Update commit headline (Bjorn) Changes in v12->v13: - Added Dave Jiang's review-by Changes in v11 -> v12: - Correct parameters to call trace_cxl_aer_correctable_error() - Add reviewed-by for Jonathan and Shiju Changes in v10->v11: - Updated CE and UCE trace routines to maintain consistent TP_Struct ABI and unchanged TP_printk() logging. --- drivers/cxl/core/core.h | 11 +++++++---- drivers/cxl/core/ras.c | 23 ++++++++++++++--------- drivers/cxl/core/ras_rch.c | 6 ++++-- drivers/cxl/core/trace.h | 21 +++++++++++---------- 4 files changed, 36 insertions(+), 25 deletions(-) diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index be3c7b137115..c6cfaf2720e1 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -155,8 +155,9 @@ static inline struct device *dport_to_host(struct cxl_d= port *dport) #ifdef CONFIG_CXL_RAS int cxl_ras_init(void); void cxl_ras_exit(void); -bool cxl_handle_ras(struct device *dev, void __iomem *ras_base); -void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base); +bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *ras_base= ); +void cxl_handle_cor_ras(struct device *dev, u64 serial, + void __iomem *ras_base); void cxl_dport_map_rch_aer(struct cxl_dport *dport); void cxl_disable_rch_root_ints(struct cxl_dport *dport); void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds); @@ -167,11 +168,13 @@ static inline int cxl_ras_init(void) return 0; } static inline void cxl_ras_exit(void) { } -static inline bool cxl_handle_ras(struct device *dev, void __iomem *ras_ba= se) +static inline bool cxl_handle_ras(struct device *dev, u64 serial, + void __iomem *ras_base) { return false; } -static inline void cxl_handle_cor_ras(struct device *dev, void __iomem *ra= s_base) { } +static inline void cxl_handle_cor_ras(struct device *dev, u64 serial, + void __iomem *ras_base) { } static inline void cxl_dport_map_rch_aer(struct cxl_dport *dport) { } static inline void cxl_disable_rch_root_ints(struct cxl_dport *dport) { } static inline void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) {= } diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index f6a8f4a355f1..74df561ed32e 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -37,7 +37,8 @@ static void cxl_cper_trace_corr_prot_err(struct cxl_memde= v *cxlmd, { u32 status =3D ras_cap.cor_status & ~ras_cap.cor_mask; =20 - trace_cxl_aer_correctable_error(cxlmd, status); + trace_cxl_aer_correctable_error(&cxlmd->dev, status, + cxlmd->cxlds->serial); } =20 static void @@ -45,6 +46,7 @@ cxl_cper_trace_uncorr_prot_err(struct cxl_memdev *cxlmd, struct cxl_ras_capability_regs ras_cap) { u32 status =3D ras_cap.uncor_status & ~ras_cap.uncor_mask; + struct cxl_dev_state *cxlds =3D cxlmd->cxlds; u32 fe; =20 if (hweight32(status) > 1) @@ -53,8 +55,9 @@ cxl_cper_trace_uncorr_prot_err(struct cxl_memdev *cxlmd, else fe =3D status; =20 - trace_cxl_aer_uncorrectable_error(cxlmd, status, fe, - ras_cap.header_log); + trace_cxl_aer_uncorrectable_error(&cxlmd->dev, status, fe, + ras_cap.header_log, + cxlds->serial); } =20 static int match_memdev_by_parent(struct device *dev, const void *uport) @@ -182,7 +185,7 @@ void devm_cxl_port_ras_setup(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(devm_cxl_port_ras_setup, "CXL"); =20 -void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base) +void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iomem *ras_= base) { void __iomem *addr; u32 status; @@ -194,7 +197,7 @@ void cxl_handle_cor_ras(struct device *dev, void __iome= m *ras_base) status =3D readl(addr); if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); - trace_cxl_aer_correctable_error(to_cxl_memdev(dev), status); + trace_cxl_aer_correctable_error(dev, status, serial); } } =20 @@ -219,7 +222,7 @@ static void header_log_copy(void __iomem *ras_base, u32= *log) * Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. */ -bool cxl_handle_ras(struct device *dev, void __iomem *ras_base) +bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *ras_base) { u32 hl[CXL_HEADERLOG_SIZE_U32]; void __iomem *addr; @@ -246,7 +249,7 @@ bool cxl_handle_ras(struct device *dev, void __iomem *r= as_base) } =20 header_log_copy(ras_base, hl); - trace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl); + trace_cxl_aer_uncorrectable_error(dev, status, fe, hl, serial); writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); =20 return true; @@ -269,7 +272,8 @@ void cxl_cor_error_detected(struct pci_dev *pdev) if (cxlds->rcd) cxl_handle_rdport_errors(cxlds); =20 - cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlmd->endpoint->regs.ras); + cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlds->serial, + cxlmd->endpoint->regs.ras); } } EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); @@ -298,7 +302,8 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pde= v, * chance the situation is recoverable dump the status of the RAS * capability registers and bounce the active state of the memdev. */ - ue =3D cxl_handle_ras(&cxlds->cxlmd->dev, cxlmd->endpoint->regs.ras); + ue =3D cxl_handle_ras(&cxlds->cxlmd->dev, cxlds->serial, + cxlmd->endpoint->regs.ras); } =20 switch (state) { diff --git a/drivers/cxl/core/ras_rch.c b/drivers/cxl/core/ras_rch.c index 0a8b3b9b6388..5771abfc16de 100644 --- a/drivers/cxl/core/ras_rch.c +++ b/drivers/cxl/core/ras_rch.c @@ -115,7 +115,9 @@ void cxl_handle_rdport_errors(struct cxl_dev_state *cxl= ds) =20 pci_print_aer(pdev, severity, &aer_regs); if (severity =3D=3D AER_CORRECTABLE) - cxl_handle_cor_ras(&cxlds->cxlmd->dev, dport->regs.ras); + cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlds->serial, + dport->regs.ras); else - cxl_handle_ras(&cxlds->cxlmd->dev, dport->regs.ras); + cxl_handle_ras(&cxlds->cxlmd->dev, cxlds->serial, + dport->regs.ras); } diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h index a972e4ef1936..5f630543b720 100644 --- a/drivers/cxl/core/trace.h +++ b/drivers/cxl/core/trace.h @@ -77,11 +77,12 @@ TRACE_EVENT(cxl_port_aer_uncorrectable_error, ); =20 TRACE_EVENT(cxl_aer_uncorrectable_error, - TP_PROTO(const struct cxl_memdev *cxlmd, u32 status, u32 fe, u32 *hl), - TP_ARGS(cxlmd, status, fe, hl), + TP_PROTO(const struct device *cxlmd, u32 status, u32 fe, u32 *hl, + u64 serial), + TP_ARGS(cxlmd, status, fe, hl, serial), TP_STRUCT__entry( - __string(memdev, dev_name(&cxlmd->dev)) - __string(host, dev_name(cxlmd->dev.parent)) + __string(memdev, dev_name(cxlmd)) + __string(host, dev_name(cxlmd->parent)) __field(u64, serial) __field(u32, status) __field(u32, first_error) @@ -90,7 +91,7 @@ TRACE_EVENT(cxl_aer_uncorrectable_error, TP_fast_assign( __assign_str(memdev); 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charset="utf-8" The CXL driver's uncorrectable (UCE) protocol error handling will be updated in the future. One required change is for the error handlers to force a system panic when a UCE is detected. Introduce PCI_ERS_RESULT_PANIC as a 'enum pci_ers_result' type. This will be used by CXL UCE fatal and non-fatal recovery in future patches. Update PCIe recovery documentation with details of PCI_ERS_RESULT_PANIC. Signed-off-by: Terry Bowman Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Reviewed-by: Ben Cheatham Reviewed-by: Dan Williams --- Changes in v14 -> v15: - None Changes in v13 -> v14: - Add review-by for Dan - Update Title prefix (Bjorn) - Removed merge_result. Only logging error for device reporting the error (Dan) Changes in v12->v13: - Add Dave Jiang's, Jonathan's, Ben's review-by - Typo fix (Ben) Changes v11 -> v12: - Documentation requested (Lukas) --- Documentation/PCI/pci-error-recovery.rst | 2 ++ include/linux/pci.h | 3 +++ 2 files changed, 5 insertions(+) diff --git a/Documentation/PCI/pci-error-recovery.rst b/Documentation/PCI/p= ci-error-recovery.rst index 43bc4e3665b4..82ee2c8c0450 100644 --- a/Documentation/PCI/pci-error-recovery.rst +++ b/Documentation/PCI/pci-error-recovery.rst @@ -102,6 +102,8 @@ Possible return values are:: PCI_ERS_RESULT_NEED_RESET, /* Device driver wants slot to be reset. */ PCI_ERS_RESULT_DISCONNECT, /* Device has completely failed, is unrecove= rable */ PCI_ERS_RESULT_RECOVERED, /* Device driver is fully recovered and oper= ational */ + PCI_ERS_RESULT_NO_AER_DRIVER, /* No AER capabilities registered for the = driver */ + PCI_ERS_RESULT_PANIC, /* System is unstable, panic. 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charset="utf-8" The AER driver now forwards CXL protocol errors to the CXL driver via a kfifo. The CXL driver must consume these work items and initiate protocol error handling while ensuring the device's RAS mappings remain valid throughout processing. Implement cxl_proto_err_work_fn() to dequeue work items forwarded by the AER service driver. Lock the parent CXL Port device to ensure the CXL device's RAS registers are accessible during handling. Add pdev reference-p= ut to match reference-get in AER driver. This will ensure pdev access after kfifo dequeue. These changes apply to CXL Ports and CXL Endpoints. Update is_cxl_error() to recognize CXL Port devices with errors. Signed-off-by: Terry Bowman Acked-by: Bjorn Helgaas Reviewed-by: Dan Williams --- Changes in v14->v15: - Move pci_dev_get() to first patch (Dave) - Move in is_cxl_error() change from later patch (Terry) - Use pr_err_ratelimited() with PCI device name (Terry) Changes in v13->v14: - Update commit title's prefix (Bjorn) - Add pdev ref get in AER driver before enqueue and add pdev ref put in CXL driver after dequeue and handling (Dan) - Removed handling to simplify patch context (Terry) Changes in v12->v13: - Add cxlmd lock using guard() (Terry) - Remove exporting of unused function, pci_aer_clear_fatal_status() (Dave J= iang) - Change pr_err() calls to ratelimited. (Terry) - Update commit message. (Terry) - Remove namespace qualifier from pcie_clear_device_status() export (Dave Jiang) - Move locks into cxl_proto_err_work_fn() (Dave) - Update log messages in cxl_forward_error() (Ben) Changes in v11->v12: - Add guard for CE case in cxl_handle_proto_error() (Dave) Changes in v10->v11: - Reword patch commit message to remove RCiEP details (Jonathan) - Add #include (Terry) - is_cxl_rcd() - Fix short comment message wrap (Jonathan) - is_cxl_rcd() - Combine return calls into 1 (Jonathan) - cxl_handle_proto_error() - Move comment earlier (Jonathan) - Use FIELD_GET() in discovering class code (Jonathan) - Remove BDF from cxl_proto_err_work_data. Use 'struct pci_dev *' (Dan) --- drivers/cxl/core/core.h | 3 + drivers/cxl/core/port.c | 6 +- drivers/cxl/core/ras.c | 106 ++++++++++++++++++++++++++++++---- drivers/pci/pcie/aer_cxl_vh.c | 5 +- 4 files changed, 105 insertions(+), 15 deletions(-) diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index c6cfaf2720e1..92aea110817d 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -182,6 +182,9 @@ static inline void devm_cxl_dport_ras_setup(struct cxl_= dport *dport) { } #endif /* CONFIG_CXL_RAS */ =20 int cxl_gpf_port_setup(struct cxl_dport *dport); +struct cxl_port *find_cxl_port(struct device *dport_dev, + struct cxl_dport **dport); +struct cxl_port *find_cxl_port_by_uport(struct device *uport_dev); =20 struct cxl_hdm; int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhd= m, diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index ee7d14528867..8e30a3e7f610 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1402,8 +1402,8 @@ static struct cxl_port *__find_cxl_port(struct cxl_fi= nd_port_ctx *ctx) return NULL; } =20 -static struct cxl_port *find_cxl_port(struct device *dport_dev, - struct cxl_dport **dport) +struct cxl_port *find_cxl_port(struct device *dport_dev, + struct cxl_dport **dport) { struct cxl_find_port_ctx ctx =3D { .dport_dev =3D dport_dev, @@ -1607,7 +1607,7 @@ static int match_port_by_uport(struct device *dev, co= nst void *data) * Function takes a device reference on the port device. Caller should do a * put_device() when done. */ -static struct cxl_port *find_cxl_port_by_uport(struct device *uport_dev) +struct cxl_port *find_cxl_port_by_uport(struct device *uport_dev) { struct device *dev; =20 diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 74df561ed32e..a6c0bc6d7203 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -118,17 +118,6 @@ static void cxl_cper_prot_err_work_fn(struct work_stru= ct *work) } static DECLARE_WORK(cxl_cper_prot_err_work, cxl_cper_prot_err_work_fn); =20 -int cxl_ras_init(void) -{ - return cxl_cper_register_prot_err_work(&cxl_cper_prot_err_work); -} - -void cxl_ras_exit(void) -{ - cxl_cper_unregister_prot_err_work(&cxl_cper_prot_err_work); - cancel_work_sync(&cxl_cper_prot_err_work); -} - static void cxl_dport_map_ras(struct cxl_dport *dport) { struct cxl_register_map *map =3D &dport->reg_map; @@ -185,6 +174,50 @@ void devm_cxl_port_ras_setup(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(devm_cxl_port_ras_setup, "CXL"); =20 +/* + * get_cxl_port - Return the parent CXL Port of a PCI device + * @pdev: PCI device whose parent CXL Port is being queried + * + * Looks up and returns the parent CXL Port associated with @pdev. On + * success, the returned port has its reference count incremented and must + * be released by the caller. Returns NULL if no associated CXL port is + * found. + * + * Return: Pointer to the parent &struct cxl_port or NULL on failure + */ +static struct cxl_port *get_cxl_port(struct pci_dev *pdev) +{ + switch (pci_pcie_type(pdev)) { + case PCI_EXP_TYPE_ROOT_PORT: + case PCI_EXP_TYPE_DOWNSTREAM: + { + struct cxl_dport *dport; + struct cxl_port *port =3D find_cxl_port(&pdev->dev, &dport); + + if (!port) { + pci_err(pdev, "Failed to find the CXL device"); + return NULL; + } + return port; + } + case PCI_EXP_TYPE_UPSTREAM: + case PCI_EXP_TYPE_ENDPOINT: + { + struct cxl_port *port =3D find_cxl_port_by_uport(&pdev->dev); + + if (!port) { + pci_err(pdev, "Failed to find the CXL device"); + return NULL; + } + return port; + } + } + + pr_err_ratelimited("%s: Error - Unsupported device type (%#x)", + pci_name(pdev), pci_pcie_type(pdev)); + return NULL; +} + void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iomem *ras_= base) { void __iomem *addr; @@ -327,3 +360,54 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pd= ev, return PCI_ERS_RESULT_NEED_RESET; } EXPORT_SYMBOL_NS_GPL(cxl_error_detected, "CXL"); + +static void cxl_handle_proto_error(struct cxl_proto_err_work_data *err_inf= o) +{ +} + +static void cxl_proto_err_work_fn(struct work_struct *work) +{ + struct cxl_proto_err_work_data wd; + + while (cxl_proto_err_kfifo_get(&wd)) { + struct pci_dev *pdev __free(pci_dev_put) =3D wd.pdev; + + if (!pdev) { + pr_err_ratelimited("%s: NULL PCI device passed in AER-CXL KFifo\n", + pci_name(pdev)); + continue; + } + + struct cxl_port *port __free(put_cxl_port) =3D get_cxl_port(pdev); + if (!port) { + pr_err_ratelimited("%s: Failed to find parent port device in CXL topolo= gy\n", + pci_name(pdev)); + continue; + } + guard(device)(&port->dev); + + cxl_handle_proto_error(&wd); + } +} + +static struct work_struct cxl_proto_err_work; +static DECLARE_WORK(cxl_proto_err_work, cxl_proto_err_work_fn); + +int cxl_ras_init(void) +{ + if (cxl_cper_register_prot_err_work(&cxl_cper_prot_err_work)) + pr_err("Failed to initialize CXL RAS CPER\n"); + + cxl_register_proto_err_work(&cxl_proto_err_work); + + return 0; +} + +void cxl_ras_exit(void) +{ + cxl_cper_unregister_prot_err_work(&cxl_cper_prot_err_work); + cancel_work_sync(&cxl_cper_prot_err_work); + + cxl_unregister_proto_err_work(); + cancel_work_sync(&cxl_proto_err_work); +} diff --git a/drivers/pci/pcie/aer_cxl_vh.c b/drivers/pci/pcie/aer_cxl_vh.c index de8bca383159..6bcd6271afbf 100644 --- a/drivers/pci/pcie/aer_cxl_vh.c +++ b/drivers/pci/pcie/aer_cxl_vh.c @@ -34,7 +34,10 @@ bool is_cxl_error(struct pci_dev *pdev, struct aer_err_i= nfo *info) if (!info || !info->is_cxl) return false; =20 - if (pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_ENDPOINT) + if ((pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_ENDPOINT) && + (pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_ROOT_PORT) && + (pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_UPSTREAM) && + (pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_DOWNSTREAM)) return false; =20 return is_aer_internal_error(info); --=20 2.34.1 From nobody Sat Feb 7 06:14:10 2026 Received: from SN4PR0501CU005.outbound.protection.outlook.com (mail-southcentralusazon11011000.outbound.protection.outlook.com [40.93.194.0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 195AE202C48; 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Mon, 2 Feb 2026 20:53:55 -0600 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v15 5/9] PCI: Establish common CXL Port protocol error flow Date: Mon, 2 Feb 2026 20:52:40 -0600 Message-ID: <20260203025244.3093805-6-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260203025244.3093805-1-terry.bowman@amd.com> References: <20260203025244.3093805-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB52:EE_|MW6PR12MB8868:EE_ X-MS-Office365-Filtering-Correlation-Id: 3f7f3d2d-749b-4502-c6ed-08de62cf7916 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|82310400026|36860700013|921020; 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charset="utf-8" Introduce CXL Port protocol error handling callbacks to unify detection, logging, and recovery across CXL Ports and Endpoints, including RCH downstream ports. Establish a consistent flow for correctable and uncorrectable CXL protocol errors. Provide the solution by adding cxl_port_cor_error_detected() and cxl_port_error_detected() to handle correctable and uncorrectable handling through CXL RAS helpers, coordinating uncorrectable recovery in cxl_do_recovery(), and panicking when the handler returns PCI_ERS_RESULT_PA= NIC to preserve fatal cachemem behavior. Gate endpoint handling on the endpoint driver being bound to avoid processing errors on disabled devices. Centralize the RAS base lookup in cxl_get_ras_base(), selecting the downstream-port dport->regs.ras for Root/Downstream Ports and port->regs.ras for Upstream Ports/Endpoints. Export pcie_clear_device_status() and pci_aer_clear_fatal_status() to enable cxl_core to clear PCIe/AER state in these flows. Signed-off-by: Terry Bowman Acked-by: Bjorn Helgaas Reviewed-by: Dave Jiang dave.jiang@intel.com --- Changes in v14->v15: - Update commit message and title. Added Bjorn's ack. - Move CE and UCE handling logic here Changes in v13->v14: - Add Dave Jiang's review-by - Update commit message & headline (Bjorn) - Refactor cxl_port_error_detected()/cxl_port_cor_error_detected() to one line (Jonathan) - Remove cxl_walk_port() (Dan) - Remove cxl_pci_drv_bound(). Check for 'is_cxl' parent port is sufficient (Dan) - Remove device_lock_if() - Combined CE and UCE here (Terry) Changes in v12->v13: - Move get_pci_cxl_host_dev() and cxl_handle_proto_error() to Dequeue patch (Terry) - Remove EP case in cxl_get_ras_base(), not used. (Terry) - Remove check for dport->dport_dev (Dave) - Remove whitespace (Terry) Changes in v11->v12: - Add call to cxl_pci_drv_bound() in cxl_handle_proto_error() and pci_to_cxl_dev() - Change cxl_error_detected() -> cxl_cor_error_detected() - Remove NULL variable assignments - Replace bus_find_device() with find_cxl_port_by_uport() for upstream port searches. Changes in v10->v11: - None --- drivers/cxl/core/ras.c | 134 +++++++++++++++++++++++++++++++++++++++++ drivers/pci/pci.c | 1 + drivers/pci/pci.h | 2 - drivers/pci/pcie/aer.c | 1 + include/linux/aer.h | 2 + include/linux/pci.h | 2 + 6 files changed, 140 insertions(+), 2 deletions(-) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index a6c0bc6d7203..0216dafa6118 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -218,6 +218,68 @@ static struct cxl_port *get_cxl_port(struct pci_dev *p= dev) return NULL; } =20 +static void __iomem *cxl_get_ras_base(struct device *dev) +{ + struct pci_dev *pdev =3D to_pci_dev(dev); + + switch (pci_pcie_type(pdev)) { + case PCI_EXP_TYPE_ROOT_PORT: + case PCI_EXP_TYPE_DOWNSTREAM: + { + struct cxl_dport *dport; + struct cxl_port *port __free(put_cxl_port) =3D find_cxl_port(&pdev->dev,= &dport); + + if (!dport) { + pci_err(pdev, "Failed to find the CXL device"); + return NULL; + } + return dport->regs.ras; + } + case PCI_EXP_TYPE_UPSTREAM: + case PCI_EXP_TYPE_ENDPOINT: + { + struct cxl_port *port __free(put_cxl_port) =3D find_cxl_port_by_uport(&p= dev->dev); + + if (!port) { + pci_err(pdev, "Failed to find the CXL device"); + return NULL; + } + return port->regs.ras; + } + } + dev_warn_once(dev, "Error: Unsupported device type (%#x)", pci_pcie_type(= pdev)); + return NULL; +} + +static pci_ers_result_t cxl_port_error_detected(struct device *dev); + +static void cxl_do_recovery(struct pci_dev *pdev) +{ + struct cxl_port *port __free(put_cxl_port) =3D get_cxl_port(pdev); + pci_ers_result_t status; + + if (!port) { + pci_err(pdev, "Failed to find the CXL device\n"); + return; + } + + status =3D cxl_port_error_detected(&pdev->dev); + if (status =3D=3D PCI_ERS_RESULT_PANIC) + panic("CXL cachemem error."); + + /* + * If we have native control of AER, clear error status in the device + * that detected the error. If the platform retained control of AER, + * it is responsible for clearing this status. In that case, the + * signaling device may not even be visible to the OS. + */ + if (pcie_aer_is_native(pdev)) { + pcie_clear_device_status(pdev); + pci_aer_clear_nonfatal_status(pdev); + pci_aer_clear_fatal_status(pdev); + } +} + void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iomem *ras_= base) { void __iomem *addr; @@ -288,6 +350,60 @@ bool cxl_handle_ras(struct device *dev, u64 serial, vo= id __iomem *ras_base) return true; } =20 +static void cxl_port_cor_error_detected(struct device *dev) +{ + struct pci_dev *pdev =3D to_pci_dev(dev); + struct cxl_port *port __free(put_cxl_port) =3D get_cxl_port(pdev); + + if (is_cxl_endpoint(port)) { + struct cxl_memdev *cxlmd =3D to_cxl_memdev(port->uport_dev); + struct cxl_dev_state *cxlds =3D cxlmd->cxlds; + + guard(device)(&cxlmd->dev); + + if (!dev->driver) { + dev_warn(&pdev->dev, + "%s: memdev disabled, abort error handling\n", + dev_name(dev)); + return; + } + + if (cxlds->rcd) + cxl_handle_rdport_errors(cxlds); + + cxl_handle_cor_ras(dev, cxlds->serial, cxl_get_ras_base(dev)); + } else { + cxl_handle_cor_ras(dev, 0, cxl_get_ras_base(dev)); + } +} + +static pci_ers_result_t cxl_port_error_detected(struct device *dev) +{ + struct pci_dev *pdev =3D to_pci_dev(dev); + struct cxl_port *port __free(put_cxl_port) =3D get_cxl_port(pdev); + + if (is_cxl_endpoint(port)) { + struct cxl_memdev *cxlmd =3D to_cxl_memdev(port->uport_dev); + struct cxl_dev_state *cxlds =3D cxlmd->cxlds; + + guard(device)(&cxlmd->dev); + + if (!dev->driver) { + dev_warn(&pdev->dev, + "%s: memdev disabled, abort error handling\n", + dev_name(dev)); + return PCI_ERS_RESULT_NONE; + } + + if (cxlds->rcd) + cxl_handle_rdport_errors(cxlds); + + return cxl_handle_ras(dev, cxlds->serial, cxl_get_ras_base(dev)); + } else { + return cxl_handle_ras(dev, 0, cxl_get_ras_base(dev)); + } +} + void cxl_cor_error_detected(struct pci_dev *pdev) { struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); @@ -363,6 +479,24 @@ EXPORT_SYMBOL_NS_GPL(cxl_error_detected, "CXL"); =20 static void cxl_handle_proto_error(struct cxl_proto_err_work_data *err_inf= o) { + struct pci_dev *pdev =3D err_info->pdev; + + if (err_info->severity =3D=3D AER_CORRECTABLE) { + + if (!pcie_aer_is_native(pdev)) + return; + + if (pdev->aer_cap) + pci_clear_and_set_config_dword(pdev, + pdev->aer_cap + PCI_ERR_COR_STATUS, + 0, PCI_ERR_COR_INTERNAL); + + cxl_port_cor_error_detected(&pdev->dev); + + pcie_clear_device_status(pdev); + } else { + cxl_do_recovery(pdev); + } } =20 static void cxl_proto_err_work_fn(struct work_struct *work) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 13dbb405dc31..b7bfefdaf990 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -2248,6 +2248,7 @@ void pcie_clear_device_status(struct pci_dev *dev) pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta); pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta); } +EXPORT_SYMBOL_GPL(pcie_clear_device_status); #endif =20 /** diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 8ccb3ba61e11..d81c4170f595 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -229,7 +229,6 @@ void pci_refresh_power_state(struct pci_dev *dev); int pci_power_up(struct pci_dev *dev); void pci_disable_enabled_device(struct pci_dev *dev); int pci_finish_runtime_suspend(struct pci_dev *dev); -void pcie_clear_device_status(struct pci_dev *dev); void pcie_clear_root_pme_status(struct pci_dev *dev); bool pci_check_pme_status(struct pci_dev *dev); void pci_pme_wakeup_bus(struct pci_bus *bus); @@ -1198,7 +1197,6 @@ void pci_restore_aer_state(struct pci_dev *dev); static inline void pci_no_aer(void) { } static inline void pci_aer_init(struct pci_dev *d) { } static inline void pci_aer_exit(struct pci_dev *d) { } -static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINV= AL; } static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -= EINVAL; } static inline void pci_save_aer_state(struct pci_dev *dev) { } diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 7af10a74da34..4fc9de4c78f8 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -298,6 +298,7 @@ void pci_aer_clear_fatal_status(struct pci_dev *dev) if (status) pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status); } +EXPORT_SYMBOL_GPL(pci_aer_clear_fatal_status); =20 /** * pci_aer_raw_clear_status - Clear AER error registers. diff --git a/include/linux/aer.h b/include/linux/aer.h index f351e41dd979..c1aef7859d0a 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -65,6 +65,7 @@ struct cxl_proto_err_work_data { =20 #if defined(CONFIG_PCIEAER) int pci_aer_clear_nonfatal_status(struct pci_dev *dev); +void pci_aer_clear_fatal_status(struct pci_dev *dev); int pcie_aer_is_native(struct pci_dev *dev); void pci_aer_unmask_internal_errors(struct pci_dev *dev); #else @@ -72,6 +73,7 @@ static inline int pci_aer_clear_nonfatal_status(struct pc= i_dev *dev) { return -EINVAL; } +static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; } static inline void pci_aer_unmask_internal_errors(struct pci_dev *dev) { } #endif diff --git a/include/linux/pci.h b/include/linux/pci.h index ee05d5925b13..1ef4743bf151 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1921,8 +1921,10 @@ static inline void pci_hp_unignore_link_change(struc= t pci_dev *pdev) { } =20 #ifdef CONFIG_PCIEAER bool pci_aer_available(void); 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charset="utf-8" CXL Protocol errors are logged for Endpoints in cxl_handle_ras() and cxl_handle_cor_ras(). The same is missing for CXL Port devices. The CXL Port logging function is already present but needs a call added from the handlers. Update cxl_handle_ras() and cxl_handle_cor_ras() to call the CXL Port trace logging function. Also, add log messages in the case 'ras_base' is NULL. And, add calls to the existing CXL Port tracing in the same functions. Signed-off-by: Terry Bowman --- Changes in v14 -> v15: - New commit --- drivers/cxl/core/core.h | 10 ++++++---- drivers/cxl/core/ras.c | 30 ++++++++++++++++++++++-------- 2 files changed, 28 insertions(+), 12 deletions(-) diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 92aea110817d..3b232e991b12 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -6,6 +6,7 @@ =20 #include #include +#include =20 extern const struct device_type cxl_nvdimm_bridge_type; extern const struct device_type cxl_nvdimm_type; @@ -155,7 +156,8 @@ static inline struct device *dport_to_host(struct cxl_d= port *dport) #ifdef CONFIG_CXL_RAS int cxl_ras_init(void); void cxl_ras_exit(void); -bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *ras_base= ); +pci_ers_result_t cxl_handle_ras(struct device *dev, u64 serial, + void __iomem *ras_base); void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iomem *ras_base); void cxl_dport_map_rch_aer(struct cxl_dport *dport); @@ -168,10 +170,10 @@ static inline int cxl_ras_init(void) return 0; } static inline void cxl_ras_exit(void) { } -static inline bool cxl_handle_ras(struct device *dev, u64 serial, - void __iomem *ras_base) +static inline pci_ers_result_t cxl_handle_ras(struct device *dev, u64 seri= al, + void __iomem *ras_base) { - return false; + return PCI_ERS_RESULT_NONE; } static inline void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iomem *ras_base) { } diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 0216dafa6118..970ff3df442c 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -285,15 +285,22 @@ void cxl_handle_cor_ras(struct device *dev, u64 seria= l, void __iomem *ras_base) void __iomem *addr; u32 status; =20 - if (!ras_base) + if (!ras_base) { + pr_err_ratelimited("%s: CXL RAS registers aren't mapped\n", + dev_name(dev)); return; + } =20 addr =3D ras_base + CXL_RAS_CORRECTABLE_STATUS_OFFSET; status =3D readl(addr); - if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { - writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); + if (!(status & CXL_RAS_CORRECTABLE_STATUS_MASK)) + return; + + writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); + if (is_cxl_memdev(dev)) trace_cxl_aer_correctable_error(dev, status, serial); - } + else + trace_cxl_port_aer_correctable_error(dev, status); } =20 /* CXL spec rev3.0 8.2.4.16.1 */ @@ -317,15 +324,19 @@ static void header_log_copy(void __iomem *ras_base, u= 32 *log) * Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. */ -bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *ras_base) +pci_ers_result_t +cxl_handle_ras(struct device *dev, u64 serial, void __iomem *ras_base) { u32 hl[CXL_HEADERLOG_SIZE_U32]; void __iomem *addr; u32 status; u32 fe; =20 - if (!ras_base) + if (!ras_base) { + pr_err_ratelimited("%s: CXL RAS registers aren't mapped\n", + dev_name(dev)); return false; + } =20 addr =3D ras_base + CXL_RAS_UNCORRECTABLE_STATUS_OFFSET; status =3D readl(addr); @@ -344,10 +355,13 @@ bool cxl_handle_ras(struct device *dev, u64 serial, v= oid __iomem *ras_base) } =20 header_log_copy(ras_base, hl); - trace_cxl_aer_uncorrectable_error(dev, status, fe, hl, serial); + if (is_cxl_memdev(dev)) + trace_cxl_aer_uncorrectable_error(dev, status, fe, hl, serial); + else + trace_cxl_port_aer_uncorrectable_error(dev, status, fe, hl); writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); =20 - return true; + return PCI_ERS_RESULT_PANIC; } =20 static void cxl_port_cor_error_detected(struct device *dev) --=20 2.34.1 From nobody Sat Feb 7 06:14:10 2026 Received: from PH0PR06CU001.outbound.protection.outlook.com (mail-westus3azon11011005.outbound.protection.outlook.com [40.107.208.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D52B631D371; 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charset="utf-8" CXL drivers now implement protocol RAS support. PCI protocol errors, however, continue to be reported via the AER capability and must still be handled by a PCI error recovery callback. Replace the existing cxl_error_detected() callback in cxl/pci.c with a new cxl_pci_error_detected() implementation that handles only uncorrectable PCI protocol errors reported through AER. Introduce helper named cxl_handler_aer() amd implement to handle and log the CXL device's AER error. This cleanly separates CXL protocol error handling from PCI AER handling and ensures that each subsystem processes only the errors it is responsible. Signed-off-by: Terry Bowman --- Changes in v14->v15: - Title update (Terry) - Change cxl_pci_error-detected() to handle & log AER (Terry) - Update commit message (Terry) - Moved cxl_handle_ras()/cxl_handle_cor_ras() to earlier patch (Terry) Changes in v13->v14: - Update commit headline (Bjorn) - Rename pci_error_detected()/pci_cor_error_detected() -> cxl_pci_error_detected/cxl_pci_cor_error_detected() (Jonathan) - Remove now-invalid comment in cxl_error_detected() (Jonathan) - Split into separate patches for UCE and CE (Terry) Changes in v12->v13: - Update commit messaqge (Terry) - Updated all the implementation and commit message. (Terry) - Refactored cxl_cor_error_detected()/cxl_error_detected() to remove pdev (Dave Jiang) Changes in v11->v12: - None Changes in v10->v11: - cxl_error_detected() - Change handlers' scoped_guard() to guard() (Jonath= an) - cxl_error_detected() - Remove extra line (Shiju) - Changes moved to core/ras.c (Terry) - cxl_error_detected(), remove 'ue' and return with function call. (Jonatha= n) - Remove extra space in documentation for PCI_ERS_RESULT_PANIC definition - Move #include "pci.h from cxl.h to core.h (Terry) - Remove unnecessary includes of cxl.h and core.h in mem.c (Terry) --- drivers/cxl/core/ras.c | 68 +++++++++++++++--------------------------- drivers/cxl/cxlpci.h | 9 +++--- drivers/cxl/pci.c | 6 ++-- 3 files changed, 31 insertions(+), 52 deletions(-) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 970ff3df442c..061e6aaec176 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -441,55 +441,35 @@ void cxl_cor_error_detected(struct pci_dev *pdev) } EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); =20 -pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, - pci_channel_state_t state) +static bool cxl_handle_aer(struct pci_dev *pdev) { - struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); - struct cxl_memdev *cxlmd =3D cxlds->cxlmd; - struct device *dev =3D &cxlmd->dev; - bool ue; - - scoped_guard(device, dev) { - if (!dev->driver) { - dev_warn(&pdev->dev, - "%s: memdev disabled, abort error handling\n", - dev_name(dev)); - return PCI_ERS_RESULT_DISCONNECT; - } + struct aer_capability_regs aer; + u32 aer_cap =3D pdev->aer_cap; =20 - if (cxlds->rcd) - cxl_handle_rdport_errors(cxlds); - /* - * A frozen channel indicates an impending reset which is fatal to - * CXL.mem operation, and will likely crash the system. On the off - * chance the situation is recoverable dump the status of the RAS - * capability registers and bounce the active state of the memdev. - */ - ue =3D cxl_handle_ras(&cxlds->cxlmd->dev, cxlds->serial, - cxlmd->endpoint->regs.ras); + if (!aer_cap) { + pr_warn_ratelimited("%s: AER capability isn't present\n", + pci_name(pdev)); + return false; } =20 - switch (state) { - case pci_channel_io_normal: - if (ue) { - device_release_driver(dev); - return PCI_ERS_RESULT_NEED_RESET; - } - return PCI_ERS_RESULT_CAN_RECOVER; - case pci_channel_io_frozen: - dev_warn(&pdev->dev, - "%s: frozen state error detected, disable CXL.mem\n", - dev_name(dev)); - device_release_driver(dev); - return PCI_ERS_RESULT_NEED_RESET; - case pci_channel_io_perm_failure: - dev_warn(&pdev->dev, - "failure state error detected, request disconnect\n"); - return PCI_ERS_RESULT_DISCONNECT; - } - return PCI_ERS_RESULT_NEED_RESET; + pci_read_config_dword(pdev, aer_cap + PCI_ERR_UNCOR_STATUS, &aer.uncor_st= atus); + pci_read_config_dword(pdev, aer_cap + PCI_ERR_UNCOR_MASK, &aer.uncor_mask= ); + + /* The AER driver logged the error */ + pci_aer_clear_nonfatal_status(pdev); + pci_aer_clear_fatal_status(pdev); + + return (aer.uncor_status & aer.uncor_mask); +} + +pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev, + pci_channel_state_t error) +{ + u32 rc =3D cxl_handle_aer(pdev); + + return rc ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_CAN_RECOVER; } -EXPORT_SYMBOL_NS_GPL(cxl_error_detected, "CXL"); +EXPORT_SYMBOL_NS_GPL(cxl_pci_error_detected, "CXL"); =20 static void cxl_handle_proto_error(struct cxl_proto_err_work_data *err_inf= o) { diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index 970add0256e9..5534422b496c 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -79,15 +79,14 @@ void read_cdat_data(struct cxl_port *port); =20 #ifdef CONFIG_CXL_RAS void cxl_cor_error_detected(struct pci_dev *pdev); -pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, - pci_channel_state_t state); void devm_cxl_dport_rch_ras_setup(struct cxl_dport *dport); +pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev, + pci_channel_state_t error); void devm_cxl_port_ras_setup(struct cxl_port *port); #else static inline void cxl_cor_error_detected(struct pci_dev *pdev) { } - -static inline pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, - pci_channel_state_t state) +static inline pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev, + pci_channel_state_t state) { return PCI_ERS_RESULT_NONE; } diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index acb0eb2a13c3..ff741adc7c7f 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -1051,8 +1051,8 @@ static void cxl_reset_done(struct pci_dev *pdev) } } =20 -static const struct pci_error_handlers cxl_error_handlers =3D { - .error_detected =3D cxl_error_detected, +static const struct pci_error_handlers pci_error_handlers =3D { + .error_detected =3D cxl_pci_error_detected, .slot_reset =3D cxl_slot_reset, .resume =3D cxl_error_resume, .cor_error_detected =3D cxl_cor_error_detected, @@ -1063,7 +1063,7 @@ static struct pci_driver cxl_pci_driver =3D { .name =3D KBUILD_MODNAME, .id_table =3D cxl_mem_pci_tbl, .probe =3D cxl_pci_probe, - .err_handler =3D &cxl_error_handlers, + .err_handler =3D &pci_error_handlers, .dev_groups =3D cxl_rcd_groups, .driver =3D { .probe_type =3D PROBE_PREFER_ASYNCHRONOUS, --=20 2.34.1 From nobody Sat Feb 7 06:14:10 2026 Received: from CH4PR04CU002.outbound.protection.outlook.com (mail-northcentralusazon11013000.outbound.protection.outlook.com [40.107.201.0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0DE892F363E; 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charset="utf-8" CXL drivers dont require a correctable PCI AER handler. Correctable AER errors reported by CXL devices are logged and cleared in the AER driver. This makes the correctable AER handler callback in the CXL driver unnecessary. Remove cxl_cor_error_detected() and drop the .cor_error_detected callback from the CXL PCI error handlers. This consolidates correctable error reporting under the CXL RAS infrastruct= ure and avoids redundant or conflicting logging with the AER driver. Signed-off-by: Terry Bowman --- Changes in v14->v15: - Remove cxl_pci_cor_error_detected(). Is not needed. AER is logged in the AER driver. (Dan) - Update commit message (Terry) Changes in v13->v14: - New commit - Change cxl_cor_error_detected() parameter to &pdev->dev device from memdev device. (Terry) - Updated commit message (Terry) --- drivers/cxl/core/ras.c | 23 ----------------------- drivers/cxl/cxlpci.h | 2 -- drivers/cxl/pci.c | 1 - 3 files changed, 26 deletions(-) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 061e6aaec176..e5a0d0283d3f 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -418,29 +418,6 @@ static pci_ers_result_t cxl_port_error_detected(struct= device *dev) } } =20 -void cxl_cor_error_detected(struct pci_dev *pdev) -{ - struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); - struct cxl_memdev *cxlmd =3D cxlds->cxlmd; - struct device *dev =3D &cxlds->cxlmd->dev; - - scoped_guard(device, dev) { - if (!dev->driver) { - dev_warn(&pdev->dev, - "%s: memdev disabled, abort error handling\n", - dev_name(dev)); - return; - } - - if (cxlds->rcd) - cxl_handle_rdport_errors(cxlds); - - cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlds->serial, - cxlmd->endpoint->regs.ras); - } -} -EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); - static bool cxl_handle_aer(struct pci_dev *pdev) { struct aer_capability_regs aer; diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index 5534422b496c..e3388dffdd75 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -78,13 +78,11 @@ struct cxl_dev_state; void read_cdat_data(struct cxl_port *port); =20 #ifdef CONFIG_CXL_RAS -void cxl_cor_error_detected(struct pci_dev *pdev); void devm_cxl_dport_rch_ras_setup(struct cxl_dport *dport); pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t error); void devm_cxl_port_ras_setup(struct cxl_port *port); #else -static inline void cxl_cor_error_detected(struct pci_dev *pdev) { } static inline pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) { diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index ff741adc7c7f..c6b2966f5fda 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -1055,7 +1055,6 @@ static const struct pci_error_handlers pci_error_hand= lers =3D { .error_detected =3D cxl_pci_error_detected, .slot_reset =3D cxl_slot_reset, .resume =3D cxl_error_resume, - .cor_error_detected =3D cxl_cor_error_detected, .reset_done =3D cxl_reset_done, }; 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charset="utf-8" CXL protocol errors are not enabled for all CXL devices after boot. These must be enabled inorder to process CXL protocol errors. Introduce cxl_unmask_proto_interrupts() to call pci_aer_unmask_internal_err= ors(). pci_aer_unmask_internal_errors() expects the pdev->aer_cap is initialized. But, dev->aer_cap is not initialized for CXL Upstream Switch Ports and CXL Downstream Switch Ports. Initialize the dev->aer_cap if necessary. Enable A= ER correctable internal errors and uncorrectable internal errors for all CXL devices. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Dave Jiang Reviewed-by: Ben Cheatham --- Changes in v13->v14: - Update commit title's prefix (Bjorn) Changes in v12->v13: - Add dev and dev_is_pci() NULL checks in cxl_unmask_proto_interrupts() (Te= rry) - Add Dave Jiang's and Ben's review-by Changes in v11->v12: - None Changes in v10->v11: - Added check for valid PCI devices in is_cxl_error() (Terry) - Removed check for RCiEP in cxl_handle_proto_err() and cxl_report_error_detected() (Terry) --- drivers/cxl/core/port.c | 2 ++ drivers/cxl/core/ras.c | 22 ++++++++++++++++++++++ drivers/cxl/cxlpci.h | 4 ++++ 3 files changed, 28 insertions(+) diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 8e30a3e7f610..b63e8117d937 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1870,6 +1870,8 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd) =20 rc =3D cxl_add_ep(dport, &cxlmd->dev); =20 + cxl_unmask_proto_interrupts(cxlmd->cxlds->dev); + /* * If the endpoint already exists in the port's list, * that's ok, it was added on a previous pass. diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index e5a0d0283d3f..d6c2fd4ae067 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -118,6 +118,24 @@ static void cxl_cper_prot_err_work_fn(struct work_stru= ct *work) } static DECLARE_WORK(cxl_cper_prot_err_work, cxl_cper_prot_err_work_fn); =20 +void cxl_unmask_proto_interrupts(struct device *dev) +{ + if (!dev || !dev_is_pci(dev)) + return; + + struct pci_dev *pdev __free(pci_dev_put) =3D pci_dev_get(to_pci_dev(dev)); + + if (!pdev->aer_cap) { + pdev->aer_cap =3D pci_find_ext_capability(pdev, + PCI_EXT_CAP_ID_ERR); + if (!pdev->aer_cap) + return; + } + + pci_aer_unmask_internal_errors(pdev); +} +EXPORT_SYMBOL_NS_GPL(cxl_unmask_proto_interrupts, "CXL"); + static void cxl_dport_map_ras(struct cxl_dport *dport) { struct cxl_register_map *map =3D &dport->reg_map; @@ -128,6 +146,8 @@ static void cxl_dport_map_ras(struct cxl_dport *dport) else if (cxl_map_component_regs(map, &dport->regs.component, BIT(CXL_CM_CAP_CAP_ID_RAS))) dev_dbg(dev, "Failed to map RAS capability.\n"); + + cxl_unmask_proto_interrupts(dev); } =20 /** @@ -171,6 +191,8 @@ void devm_cxl_port_ras_setup(struct cxl_port *port) if (cxl_map_component_regs(map, &port->regs, BIT(CXL_CM_CAP_CAP_ID_RAS))) dev_dbg(&port->dev, "Failed to map RAS capability\n"); + + cxl_unmask_proto_interrupts(port->uport_dev); } EXPORT_SYMBOL_NS_GPL(devm_cxl_port_ras_setup, "CXL"); =20 diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index e3388dffdd75..b5fea624b2cc 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -82,6 +82,7 @@ void devm_cxl_dport_rch_ras_setup(struct cxl_dport *dport= ); pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t error); void devm_cxl_port_ras_setup(struct cxl_port *port); +void cxl_unmask_proto_interrupts(struct device *dev); #else static inline pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) @@ -94,6 +95,9 @@ static inline void devm_cxl_dport_rch_ras_setup(struct cx= l_dport *dport) static inline void devm_cxl_port_ras_setup(struct cxl_port *port) { } +static inline void cxl_unmask_proto_interrupts(struct device *dev) +{ +} #endif =20 #endif /* __CXL_PCI_H__ */ --=20 2.34.1