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Tue, 3 Feb 2026 15:28:11 +0100 From: Patrice Chotard Date: Tue, 3 Feb 2026 15:28:13 +0100 Subject: [PATCH v6 7/7] arm64: dts: st: Add boot phase tags for STMicroelectronics mp2 boards Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260203-upstream_uboot_properties-v6-7-0a2280e84d31@foss.st.com> References: <20260203-upstream_uboot_properties-v6-0-0a2280e84d31@foss.st.com> In-Reply-To: <20260203-upstream_uboot_properties-v6-0-0a2280e84d31@foss.st.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Patrick Delaunay , Christoph Niedermaier , Marek Vasut CC: , , , , , Patrice Chotard X-Mailer: b4 0.14.3 X-ClientProxiedBy: STKCAS1NODE1.st.com (10.75.128.134) To STKDAG1NODE1.st.com (10.75.128.132) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AMS1EPF0000004A:EE_|GVXPR10MB9663:EE_ X-MS-Office365-Filtering-Correlation-Id: d1f2e7a4-3a2b-4c08-071b-08de633075c7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|82310400026|1800799024|36860700013; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: +BxFQ0KklLuBJntYn61GoIJwVo0GZde0PVs8+oH8eD4FM5spf5grg3MYzuy8F6rVrnffBTIAK5EYNeaeCEPN3kCJqrN68vJUGEqN4SawTYr1hVrBzhJzKt4kqrqHOUa7UQsOPU8vd/vRpN5iKi0g8oqHSQ1esCEHFfDPYKbvXh+6knQxWC9xt8cvYrN0HGxa6BR8nAa9nPsLClpkR9dO1XXn6+E/B8nMzs6XyVkfxjZpz4taZNgo4V3Z9iqL0v13h1jOlliDeRUd3FnQ0/+pAI01S0pyT1fLvdmIkWMrTXOBwpAQ/cfnCiLIIvMEBvaSdjQKQq3BO7qkeLV90yMOVkW6MYjzn0u3aT09MyfNw5kAQBI8R0EUsFDMcZowNNIALQfc9EBPe/eCMK8G7eJTeRbOcofZT1N8A4aRr+gk9uSTzjmD3HYOu241WCI2VHpn X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2026 14:28:11.7790 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d1f2e7a4-3a2b-4c08-071b-08de633075c7 X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.59];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: AMS1EPF0000004A.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GVXPR10MB9663 The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard --- arch/arm64/boot/dts/st/stm32mp211.dtsi | 4 +- arch/arm64/boot/dts/st/stm32mp215f-dk.dts | 29 ++++++++ arch/arm64/boot/dts/st/stm32mp231.dtsi | 4 +- arch/arm64/boot/dts/st/stm32mp235f-dk.dts | 95 ++++++++++++++++++++++++++ arch/arm64/boot/dts/st/stm32mp251.dtsi | 4 +- arch/arm64/boot/dts/st/stm32mp255.dtsi | 2 +- arch/arm64/boot/dts/st/stm32mp257f-dk.dts | 103 +++++++++++++++++++++++++= +++ arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 105 +++++++++++++++++++++++++= ++++ 8 files changed, 339 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/st/stm32mp211.dtsi b/arch/arm64/boot/dts/s= t/stm32mp211.dtsi index cd078a16065e..7ddda11a6cc9 100644 --- a/arch/arm64/boot/dts/st/stm32mp211.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp211.dtsi @@ -47,7 +47,7 @@ ck_flexgen_51: clock-200000000 { }; =20 firmware { - optee { + optee: optee { compatible =3D "linaro,optee-tz"; method =3D "smc"; }; @@ -70,7 +70,7 @@ scmi_reset: protocol@16 { }; }; =20 - psci { + psci: psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; }; diff --git a/arch/arm64/boot/dts/st/stm32mp215f-dk.dts b/arch/arm64/boot/dt= s/st/stm32mp215f-dk.dts index 7bdaeaa5ab0f..6841433199eb 100644 --- a/arch/arm64/boot/dts/st/stm32mp215f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp215f-dk.dts @@ -44,6 +44,35 @@ &arm_wdt { status =3D "okay"; }; =20 +&optee { + bootph-all; +}; + +&psci { + bootph-all; +}; + +&rifsc { + bootph-all; +}; + +&scmi { + bootph-all; +}; + +&scmi_clk { + bootph-all; +}; + +&scmi_reset { + bootph-all; +}; + +&syscfg { + bootph-all; +}; + &usart2 { + bootph-all; status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/s= t/stm32mp231.dtsi index b5d81d1ee153..142a57006823 100644 --- a/arch/arm64/boot/dts/st/stm32mp231.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi @@ -59,7 +59,7 @@ optee: optee { interrupts =3D ; }; =20 - scmi { + scmi: scmi { compatible =3D "linaro,scmi-optee"; #address-cells =3D <1>; #size-cells =3D <0>; @@ -111,7 +111,7 @@ scmi_vdda18adc: regulator@7 { }; }; =20 - psci { + psci: psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 diff --git a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts b/arch/arm64/boot/dt= s/st/stm32mp235f-dk.dts index 5ecc5ef61590..2f6157957d13 100644 --- a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts @@ -95,6 +95,10 @@ &arm_wdt { status =3D "okay"; }; =20 +&bsec { + bootph-all; +}; + ðernet1 { pinctrl-0 =3D <ð1_rgmii_pins_b>; pinctrl-1 =3D <ð1_rgmii_sleep_pins_b>; @@ -117,6 +121,78 @@ phy1_eth1: ethernet-phy@1 { }; }; =20 +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + +&optee { + bootph-all; +}; + +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&psci { + bootph-all; +}; + +&rcc { + bootph-all; +}; + +&rifsc { + bootph-all; +}; + +&scmi { + bootph-all; +}; + +&scmi_clk { + bootph-all; +}; + &scmi_regu { scmi_vddio1: regulator@0 { regulator-min-microvolt =3D <1800000>; @@ -128,6 +204,10 @@ scmi_vdd_sdcard: regulator@23 { }; }; =20 +&scmi_reset { + bootph-all; +}; + &sdmmc1 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc1_b4_pins_a>; @@ -142,12 +222,27 @@ &sdmmc1 { status =3D "okay"; }; =20 +&syscfg { + bootph-all; +}; + &usart2 { pinctrl-names =3D "default", "idle", "sleep"; pinctrl-0 =3D <&usart2_pins_a>; pinctrl-1 =3D <&usart2_idle_pins_a>; pinctrl-2 =3D <&usart2_sleep_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; + +&usart2_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 8b925ed0d881..80ff8a43801e 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -68,7 +68,7 @@ optee: optee { interrupts =3D ; }; =20 - scmi { + scmi: scmi { compatible =3D "linaro,scmi-optee"; #address-cells =3D <1>; #size-cells =3D <0>; @@ -139,7 +139,7 @@ v2m0: v2m@48090000 { }; }; =20 - psci { + psci: psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/s= t/stm32mp255.dtsi index 7a598f53a2a0..3ba4e6166586 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -40,4 +40,4 @@ venc: venc@480e0000 { clocks =3D <&rcc CK_BUS_VENC>; access-controllers =3D <&rifsc 90>; }; -}; \ No newline at end of file +}; diff --git a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts b/arch/arm64/boot/dt= s/st/stm32mp257f-dk.dts index 4135e7c0d9a3..a6853d4aa45b 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts @@ -102,6 +102,10 @@ &arm_wdt { status =3D "okay"; }; =20 +&bsec { + bootph-all; +}; + ðernet1 { pinctrl-0 =3D <ð1_rgmii_pins_b>; pinctrl-1 =3D <ð1_rgmii_sleep_pins_b>; @@ -124,6 +128,86 @@ phy1_eth1: ethernet-phy@1 { }; }; =20 +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + +&optee { + bootph-all; +}; + +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&psci { + bootph-all; +}; + +&rcc { + bootph-all; +}; + +&rifsc { + bootph-all; +}; + +&scmi { + bootph-all; +}; + +&scmi_clk { + bootph-all; +}; + &scmi_regu { scmi_vddio1: regulator@0 { regulator-min-microvolt =3D <1800000>; @@ -135,6 +219,10 @@ scmi_vdd_sdcard: regulator@23 { }; }; =20 +&scmi_reset { + bootph-all; +}; + &sdmmc1 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc1_b4_pins_a>; @@ -149,12 +237,27 @@ &sdmmc1 { status =3D "okay"; }; =20 +&syscfg { + bootph-all; +}; + &usart2 { pinctrl-names =3D "default", "idle", "sleep"; pinctrl-0 =3D <&usart2_pins_a>; pinctrl-1 =3D <&usart2_idle_pins_a>; pinctrl-2 =3D <&usart2_sleep_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; + +&usart2_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/d= ts/st/stm32mp257f-ev1.dts index 852a73b0c516..cbf08d4304f3 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -167,6 +167,10 @@ &arm_wdt { status =3D "okay"; }; =20 +&bsec { + bootph-all; +}; + &combophy { clocks =3D <&rcc CK_BUS_USB3PCIEPHY>, <&rcc CK_KER_USB3PCIEPHY>, <&pad_cl= k>; clock-names =3D "apb", "ker", "pad"; @@ -253,6 +257,54 @@ phy0_eth2: ethernet-phy@1 { }; }; =20 +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + &i2c2 { pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&i2c2_pins_a>; @@ -338,6 +390,7 @@ timer { }; =20 <dc { + bootph-all; status =3D "okay"; port { ltdc_ep0_out: endpoint { @@ -347,6 +400,7 @@ ltdc_ep0_out: endpoint { }; =20 &lvds { + bootph-all; status =3D "okay"; ports { #address-cells =3D <1>; @@ -368,6 +422,10 @@ lvds_out0: endpoint { }; }; =20 +&optee { + bootph-all; +}; + &pcie_ep { pinctrl-names =3D "default", "init"; pinctrl-0 =3D <&pcie_pins_a>; @@ -389,10 +447,38 @@ pcie@0,0 { }; }; =20 +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&psci { + bootph-all; +}; + +&rcc { + bootph-all; +}; + &rtc { status =3D "okay"; }; =20 +&rifsc { + bootph-all; +}; + +&scmi { + bootph-all; +}; + +&scmi_clk { + bootph-all; +}; + &scmi_regu { scmi_vddio1: regulator@0 { regulator-min-microvolt =3D <1800000>; @@ -424,6 +510,10 @@ scmi_vdd_sdcard: regulator@23 { }; }; =20 +&scmi_reset { + bootph-all; +}; + &sdmmc1 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc1_b4_pins_a>; @@ -438,6 +528,10 @@ &sdmmc1 { status =3D "okay"; }; =20 +&syscfg { + bootph-all; +}; + &spi3 { pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&spi3_pins_a>; @@ -515,11 +609,22 @@ &usart2 { pinctrl-0 =3D <&usart2_pins_a>; pinctrl-1 =3D <&usart2_idle_pins_a>; pinctrl-2 =3D <&usart2_sleep_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; =20 +&usart2_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usart6 { pinctrl-names =3D "default", "idle", "sleep"; pinctrl-0 =3D <&usart6_pins_a>; --=20 2.43.0