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Tue, 3 Feb 2026 15:28:07 +0100 From: Patrice Chotard Date: Tue, 3 Feb 2026 15:28:07 +0100 Subject: [PATCH v6 1/7] ARM: dts: stm32: Add boot phase tags for STMicroelectronics f4 boards Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260203-upstream_uboot_properties-v6-1-0a2280e84d31@foss.st.com> References: <20260203-upstream_uboot_properties-v6-0-0a2280e84d31@foss.st.com> In-Reply-To: <20260203-upstream_uboot_properties-v6-0-0a2280e84d31@foss.st.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Patrick Delaunay , Christoph Niedermaier , Marek Vasut CC: , , , , , Patrice Chotard X-Mailer: b4 0.14.3 X-ClientProxiedBy: STKCAS1NODE1.st.com (10.75.128.134) To STKDAG1NODE1.st.com (10.75.128.132) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AMS1EPF0000004C:EE_|PA1PR10MB9102:EE_ X-MS-Office365-Filtering-Correlation-Id: 6037ad68-cefe-4ebf-51bb-08de63307369 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|82310400026|36860700013; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: e8pph64XPapN+nWZAwTn/EeV4F0xE6mM61cc6Rt2jpPH09LxFIcxoVaGGa45ULdBM6MomuwBJOSJ6ILKLslXfzhitxSEs5zt3cOsyKSlo3n0k7K4axAuU1YaacwiJElMyNaM0Ik3U82isIbVcSPS4rEY4LONzMTnI7V1LMwvGPUYAJrziydrBO6AJBa3g79XqBRDMxklbjdiVe4gid/F3yDzCTTLCMi4ZOWJNlhasCwu5X2BFpt7nH9LaTE6hbq0Bs4VwAKk4gNlyEFwYj6hZXgKfU6QzDpQrZTqCLH+RgCWvAA5eRvSSZMb84pnvGUg9CN5vBs36hoKl1IQQdG95xQwZjZ8aFmtQp6eZ2wKdgj4QFei99VQweEskRHvzbak1RtFk9Qc/KD/VDezf5gDk7vU4vy0pWOKiXpTjz+MigOl1WbLA7tKpG8Ri0JYq8L2 X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2026 14:28:07.8232 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6037ad68-cefe-4ebf-51bb-08de63307369 X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.59];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: AMS1EPF0000004C.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA1PR10MB9102 The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/st/stm32429i-eval.dts | 80 ++++++++++++++++++++++++++++= ++++ arch/arm/boot/dts/st/stm32f429-disco.dts | 80 ++++++++++++++++++++++++++++= ++++ arch/arm/boot/dts/st/stm32f469-disco.dts | 72 ++++++++++++++++++++++++++++ 3 files changed, 232 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32429i-eval.dts b/arch/arm/boot/dts/st= /stm32429i-eval.dts index f4b1c4eb64f2..8a08b9f6b837 100644 --- a/arch/arm/boot/dts/st/stm32429i-eval.dts +++ b/arch/arm/boot/dts/st/stm32429i-eval.dts @@ -188,6 +188,15 @@ adc3: adc@200 { =20 &clk_hse { clock-frequency =3D <25000000>; + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_i2s_ckin { + bootph-all; }; =20 &crc { @@ -209,6 +218,50 @@ dcmi_0: endpoint { }; }; =20 +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + &i2c1 { pinctrl-0 =3D <&i2c1_pins>; pinctrl-names =3D "default"; @@ -278,6 +331,18 @@ phy1: ethernet-phy@1 { }; }; =20 +&pinctrl { + bootph-all; +}; + +&pwrcfg { + bootph-all; +}; + +&rcc { + bootph-all; +}; + &rtc { status =3D "okay"; }; @@ -293,6 +358,10 @@ &sdio { max-frequency =3D <12500000>; }; =20 +&syscfg { + bootph-all; +}; + &timers1 { status =3D "okay"; =20 @@ -325,6 +394,7 @@ &timers5 { /* Override timer5 to act as clockevent */ compatible =3D "st,stm32-timer"; interrupts =3D <50>; + bootph-all; status =3D "okay"; /delete-property/#address-cells; /delete-property/#size-cells; @@ -339,6 +409,16 @@ &usart1 { status =3D "okay"; }; =20 +&usart1_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_hs { dr_mode =3D "host"; phys =3D <&usbotg_hs_phy>; diff --git a/arch/arm/boot/dts/st/stm32f429-disco.dts b/arch/arm/boot/dts/s= t/stm32f429-disco.dts index ded369abee4f..047845ab3d5f 100644 --- a/arch/arm/boot/dts/st/stm32f429-disco.dts +++ b/arch/arm/boot/dts/st/stm32f429-disco.dts @@ -113,12 +113,65 @@ vcc5v_otg: vcc5v-otg-regulator { =20 &clk_hse { clock-frequency =3D <8000000>; + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_i2s_ckin { + bootph-all; }; =20 &crc { status =3D "okay"; }; =20 +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + &i2c3 { pinctrl-names =3D "default"; pinctrl-0 =3D <&i2c3_pins>; @@ -176,6 +229,18 @@ ltdc_out_rgb: endpoint { }; }; =20 +&pinctrl { + bootph-all; +}; + +&pwrcfg { + bootph-all; +}; + +&rcc { + bootph-all; +}; + &rtc { assigned-clocks =3D <&rcc 1 CLK_RTC>; assigned-clock-parents =3D <&rcc 1 CLK_LSI>; @@ -216,10 +281,15 @@ panel_in_rgb: endpoint { }; }; =20 +&syscfg { + bootph-all; +}; + &timers5 { /* Override timer5 to act as clockevent */ compatible =3D "st,stm32-timer"; interrupts =3D <50>; + bootph-all; status =3D "okay"; /delete-property/#address-cells; /delete-property/#size-cells; @@ -234,6 +304,16 @@ &usart1 { status =3D "okay"; }; =20 +&usart1_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_hs { compatible =3D "st,stm32f4x9-fsotg"; dr_mode =3D "host"; diff --git a/arch/arm/boot/dts/st/stm32f469-disco.dts b/arch/arm/boot/dts/s= t/stm32f469-disco.dts index 943afba06b5f..ecd33d6003b3 100644 --- a/arch/arm/boot/dts/st/stm32f469-disco.dts +++ b/arch/arm/boot/dts/st/stm32f469-disco.dts @@ -181,7 +181,52 @@ dsi_panel_in: endpoint { }; }; =20 +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + <dc { + bootph-all; status =3D "okay"; =20 port { @@ -191,10 +236,26 @@ ltdc_out_dsi: endpoint { }; }; =20 +&pinctrl { + bootph-all; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ptNjdaswbdzLDiipKwMwKxyZwHwoRa+3uTkci2Uw1wA6n3j/AJElpFAk728US4BVGizdCUsAAnJIyHyzaAAPTwsqiQACcWXdlU5tx7ZLXTAK+L1ZLKZzcv2yTHL743d2dlqC7xlXJ7HYljcS6FOqzKk9P4B5zVanKTRXY/0FwNyi/D2hOFNrrBw2tlBL4Fme0d09mf9GuEGWX6sIXFMSseGhZqhG3a6jyXibLXlA1n1+00JvnJUVS5RI233f8TvmWe4Cb/eLEcLoBQQ8iMHYJ6SpW8CDEUI3dbaP4nmWu5pNMj2pvHmSSBQHz/ubGBWLcqQ2yXQr+guEN4vFH+ReGcZWGNFOWjGs/Dpu9Px+PkOp5Fa3sVK1mtHs1AhIzw46XU9XoAzas6NCHpw8MUz8TG7SZDPe6jW7DpuJScZCs43mlU0zU/485ZUF39L3cQs1 X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2026 14:28:08.5332 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 143a3de6-2f7a-4bd1-53f2-08de633073d5 X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.60];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: AM3PEPF00009B9B.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAVPR10MB7355 The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/st/stm32746g-eval.dts | 10 +++++ arch/arm/boot/dts/st/stm32f746-disco.dts | 75 ++++++++++++++++++++++++++++= +++ arch/arm/boot/dts/st/stm32f746.dtsi | 2 +- arch/arm/boot/dts/st/stm32f769-disco.dts | 76 ++++++++++++++++++++++++++++= ++-- 4 files changed, 158 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32746g-eval.dts b/arch/arm/boot/dts/st= /stm32746g-eval.dts index 6772c1f9d03e..d66b670de6f2 100644 --- a/arch/arm/boot/dts/st/stm32746g-eval.dts +++ b/arch/arm/boot/dts/st/stm32746g-eval.dts @@ -226,6 +226,16 @@ &usart1 { status =3D "okay"; }; =20 +&usart1_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_hs { dr_mode =3D "otg"; phys =3D <&usbotg_hs_phy>; diff --git a/arch/arm/boot/dts/st/stm32f746-disco.dts b/arch/arm/boot/dts/s= t/stm32f746-disco.dts index 61ca41ea523e..5db37bbe6c2a 100644 --- a/arch/arm/boot/dts/st/stm32f746-disco.dts +++ b/arch/arm/boot/dts/st/stm32f746-disco.dts @@ -150,6 +150,51 @@ panel_in_rgb: endpoint { =20 &clk_hse { clock-frequency =3D <25000000>; + bootph-all; +}; + +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; }; =20 &i2c1 { @@ -179,6 +224,7 @@ touchscreen@38 { <dc { pinctrl-0 =3D <<dc_pins_a>; pinctrl-names =3D "default"; + bootph-all; status =3D "okay"; =20 port { @@ -188,6 +234,22 @@ ltdc_out_rgb: endpoint { }; }; =20 +&pinctrl { + bootph-all; +}; + +&pwrcfg { + bootph-all; +}; + +&rcc { + bootph-all; +}; + +&soc { + bootph-all; +}; + &sdio1 { status =3D "okay"; vmmc-supply =3D <&vcc_3v3>; @@ -203,6 +265,7 @@ &timers5 { /* Override timer5 to act as clockevent */ compatible =3D "st,stm32-timer"; interrupts =3D <50>; + bootph-all; status =3D "okay"; /delete-property/#address-cells; /delete-property/#size-cells; @@ -214,9 +277,21 @@ &timers5 { &usart1 { pinctrl-0 =3D <&usart1_pins_b>; pinctrl-names =3D "default"; + bootph-all; status =3D "okay"; }; =20 + +&usart1_pins_b { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_fs { dr_mode =3D "host"; pinctrl-0 =3D <&usbotg_fs_pins_a>; diff --git a/arch/arm/boot/dts/st/stm32f746.dtsi b/arch/arm/boot/dts/st/stm= 32f746.dtsi index 208f8c6dfc9d..1fede5bdc347 100644 --- a/arch/arm/boot/dts/st/stm32f746.dtsi +++ b/arch/arm/boot/dts/st/stm32f746.dtsi @@ -75,7 +75,7 @@ clk_i2s_ckin: clk-i2s-ckin { }; }; =20 - soc { + soc: soc { timers2: timers@40000000 { #address-cells =3D <1>; #size-cells =3D <0>; diff --git a/arch/arm/boot/dts/st/stm32f769-disco.dts b/arch/arm/boot/dts/s= t/stm32f769-disco.dts index e5854fa1071b..7338e78847b6 100644 --- a/arch/arm/boot/dts/st/stm32f769-disco.dts +++ b/arch/arm/boot/dts/st/stm32f769-disco.dts @@ -128,10 +128,6 @@ vcc_3v3: vcc-3v3 { }; }; =20 -&rcc { - compatible =3D "st,stm32f769-rcc", "st,stm32f746-rcc", "st,stm32-rcc"; -}; - &cec { pinctrl-0 =3D <&cec_pins_a>; pinctrl-names =3D "default"; @@ -140,11 +136,13 @@ &cec { =20 &clk_hse { clock-frequency =3D <25000000>; + bootph-all; }; =20 &dsi { #address-cells =3D <1>; #size-cells =3D <0>; + bootph-all; status =3D "okay"; =20 ports { @@ -181,6 +179,50 @@ dsi_panel_in: endpoint { }; }; =20 +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + &i2c1 { pinctrl-0 =3D <&i2c1_pins_b>; pinctrl-names =3D "default"; @@ -190,6 +232,7 @@ &i2c1 { }; =20 <dc { + bootph-all; status =3D "okay"; =20 port { @@ -199,6 +242,19 @@ ltdc_out_dsi: endpoint { }; }; =20 +&pinctrl { + bootph-all; +}; + +&pwrcfg { + bootph-all; +}; + +&rcc { + compatible =3D "st,stm32f769-rcc", "st,stm32f746-rcc", "st,stm32-rcc"; + bootph-all; +}; + &rtc { status =3D "okay"; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: dq9eZpyKxVYwhgluyRBZAGefZVWSI5ZpntX3xSQxVzQMgcRB4/8YGYycYeEqpewavB8l6/NAQ0HfW6t6nNR7EEyODy5q9Xt9sNb+lKCMRGq+xN/3u1wGHT0fM8C48RfvYghIXZAMPcsQ7dFUB7dE11IRzHFwJnpSwiFsrb3fHz91uDfkt/rEaOtTw7WLVwU2WHxhOkkOL/5n7tH8d65sZuFzRpmxHVTEz9sKv1Imda6ZUL9elmOjGI8X872bOrDCpHTUlC6XFlI4dN05x+q9jCGwPnw5ZM4juZwuGHby+WhhSSS1g4dqucrn8LMozN56avynWcoJ736z5fTPtj+51jTcGCwJwKmyKTchHFEcpUu1NDswm+4Vsh5kbg9VDZFgSaXNxGeOznJaF6dfhdM2XD1G0uC7pMTf2G9lCvFPaQsmuuw5oGUTPeL45qDzWKoZ X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2026 14:28:09.2184 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8722c0a1-39c7-4662-8bc9-08de6330743e X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.59];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: AMS1EPF00000048.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB4PR10MB7495 The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/st/stm32h743i-disco.dts | 69 ++++++++++++++++++++++++++= ++++ arch/arm/boot/dts/st/stm32h743i-eval.dts | 69 ++++++++++++++++++++++++++= ++++ arch/arm/boot/dts/st/stm32h747i-disco.dts | 69 ++++++++++++++++++++++++++= ++++ arch/arm/boot/dts/st/stm32h750i-art-pi.dts | 69 ++++++++++++++++++++++++++= ++++ 4 files changed, 276 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32h743i-disco.dts b/arch/arm/boot/dts/= st/stm32h743i-disco.dts index 78d55b77db7c..1b4b9bc5c72d 100644 --- a/arch/arm/boot/dts/st/stm32h743i-disco.dts +++ b/arch/arm/boot/dts/st/stm32h743i-disco.dts @@ -107,6 +107,59 @@ u-boot { =20 &clk_hse { clock-frequency =3D <25000000>; + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_i2s { + bootph-all; +}; + +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; }; =20 &mac { @@ -126,6 +179,18 @@ phy0: ethernet-phy@0 { }; }; =20 +&pinctrl { + bootph-all; +}; + +&pwrcfg { + bootph-all; +}; + +&rcc { + bootph-all; +}; + &sdmmc1 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc1_b4_pins_a>; @@ -138,6 +203,10 @@ &sdmmc1 { status =3D "okay"; }; =20 +&timer5 { + bootph-all; +}; + &usart2 { pinctrl-0 =3D <&usart2_pins_a>; pinctrl-names =3D "default"; diff --git a/arch/arm/boot/dts/st/stm32h743i-eval.dts b/arch/arm/boot/dts/s= t/stm32h743i-eval.dts index e5e10b0758ee..55674fe05431 100644 --- a/arch/arm/boot/dts/st/stm32h743i-eval.dts +++ b/arch/arm/boot/dts/st/stm32h743i-eval.dts @@ -124,6 +124,59 @@ adc1: adc@0 { =20 &clk_hse { clock-frequency =3D <25000000>; + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_i2s { + bootph-all; +}; + +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; }; =20 &i2c1 { @@ -155,6 +208,18 @@ phy0: ethernet-phy@0 { }; }; =20 +&pinctrl { + bootph-all; +}; + +&pwrcfg { + bootph-all; +}; + +&rcc { + bootph-all; +}; + &sdmmc1 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; @@ -169,6 +234,10 @@ &sdmmc1 { status =3D "okay"; }; =20 +&timer5 { + bootph-all; +}; + &usart1 { pinctrl-0 =3D <&usart1_pins_a>; pinctrl-names =3D "default"; diff --git a/arch/arm/boot/dts/st/stm32h747i-disco.dts b/arch/arm/boot/dts/= st/stm32h747i-disco.dts index c9dcc680e26d..ef36454808d5 100644 --- a/arch/arm/boot/dts/st/stm32h747i-disco.dts +++ b/arch/arm/boot/dts/st/stm32h747i-disco.dts @@ -104,6 +104,59 @@ u-boot { =20 &clk_hse { clock-frequency =3D <25000000>; + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_i2s { + bootph-all; +}; + +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; }; =20 &mac { @@ -123,6 +176,18 @@ phy0: ethernet-phy@0 { }; }; =20 +&pinctrl { + bootph-all; +}; + +&pwrcfg { + bootph-all; +}; + +&rcc { + bootph-all; +}; + &sdmmc1 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc1_b4_pins_a>; @@ -136,6 +201,10 @@ &sdmmc1 { status =3D "okay"; }; =20 +&timer5 { + bootph-all; +}; + &usart1 { pinctrl-0 =3D <&usart1_pins_b>; pinctrl-names =3D "default"; diff --git a/arch/arm/boot/dts/st/stm32h750i-art-pi.dts b/arch/arm/boot/dts= /st/stm32h750i-art-pi.dts index 56c53e262da7..8dddc70c37a1 100644 --- a/arch/arm/boot/dts/st/stm32h750i-art-pi.dts +++ b/arch/arm/boot/dts/st/stm32h750i-art-pi.dts @@ -114,6 +114,15 @@ wlan_pwr: regulator-wlan { =20 &clk_hse { clock-frequency =3D <25000000>; + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_i2s { + bootph-all; }; =20 &dma1 { @@ -124,6 +133,50 @@ &dma2 { status =3D "okay"; }; =20 +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + &mac { status =3D "disabled"; pinctrl-0 =3D <ðernet_rmii>; @@ -141,6 +194,18 @@ phy0: ethernet-phy@0 { }; }; =20 +&pinctrl { + bootph-all; +}; + +&pwrcfg { + bootph-all; +}; + +&rcc { + bootph-all; +}; + &sdmmc1 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc1_b4_pins_a>; @@ -196,6 +261,10 @@ partition@0 { }; }; =20 +&timer5 { + bootph-all; +}; + &usart2 { pinctrl-0 =3D <&usart2_pins_a>; pinctrl-names =3D "default"; --=20 2.43.0 From nobody Mon Feb 9 07:42:35 2026 Received: from AM0PR83CU005.outbound.protection.outlook.com (mail-westeuropeazon11010020.outbound.protection.outlook.com [52.101.69.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59E783A9606; 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Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi | 56 ++++++++++++---------= ---- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi b/arch/arm/boo= t/dts/st/stm32mp13xx-dhcor-som.dtsi index c18156807027..54ece71085c1 100644 --- a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi @@ -241,34 +241,6 @@ flash0: flash@0 { }; }; =20 -/* Console UART */ -&uart4 { - pinctrl-names =3D "default", "sleep", "idle"; - pinctrl-0 =3D <&uart4_pins_b>; - pinctrl-1 =3D <&uart4_sleep_pins_b>; - pinctrl-2 =3D <&uart4_idle_pins_b>; - /delete-property/dmas; - /delete-property/dma-names; - status =3D "okay"; -}; - -/* Bluetooth */ -&uart7 { - pinctrl-names =3D "default", "sleep", "idle"; - pinctrl-0 =3D <&uart7_pins_a>; - pinctrl-1 =3D <&uart7_sleep_pins_a>; - pinctrl-2 =3D <&uart7_idle_pins_a>; - uart-has-rtscts; - status =3D "okay"; - - bluetooth { - compatible =3D "infineon,cyw43439-bt", "brcm,bcm4329-bt"; - max-speed =3D <3000000>; - device-wakeup-gpios =3D <&gpiog 9 GPIO_ACTIVE_HIGH>; - shutdown-gpios =3D <&gpioi 2 GPIO_ACTIVE_HIGH>; - }; -}; - /* SDIO WiFi */ &sdmmc1 { pinctrl-names =3D "default", "opendrain", "sleep"; @@ -312,3 +284,31 @@ &sdmmc2 { vqmmc-supply =3D <&vdd>; status =3D "okay"; }; + +/* Console UART */ +&uart4 { + pinctrl-names =3D "default", "sleep", "idle"; + pinctrl-0 =3D <&uart4_pins_b>; + pinctrl-1 =3D <&uart4_sleep_pins_b>; + pinctrl-2 =3D <&uart4_idle_pins_b>; + /delete-property/dmas; + /delete-property/dma-names; + status =3D "okay"; +}; + +/* Bluetooth */ +&uart7 { + pinctrl-names =3D "default", "sleep", "idle"; + pinctrl-0 =3D <&uart7_pins_a>; + pinctrl-1 =3D <&uart7_sleep_pins_a>; + pinctrl-2 =3D <&uart7_idle_pins_a>; + uart-has-rtscts; + status =3D "okay"; + + bluetooth { + compatible =3D "infineon,cyw43439-bt", "brcm,bcm4329-bt"; + max-speed =3D <3000000>; + device-wakeup-gpios =3D <&gpiog 9 GPIO_ACTIVE_HIGH>; + shutdown-gpios =3D <&gpioi 2 GPIO_ACTIVE_HIGH>; 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Tue, 3 Feb 2026 15:28:09 +0100 From: Patrice Chotard Date: Tue, 3 Feb 2026 15:28:11 +0100 Subject: [PATCH v6 5/7] ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp13 boards Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260203-upstream_uboot_properties-v6-5-0a2280e84d31@foss.st.com> References: <20260203-upstream_uboot_properties-v6-0-0a2280e84d31@foss.st.com> In-Reply-To: <20260203-upstream_uboot_properties-v6-0-0a2280e84d31@foss.st.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Patrick Delaunay , Christoph Niedermaier , Marek Vasut CC: , , , , , Patrice Chotard X-Mailer: b4 0.14.3 X-ClientProxiedBy: STKCAS1NODE1.st.com (10.75.128.134) To STKDAG1NODE1.st.com (10.75.128.132) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AMS1EPF0000004C:EE_|AS1PR10MB5553:EE_ X-MS-Office365-Filtering-Correlation-Id: 39d0b838-6355-4ef4-1a48-08de633074fc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|7416014|376014; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: DPQ8npYR1ZjUoz3bh31+ZNXzcuT/kx3TmtF7tBEhGff/BgT0QPQ9Q+hY5Zl4w/5VJ5H8X3/DJCaG6EzabQwnbx+16b6LMiFRlSqKFHu7uPhlKWeClhqkWT4XqWg7AUxf0f0sLFs1W+jELye73kWBgaki9Ih7o4jYayovS7GBmVHQudEn3iflDfVh/vimp9jE4U3hwEA+uCTc79amgTDTo8VZrzNlhfjY/RDcn46yiOcRVHZAZHVGg2WdTNR/yb96Gh/hIjnCKHEPLeEw7PEjucUK11/eNlA8ikQW5FmfgKo4koTyBoaFGXltuYoNkmJ9cFC/2ld+nQcDGisFRWESreJQEwHN1cUEL7Aup4tH6rI6zJfUJIV6bVjvEfjpBEOsOShr3Mz2HX2F9WWpm4bQ0rkA/1p6IFwt7P0M5IvkXNyi2evYfo5vv5coP2GCm9my X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2026 14:28:10.4557 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 39d0b838-6355-4ef4-1a48-08de633074fc X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.59];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: AMS1EPF0000004C.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS1PR10MB5553 The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/st/stm32mp131.dtsi | 4 +- arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts | 21 +++++ arch/arm/boot/dts/st/stm32mp135f-dk.dts | 101 +++++++++++++++++++= ++++ arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi | 101 +++++++++++++++++++= ++++ 4 files changed, 225 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/st= m32mp131.dtsi index b9657ff91c23..3d77bdaa945a 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -36,7 +36,7 @@ arm_wdt: watchdog { }; =20 firmware { - optee { + optee: optee { method =3D "smc"; compatible =3D "linaro,optee-tz"; interrupt-parent =3D <&intc>; @@ -91,7 +91,7 @@ intc: interrupt-controller@a0021000 { <0xa0022000 0x2000>; }; =20 - psci { + psci: psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; }; diff --git a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts b/arch/arm/bo= ot/dts/st/stm32mp135f-dhcor-dhsbc.dts index 9902849ed040..526ab2e1a93c 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts @@ -350,6 +350,21 @@ timer@12 { }; }; =20 +&uart4 { + bootph-all; +}; + +&uart4_pins_b { + bootph-all; + + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usart1 { /* Expansion connector: RX:pin33 TX:pin37 */ pinctrl-names =3D "default", "sleep", "idle"; pinctrl-0 =3D <&usart1_pins_b>; @@ -367,6 +382,10 @@ &usart2 { /* Expansion connector: RX:pin10 TX:pin8 RTS= :pin11 CTS:pin36 */ status =3D "okay"; }; =20 +&usbphyc { + bootph-all; +}; + &usbh_ehci { phys =3D <&usbphyc_port0>; status =3D "okay"; @@ -432,6 +451,7 @@ connector { =20 /* LDO2 is expansion connector 3V3 supply on STM32MP13xx DHCOR DHSBC rev.2= 00 */ &vdd_ldo2 { + bootph-all; regulator-always-on; regulator-boot-on; regulator-min-microvolt =3D <3300000>; @@ -440,6 +460,7 @@ &vdd_ldo2 { =20 /* LDO5 is carrier board 3V3 supply on STM32MP13xx DHCOR DHSBC rev.200 */ &vdd_sd { + bootph-all; regulator-always-on; regulator-boot-on; regulator-min-microvolt =3D <3300000>; diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st= /stm32mp135f-dk.dts index 8dcf68b212b4..59c0d41acd54 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -179,6 +179,10 @@ &arm_wdt { status =3D "okay"; }; =20 +&bsec { + bootph-all; +}; + &crc1 { status =3D "okay"; }; @@ -226,6 +230,42 @@ phy0_eth1: ethernet-phy@0 { }; }; =20 +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + &i2c1 { pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&i2c1_pins_a>; @@ -360,6 +400,7 @@ goodix: goodix-ts@5d { =20 &iwdg2 { timeout-sec =3D <32>; + bootph-all; status =3D "okay"; }; =20 @@ -367,6 +408,7 @@ <dc { pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <<dc_pins_a>; pinctrl-1 =3D <<dc_sleep_pins_a>; + bootph-some-ram; status =3D "okay"; =20 port { @@ -376,6 +418,22 @@ ltdc_out_rgb: endpoint { }; }; =20 +&optee { + bootph-all; +}; + +&pinctrl { + bootph-all; +}; + +&psci { + bootph-some-ram; +}; + +&rcc { + bootph-all; +}; + &rtc { pinctrl-names =3D "default"; pinctrl-0 =3D <&rtc_rsvd_pins_a>; @@ -387,6 +445,14 @@ rtc_lsco_pins_a: rtc-lsco-0 { }; }; =20 +&scmi { + bootph-all; +}; + +&scmi_clk { + bootph-all; +}; + &scmi_regu { scmi_vdd_adc: regulator@10 { reg =3D ; @@ -410,6 +476,10 @@ scmi_v3v3_sw: regulator@19 { }; }; =20 +&scmi_reset { + bootph-all; +}; + &sdmmc1 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; @@ -420,9 +490,24 @@ &sdmmc1 { st,neg-edge; bus-width =3D <4>; vmmc-supply =3D <&scmi_vdd_sd>; + bootph-pre-ram; status =3D "okay"; }; =20 +&sdmmc1_b4_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&sdmmc1_clk_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + /* Wifi */ &sdmmc2 { pinctrl-names =3D "default", "opendrain", "sleep"; @@ -454,6 +539,10 @@ &spi5 { status =3D "disabled"; }; =20 +&syscfg { + bootph-all; +}; + &timers3 { /delete-property/dmas; /delete-property/dma-names; @@ -535,9 +624,20 @@ &uart4 { pinctrl-2 =3D <&uart4_idle_pins_a>; /delete-property/dmas; /delete-property/dma-names; + bootph-all; status =3D "okay"; }; =20 +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &uart8 { pinctrl-names =3D "default", "sleep", "idle"; pinctrl-0 =3D <&uart8_pins_a>; @@ -601,6 +701,7 @@ usbotg_hs_ep: endpoint { }; =20 &usbphyc { + bootph-all; status =3D "okay"; }; =20 diff --git a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi b/arch/arm/boo= t/dts/st/stm32mp13xx-dhcor-som.dtsi index 54ece71085c1..4efaca84a72c 100644 --- a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi @@ -54,6 +54,46 @@ vin: vin { }; }; =20 +&bsec { + bootph-all; +}; + +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + &i2c3 { i2c-scl-rising-time-ns =3D <96>; i2c-scl-falling-time-ns =3D <3>; @@ -216,9 +256,18 @@ eeprom0wl: eeprom@58 { =20 &iwdg2 { timeout-sec =3D <32>; + bootph-all; status =3D "okay"; }; =20 +&pinctrl { + bootph-all; +}; + +&psci { + bootph-some-ram; +}; + &qspi { pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&qspi_clk_pins_a @@ -229,6 +278,7 @@ &qspi_bk1_sleep_pins_a &qspi_cs1_sleep_pins_a>; #address-cells =3D <1>; #size-cells =3D <0>; + bootph-all; status =3D "okay"; =20 flash0: flash@0 { @@ -238,9 +288,35 @@ flash0: flash@0 { spi-max-frequency =3D <108000000>; #address-cells =3D <1>; #size-cells =3D <1>; + bootph-all; }; }; =20 +&qspi_clk_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + +&qspi_bk1_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + +&qspi_cs1_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + +&rcc { + bootph-all; +}; + /* SDIO WiFi */ &sdmmc1 { pinctrl-names =3D "default", "opendrain", "sleep"; @@ -285,6 +361,10 @@ &sdmmc2 { status =3D "okay"; }; =20 +&syscfg { + bootph-all; +}; + /* Console UART */ &uart4 { pinctrl-names =3D "default", "sleep", "idle"; @@ -312,3 +392,24 @@ bluetooth { shutdown-gpios =3D <&gpioi 2 GPIO_ACTIVE_HIGH>; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 1wy0WNDKBw0uo+Zf/79nhG4UU8I6Fg94CFP15gk0lqNwnNJRbDwDFU90Zt8vady/mBA7V5iARO4s7RiIfQEO/dYHg8KEYyMzKTouCB7Xh+LVPW+fS6LtFrqf6WjYy/n3lybbWhXeMkErEC5R4JO3d/KQVGNFZCdFc0y4fu6smcxqxxphY3OnMP4o6Agu3LipadVHdzydxwENDKcLlKpHdiqZkNljOLspdvU5IdD3wMN+6DmlPMTKJJyBdizAwt3avOrOXrepHF1DP7dFUc3fCarB7O2taF84IFD2B/tgzPZJEL4cKyCZRCY1xwEa8Q5ounM62S0u4sqbqPRQNm+NpnrDL/HNSpkxaDuRab1o4cmBhn3fDmgkSDHUy6UKEIKXwGYM5jmERELXkmjtgTR/dLiKp6sEdaVzFRqMQMgI7V5AIIzgeFy/j+tNc81B7B62 X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2026 14:28:11.1785 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 83f24b73-ce88-4fb1-8a17-08de6330756a X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.60];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: AM3PEPF00009B9F.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR10MB8823 The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/st/stm32mp151.dtsi | 2 +- arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts | 19 +++ .../st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts | 1 + .../dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts | 25 +++ .../dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts | 26 ++++ .../boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi | 100 ++++++++++++ ...m32mp157a-microgea-stm32mp1-microdev2.0-of7.dts | 27 ++++ .../stm32mp157a-microgea-stm32mp1-microdev2.0.dts | 27 ++++ .../boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi | 97 ++++++++++++ arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts | 5 + arch/arm/boot/dts/st/stm32mp157c-dk2.dts | 1 + arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts | 19 +++ arch/arm/boot/dts/st/stm32mp157c-ed1.dts | 151 ++++++++++++++++++ arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts | 5 + arch/arm/boot/dts/st/stm32mp157c-ev1.dts | 38 +++++ arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts | 1 + arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi | 119 ++++++++++++++ arch/arm/boot/dts/st/stm32mp157c-odyssey.dts | 21 +++ arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts | 1 + arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi | 5 + arch/arm/boot/dts/st/stm32mp157f-dk2.dts | 1 + arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi | 1 + arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi | 172 +++++++++++++++++= ++++ .../boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi | 55 +++++++ .../boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi | 50 ++++++ arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi | 157 +++++++++++++++++= ++ .../boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi | 50 ++++++ arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi | 122 +++++++++++++++ 28 files changed, 1297 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/st= m32mp151.dtsi index b1b568dfd126..ada55b2c1aa2 100644 --- a/arch/arm/boot/dts/st/stm32mp151.dtsi +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi @@ -30,7 +30,7 @@ arm-pmu { interrupt-parent =3D <&intc>; }; =20 - psci { + psci: psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; }; diff --git a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/= dts/st/stm32mp157a-dk1-scmi.dts index 847b360f02fc..b81b6e168b67 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts @@ -65,6 +65,7 @@ &m4_rproc { &optee { interrupt-parent =3D <&intc>; interrupts =3D ; + bootph-some-ram; }; =20 &rcc { @@ -85,3 +86,21 @@ &rng1 { &rtc { clocks =3D <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; }; + +&scmi { + bootph-some-ram; +}; + +&uart4 { + bootph-all; +}; + +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.d= ts b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts index df97e03d2a5a..4ad1313efca9 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts @@ -92,6 +92,7 @@ bridge_out: endpoint { }; =20 <dc { + bootph-some-ram; status =3D "okay"; =20 port { diff --git a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts b/= arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts index 60ce4425a7fd..ac4e313ca371 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts @@ -35,15 +35,40 @@ &sdmmc1 { pinctrl-2 =3D <&sdmmc1_b4_sleep_pins_a>; st,neg-edge; vmmc-supply =3D <&v3v3>; + bootph-all; status =3D "okay"; }; =20 +&sdmmc1_b4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + + pins2 { + bootph-all; + }; +}; + &uart4 { pinctrl-names =3D "default", "sleep", "idle"; pinctrl-0 =3D <&uart4_pins_a>; pinctrl-1 =3D <&uart4_sleep_pins_a>; pinctrl-2 =3D <&uart4_idle_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; + +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + + pins2 { + bootph-all; + bias-pull-up; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts b= /arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts index f8e404346396..cc24a29fba15 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts @@ -92,6 +92,7 @@ bridge_out_panel: endpoint { }; =20 <dc { + bootph-some-ram; status =3D "okay"; =20 port { @@ -110,15 +111,40 @@ &sdmmc1 { pinctrl-2 =3D <&sdmmc1_b4_sleep_pins_a>; st,neg-edge; vmmc-supply =3D <&v3v3>; + bootph-all; status =3D "okay"; }; =20 +&sdmmc1_b4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + + pins2 { + bootph-all; + }; +}; + &uart4 { pinctrl-names =3D "default", "sleep", "idle"; pinctrl-0 =3D <&uart4_pins_a>; pinctrl-1 =3D <&uart4_sleep_pins_a>; pinctrl-2 =3D <&uart4_idle_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; + +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + + pins2 { + bootph-all; + bias-pull-up; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi b/arch/ar= m/boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi index 569a7e940ecc..db93934019d1 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi +++ b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi @@ -61,6 +61,7 @@ vddcore: regulator-vddcore { regulator-min-microvolt =3D <1200000>; regulator-max-microvolt =3D <1200000>; regulator-always-on; + bootph-all; }; =20 vdd: regulator-vdd { @@ -69,6 +70,7 @@ vdd: regulator-vdd { regulator-min-microvolt =3D <3300000>; regulator-max-microvolt =3D <3300000>; regulator-always-on; + bootph-all; }; =20 vdd_usb: regulator-vdd-usb { @@ -77,6 +79,7 @@ vdd_usb: regulator-vdd-usb { regulator-min-microvolt =3D <3300000>; regulator-max-microvolt =3D <3300000>; regulator-always-on; + bootph-all; }; =20 vdda: regulator-vdda { @@ -85,6 +88,7 @@ vdda: regulator-vdda { regulator-min-microvolt =3D <3300000>; regulator-max-microvolt =3D <3300000>; regulator-always-on; + bootph-all; }; =20 vdd_ddr: regulator-vdd-ddr { @@ -93,6 +97,7 @@ vdd_ddr: regulator-vdd-ddr { regulator-min-microvolt =3D <1350000>; regulator-max-microvolt =3D <1350000>; regulator-always-on; + bootph-all; }; =20 vtt_ddr: regulator-vtt-ddr { @@ -102,6 +107,7 @@ vtt_ddr: regulator-vtt-ddr { regulator-max-microvolt =3D <675000>; regulator-always-on; vin-supply =3D <&vdd>; + bootph-all; }; =20 vref_ddr: regulator-vref-ddr { @@ -111,6 +117,7 @@ vref_ddr: regulator-vref-ddr { regulator-max-microvolt =3D <675000>; regulator-always-on; vin-supply =3D <&vdd>; + bootph-all; }; =20 vdd_sd: regulator-vdd-sd { @@ -119,6 +126,7 @@ vdd_sd: regulator-vdd-sd { regulator-min-microvolt =3D <3300000>; regulator-max-microvolt =3D <3300000>; regulator-always-on; + bootph-all; }; =20 v3v3: regulator-v3v3 { @@ -127,6 +135,7 @@ v3v3: regulator-v3v3 { regulator-min-microvolt =3D <3300000>; regulator-max-microvolt =3D <3300000>; regulator-always-on; + bootph-all; }; =20 v2v8: regulator-v2v8 { @@ -136,6 +145,7 @@ v2v8: regulator-v2v8 { regulator-max-microvolt =3D <2800000>; regulator-always-on; vin-supply =3D <&v3v3>; + bootph-all; }; =20 v1v8: regulator-v1v8 { @@ -145,13 +155,86 @@ v1v8: regulator-v1v8 { regulator-max-microvolt =3D <1800000>; regulator-always-on; vin-supply =3D <&v3v3>; + bootph-all; }; }; =20 +&bsec { + bootph-all; +}; + +&clk_hse { + bootph-all; +}; + +&clk_hsi { + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_lsi { + bootph-all; +}; + +&clk_csi { + bootph-all; +}; + &dts { status =3D "okay"; }; =20 +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + &i2c2 { i2c-scl-falling-time-ns =3D <20>; i2c-scl-rising-time-ns =3D <185>; @@ -167,6 +250,7 @@ &ipcc { =20 &iwdg2 { timeout-sec =3D <32>; + bootph-all; status =3D "okay"; }; =20 @@ -180,6 +264,22 @@ &m4_rproc { status =3D "okay"; }; =20 +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&psci { + bootph-some-ram; +}; + +&rcc { + bootph-all; +}; + &rng1 { status =3D "okay"; }; diff --git a/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0= -of7.dts b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0-o= f7.dts index 5116a7785201..7bfd7da4a8db 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts @@ -78,6 +78,7 @@ &i2c2 { <dc { pinctrl-names =3D "default"; pinctrl-0 =3D <<dc_pins>; + bootph-some-ram; status =3D "okay"; =20 port { @@ -134,19 +135,45 @@ &sdmmc1 { pinctrl-2 =3D <&sdmmc1_b4_sleep_pins_a>; st,neg-edge; vmmc-supply =3D <&vdd>; + bootph-all; status =3D "okay"; }; =20 +&sdmmc1_b4_pins_a { + bootph-all; + + pins1 { + bootph-all; + }; + + pins2 { + bootph-all; + }; +}; + &uart4 { pinctrl-names =3D "default", "sleep", "idle"; pinctrl-0 =3D <&uart4_pins_a>; pinctrl-1 =3D <&uart4_sleep_pins_a>; pinctrl-2 =3D <&uart4_idle_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; =20 +&uart4_pins_a { + bootph-all; + + pins1 { + bootph-all; + }; + + pins2 { + bootph-all; + }; +}; + /* J31: RS323 */ &uart8 { pinctrl-names =3D "default"; diff --git a/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0= .dts b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0.dts index d949559be020..a1f79659d7c5 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0.dts @@ -36,19 +36,46 @@ &sdmmc1 { pinctrl-2 =3D <&sdmmc1_b4_sleep_pins_a>; st,neg-edge; vmmc-supply =3D <&vdd>; + bootph-all; status =3D "okay"; }; =20 +&sdmmc1_b4_pins_a { + bootph-all; + + pins1 { + bootph-all; + }; + + pins2 { + bootph-all; + }; +}; + &uart4 { pinctrl-names =3D "default", "sleep", "idle"; pinctrl-0 =3D <&uart4_pins_a>; pinctrl-1 =3D <&uart4_sleep_pins_a>; pinctrl-2 =3D <&uart4_idle_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; =20 +&uart4_pins_a { + bootph-all; + + pins1 { + bootph-all; + }; + + pins2 { + bootph-all; + bias-pull-up; + }; +}; + /* J31: RS323 */ &uart8 { pinctrl-names =3D "default"; diff --git a/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi b/arch= /arm/boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi index a75f50cf7123..4f6f4712d634 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi +++ b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi @@ -61,6 +61,7 @@ vin: regulator-vin { regulator-min-microvolt =3D <5000000>; regulator-max-microvolt =3D <5000000>; regulator-always-on; + bootph-all; }; =20 vddcore: regulator-vddcore { @@ -70,6 +71,7 @@ vddcore: regulator-vddcore { regulator-max-microvolt =3D <1200000>; regulator-always-on; vin-supply =3D <&vin>; + bootph-all; }; =20 vdd: regulator-vdd { @@ -79,6 +81,7 @@ vdd: regulator-vdd { regulator-max-microvolt =3D <3300000>; regulator-always-on; vin-supply =3D <&vin>; + bootph-all; }; =20 vddq_ddr: regulator-vddq-ddr { @@ -88,9 +91,34 @@ vddq_ddr: regulator-vddq-ddr { regulator-max-microvolt =3D <1350000>; regulator-always-on; vin-supply =3D <&vin>; + bootph-all; }; }; =20 +&bsec { + bootph-all; +}; + +&clk_hse { + bootph-all; +}; + +&clk_hsi { + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_lsi { + bootph-all; +}; + +&clk_csi { + bootph-all; +}; + &dts { status =3D "okay"; }; @@ -113,12 +141,61 @@ nand@0 { }; }; =20 +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + &ipcc { status =3D "okay"; }; =20 &iwdg2 { timeout-sec =3D <32>; + bootph-all; status =3D "okay"; }; =20 @@ -132,6 +209,26 @@ &m4_rproc { status =3D "okay"; }; =20 +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&psci { + bootph-some-ram; +}; + +&pwr_regulators { + bootph-all; +}; + +&rcc { + bootph-all; +}; + &rng1 { status =3D "okay"; }; diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts b/arch/arm/boot/= dts/st/stm32mp157c-dk2-scmi.dts index 43280289759d..e192d033626e 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts @@ -71,6 +71,7 @@ &m4_rproc { &optee { interrupt-parent =3D <&intc>; interrupts =3D ; + bootph-some-ram; }; =20 &rcc { @@ -91,3 +92,7 @@ &rng1 { &rtc { clocks =3D <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; }; + +&scmi { + bootph-some-ram; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts b/arch/arm/boot/dts/s= t/stm32mp157c-dk2.dts index 1ec3b8f2faa9..bf9fdf0d611c 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts @@ -80,6 +80,7 @@ touchscreen@38 { }; =20 <dc { + bootph-some-ram; status =3D "okay"; =20 port { diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/= dts/st/stm32mp157c-ed1-scmi.dts index 6f27d794d270..f053a70cb254 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts @@ -70,6 +70,7 @@ &m4_rproc { &optee { interrupt-parent =3D <&intc>; interrupts =3D ; + bootph-some-ram; }; =20 &rcc { @@ -90,3 +91,21 @@ &rng1 { &rtc { clocks =3D <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; }; + +&scmi { + bootph-some-ram; +}; + +&uart4 { + bootph-all; +}; + +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts b/arch/arm/boot/dts/s= t/stm32mp157c-ed1.dts index 49dd555cc228..ef71ebd65518 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts @@ -145,6 +145,31 @@ channel@6 { }; }; =20 + +&bsec { + bootph-all; +}; + +&clk_hse { + bootph-all; +}; + +&clk_hsi { + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_lsi { + bootph-all; +}; + +&clk_csi { + bootph-all; +}; + &crc1 { status =3D "okay"; }; @@ -170,6 +195,54 @@ &dts { status =3D "okay"; }; =20 +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + &hash1 { status =3D "okay"; }; @@ -181,7 +254,9 @@ &i2c4 { i2c-scl-rising-time-ns =3D <185>; i2c-scl-falling-time-ns =3D <20>; clock-frequency =3D <400000>; + bootph-all; status =3D "okay"; + /* spare dmas for other usage */ /delete-property/dmas; /delete-property/dma-names; @@ -192,6 +267,7 @@ pmic: stpmic@33 { interrupts-extended =3D <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells =3D <2>; + bootph-all; status =3D "okay"; =20 regulators { @@ -327,12 +403,20 @@ watchdog { }; }; =20 +&i2c4_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + &ipcc { status =3D "okay"; }; =20 &iwdg2 { timeout-sec =3D <32>; + bootph-all; status =3D "okay"; }; =20 @@ -348,9 +432,26 @@ &m4_rproc { status =3D "okay"; }; =20 +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&psci { + bootph-some-ram; +}; + &pwr_regulators { vdd-supply =3D <&vdd>; vdd_3v3_usbfs-supply =3D <&vdd_usb>; + bootph-all; +}; + +&rcc { + bootph-all; }; =20 &rng1 { @@ -378,9 +479,30 @@ &sdmmc1 { sd-uhs-sdr25; sd-uhs-sdr50; sd-uhs-ddr50; + bootph-pre-ram; status =3D "okay"; }; =20 +&sdmmc1_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&sdmmc1_dir_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + &sdmmc2 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; @@ -394,9 +516,27 @@ &sdmmc2 { vmmc-supply =3D <&v3v3>; vqmmc-supply =3D <&vdd>; mmc-ddr-3_3v; + bootph-pre-ram; status =3D "okay"; }; =20 +&sdmmc2_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&sdmmc2_d47_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + &timers6 { status =3D "okay"; /* spare dmas for other usage */ @@ -412,11 +552,22 @@ &uart4 { pinctrl-0 =3D <&uart4_pins_a>; pinctrl-1 =3D <&uart4_sleep_pins_a>; pinctrl-2 =3D <&uart4_idle_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; =20 +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_hs { vbus-supply =3D <&vbus_otg>; }; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/= dts/st/stm32mp157c-ev1-scmi.dts index 6ae391bffee5..17295d67ab85 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts @@ -75,6 +75,7 @@ &m4_rproc { &optee { interrupt-parent =3D <&intc>; interrupts =3D ; + bootph-some-ram; }; =20 &rcc { @@ -95,3 +96,7 @@ &rng1 { &rtc { clocks =3D <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; }; + +&scmi { + bootph-some-ram; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts b/arch/arm/boot/dts/s= t/stm32mp157c-ev1.dts index 4e46d58bf61f..47d08c1fb061 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts @@ -231,6 +231,7 @@ &i2c5 { }; =20 <dc { + bootph-some-ram; status =3D "okay"; =20 port { @@ -262,6 +263,7 @@ &qspi_bk2_sleep_pins_a reg =3D <0x58003000 0x1000>, <0x70000000 0x4000000>; #address-cells =3D <1>; #size-cells =3D <0>; + bootph-pre-ram; status =3D "okay"; =20 flash0: flash@0 { @@ -271,6 +273,7 @@ flash0: flash@0 { spi-max-frequency =3D <108000000>; #address-cells =3D <1>; #size-cells =3D <1>; + bootph-pre-ram; }; =20 flash1: flash@1 { @@ -283,6 +286,41 @@ flash1: flash@1 { }; }; =20 +&qspi_clk_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&qspi_bk1_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&qspi_cs1_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&qspi_bk2_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&qspi_cs2_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + &sdmmc3 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc3_b4_pins_a>; diff --git a/arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts b/arch/arm/boot/d= ts/st/stm32mp157c-lxa-mc1.dts index eada9cf257be..9f513045c559 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts @@ -158,6 +158,7 @@ <dc { pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <<dc_pins_c>; pinctrl-1 =3D <<dc_sleep_pins_c>; + bootph-some-ram; status =3D "okay"; =20 port { diff --git a/arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi b/arch/arm/b= oot/dts/st/stm32mp157c-odyssey-som.dtsi index cf7485251490..1c5517f57ecd 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi @@ -75,11 +75,84 @@ led-blue { }; }; =20 +&bsec { + bootph-all; +}; + +&clk_hse { + bootph-all; +}; + +&clk_hsi { + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_lsi { + bootph-all; +}; + +&clk_csi { + bootph-all; +}; + +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + &i2c2 { pinctrl-names =3D "default"; pinctrl-0 =3D <&i2c2_pins_a>; i2c-scl-rising-time-ns =3D <185>; i2c-scl-falling-time-ns =3D <20>; + bootph-all; status =3D "okay"; /* spare dmas for other usage */ /delete-property/dmas; @@ -91,6 +164,7 @@ pmic: stpmic@33 { interrupts-extended =3D <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells =3D <2>; + bootph-all; =20 regulators { compatible =3D "st,stpmic1-regulators"; @@ -218,12 +292,20 @@ watchdog { }; }; =20 +&i2c2_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + &ipcc { status =3D "okay"; }; =20 &iwdg2 { timeout-sec =3D <32>; + bootph-all; status =3D "okay"; }; =20 @@ -237,6 +319,26 @@ &m4_rproc { status =3D "okay"; }; =20 +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&psci { + bootph-some-ram; +}; + +&pwr_regulators { + bootph-all; +}; + +&rcc { + bootph-all; +}; + &rng1 { status =3D "okay"; }; @@ -258,6 +360,23 @@ &sdmmc2 { vmmc-supply =3D <&v3v3>; vqmmc-supply =3D <&vdd>; mmc-ddr-3_3v; + bootph-pre-ram; status =3D "okay"; }; =20 +&sdmmc2_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&sdmmc2_d47_pins_d { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-odyssey.dts b/arch/arm/boot/d= ts/st/stm32mp157c-odyssey.dts index a8b3f7a54703..92bc25b3f563 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-odyssey.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-odyssey.dts @@ -75,14 +75,35 @@ &sdmmc1 { st,neg-edge; bus-width =3D <4>; vmmc-supply =3D <&v3v3>; + bootph-pre-ram; status =3D "okay"; }; =20 +&sdmmc1_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + &uart4 { pinctrl-names =3D "default"; pinctrl-0 =3D <&uart4_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; =20 +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts b/arch/arm/b= oot/dts/st/stm32mp157c-osd32mp1-red.dts index 36e6055b5665..b404ea3752d9 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts @@ -131,6 +131,7 @@ i2s2_endpoint: endpoint { }; =20 <dc { + bootph-some-ram; status =3D "okay"; =20 port { diff --git a/arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi b/arch/arm/boot= /dts/st/stm32mp157f-dk2-scmi.dtsi index 89de85a2eff3..5d29c2154b46 100644 --- a/arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi +++ b/arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi @@ -87,6 +87,7 @@ &mdma1 { &optee { interrupt-parent =3D <&intc>; interrupts =3D ; + bootph-some-ram; }; =20 &pwr_regulators { @@ -114,6 +115,10 @@ &rtc { clocks =3D <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; }; =20 +&scmi { + bootph-some-ram; +}; + &scmi_reguls { scmi_vddcore: regulator@3 { reg =3D ; diff --git a/arch/arm/boot/dts/st/stm32mp157f-dk2.dts b/arch/arm/boot/dts/s= t/stm32mp157f-dk2.dts index 8fa61e54d026..4d857b3575fd 100644 --- a/arch/arm/boot/dts/st/stm32mp157f-dk2.dts +++ b/arch/arm/boot/dts/st/stm32mp157f-dk2.dts @@ -97,6 +97,7 @@ stpmic@33 { }; =20 <dc { + bootph-some-ram; status =3D "okay"; =20 port { diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/bo= ot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi index 5c77202ee196..2e02cd8e7e0d 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi @@ -201,6 +201,7 @@ <dc { pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <<dc_pins_b>; pinctrl-1 =3D <<dc_sleep_pins_b>; + bootph-some-ram; status =3D "okay"; =20 port { diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boo= t/dts/st/stm32mp15xx-dhcom-som.dtsi index 4cc633683c6b..2c40ceaf1f33 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi @@ -103,6 +103,10 @@ channel@1 { }; }; =20 +&bsec { + bootph-all; +}; + &crc1 { status =3D "okay"; }; @@ -121,6 +125,26 @@ dac2: dac@2 { }; }; =20 +&clk_hse { + bootph-all; +}; + +&clk_hsi { + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_lsi { + bootph-all; +}; + +&clk_csi { + bootph-all; +}; + &dts { status =3D "okay"; }; @@ -190,6 +214,7 @@ &gpioa { "", "", "DHCOM-K", "", "", "", "", "", "", "", "", ""; + bootph-all; }; =20 &gpiob { @@ -197,6 +222,7 @@ &gpiob { "", "", "", "", "DHCOM-Q", "", "", "", "", "", "", ""; + bootph-all; }; =20 &gpioc { @@ -204,6 +230,7 @@ &gpioc { "", "", "DHCOM-E", "", "", "", "", "", "", "", "", ""; + bootph-all; }; =20 &gpiod { @@ -211,6 +238,7 @@ &gpiod { "", "", "DHCOM-B", "", "", "", "", "DHCOM-F", "DHCOM-D", "", "", ""; + bootph-all; }; =20 &gpioe { @@ -218,6 +246,7 @@ &gpioe { "", "", "DHCOM-P", "", "", "", "", "", "", "", "", ""; + bootph-all; }; =20 &gpiof { @@ -225,6 +254,7 @@ &gpiof { "", "", "", "", "", "", "", "", "", "", "", ""; + bootph-all; }; =20 &gpiog { @@ -232,6 +262,7 @@ &gpiog { "", "", "", "", "DHCOM-L", "", "", "", "", "", "", ""; + bootph-all; }; =20 &gpioh { @@ -239,6 +270,7 @@ &gpioh { "", "", "", "DHCOM-N", "DHCOM-J", "DHCOM-W", "DHCOM-V", "DHCOM-U", "DHCOM-T", "", "DHCOM-S", ""; + bootph-all; }; =20 &gpioi { @@ -246,6 +278,20 @@ &gpioi { "DHCOM-R", "DHCOM-M", "", "", "", "", "", "", "", "", "", ""; + bootph-all; +}; + +&gpioj { + bootph-all; + +}; + +&gpiok { + bootph-all; +}; + +&gpioz { + bootph-all; }; =20 &i2c4 { @@ -253,6 +299,8 @@ &i2c4 { pinctrl-0 =3D <&i2c4_pins_a>; i2c-scl-rising-time-ns =3D <185>; i2c-scl-falling-time-ns =3D <20>; + bootph-all; + bootph-pre-ram; status =3D "okay"; /* spare dmas for other usage */ /delete-property/dmas; @@ -269,6 +317,8 @@ pmic: stpmic@33 { interrupts-extended =3D <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells =3D <2>; + bootph-all; + bootph-pre-ram; =20 regulators { compatible =3D "st,stpmic1-regulators"; @@ -279,6 +329,7 @@ regulators { ldo6-supply =3D <&v3v3>; pwr_sw1-supply =3D <&bst_out>; pwr_sw2-supply =3D <&bst_out>; + bootph-pre-ram; =20 vddcore: buck1 { regulator-name =3D "vddcore"; @@ -409,12 +460,20 @@ eeprom@50 { }; }; =20 +&i2c4_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + &ipcc { status =3D "okay"; }; =20 &iwdg2 { timeout-sec =3D <32>; + bootph-all; status =3D "okay"; }; =20 @@ -428,9 +487,22 @@ &m4_rproc { status =3D "okay"; }; =20 +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&psci { + bootph-some-ram; +}; + &pwr_regulators { vdd-supply =3D <&vdd>; vdd_3v3_usbfs-supply =3D <&vdd_usb>; + bootph-all; }; =20 &qspi { @@ -444,6 +516,7 @@ &qspi_bk1_sleep_pins_a reg =3D <0x58003000 0x1000>, <0x70000000 0x4000000>; #address-cells =3D <1>; #size-cells =3D <0>; + bootph-pre-ram; status =3D "okay"; =20 flash0: flash@0 { @@ -453,6 +526,28 @@ flash0: flash@0 { spi-max-frequency =3D <108000000>; #address-cells =3D <1>; #size-cells =3D <1>; + bootph-pre-ram; + }; +}; + +&qspi_clk_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&qspi_bk1_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&qspi_cs1_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; }; }; =20 @@ -469,6 +564,15 @@ &rcc { assigned-clocks =3D <&rcc CK_MCO2>, <&rcc PLL4_P>; assigned-clock-parents =3D <&rcc PLL4_P>; assigned-clock-rates =3D <50000000>, <100000000>; + bootph-all; +}; + +®11 { + bootph-pre-ram; +}; + +®18 { + bootph-pre-ram; }; =20 &rng1 { @@ -495,6 +599,7 @@ &sdmmc1 { st,ckin-gpios =3D <&gpioe 4 0>; bus-width =3D <4>; vmmc-supply =3D <&vdd_sd>; + bootph-pre-ram; status =3D "okay"; }; =20 @@ -504,11 +609,24 @@ &sdmmc1_b4_pins_a { * - optional on SoMs with SD voltage translator * - mandatory on SoMs without SD voltage translator */ + bootph-pre-ram; pins1 { bias-pull-up; + bootph-pre-ram; }; pins2 { bias-pull-up; + bootph-pre-ram; + }; +}; + +&sdmmc1_dir_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; }; }; =20 @@ -525,9 +643,24 @@ &sdmmc2 { vmmc-supply =3D <&v3v3>; vqmmc-supply =3D <&v3v3>; mmc-ddr-3_3v; + bootph-pre-ram; status =3D "okay"; }; =20 +&sdmmc2_b4_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&sdmmc2_d47_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + &sdmmc3 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc3_b4_pins_a>; @@ -545,7 +678,46 @@ &sdmmc3 { &uart4 { pinctrl-names =3D "default"; pinctrl-0 =3D <&uart4_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; + +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + +&usb33 { + bootph-pre-ram; +}; + +&usbotg_hs_pins_a { + bootph-pre-ram; +}; + +&usbotg_hs { + bootph-pre-ram; +}; + +&usbphyc { + bootph-pre-ram; +}; + +&usbphyc_port0 { + bootph-pre-ram; +}; + +&usbphyc_port1 { + bootph-pre-ram; +}; + +&vdd_usb { + bootph-pre-ram; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi b/arch/a= rm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi index aceeff6c38ba..e7e2203ab11a 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi @@ -355,6 +355,7 @@ <dc { pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <<dc_pins_d>; pinctrl-1 =3D <<dc_sleep_pins_d>; + bootph-some-ram; status =3D "okay"; =20 port { @@ -402,9 +403,30 @@ &sdmmc1 { bus-width =3D <4>; vmmc-supply =3D <&vdd_sd>; vqmmc-supply =3D <&sd_switch>; + bootph-pre-ram; status =3D "okay"; }; =20 +&sdmmc1_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&sdmmc1_dir_pins_b { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + &sdmmc2 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; @@ -418,9 +440,27 @@ &sdmmc2 { st,neg-edge; vmmc-supply =3D <&v3v3>; vqmmc-supply =3D <&vdd_io>; + bootph-pre-ram; status =3D "okay"; }; =20 +&sdmmc2_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&sdmmc2_d47_pins_c { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + &sdmmc3 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc3_b4_pins_b>; @@ -455,11 +495,22 @@ &uart4 { label =3D "LS-UART1"; pinctrl-names =3D "default"; pinctrl-0 =3D <&uart4_pins_b>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; =20 +&uart4_pins_b { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &uart7 { /* On Low speed expansion header */ label =3D "LS-UART0"; @@ -512,3 +563,7 @@ &usbphyc_port0 { &usbphyc_port1 { phy-supply =3D <&vdd_usb>; }; + +&vdd_io { + bootph-pre-ram; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi b/arch= /arm/boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi index bc4ddcbdd5cf..9c6a04b4c2e3 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi @@ -231,9 +231,30 @@ &sdmmc1 { /* MicroSD */ bus-width =3D <4>; vmmc-supply =3D <&vdd>; vqmmc-supply =3D <&vdd>; + bootph-pre-ram; status =3D "okay"; }; =20 +&sdmmc1_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&sdmmc1_dir_pins_b { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + &sdmmc2 { /* eMMC */ pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; @@ -246,9 +267,27 @@ &sdmmc2 { /* eMMC */ st,neg-edge; vmmc-supply =3D <&v3v3>; vqmmc-supply =3D <&vdd>; + bootph-pre-ram; status =3D "okay"; }; =20 +&sdmmc2_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&sdmmc2_d47_pins_c { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + &sdmmc3 { /* SDIO Wi-Fi */ pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc3_b4_pins_a>; @@ -276,11 +315,22 @@ &uart4 { label =3D "UART0"; pinctrl-names =3D "default"; pinctrl-0 =3D <&uart4_pins_d>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; =20 +&uart4_pins_d { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &uart5 { /* X11 UART */ label =3D "X11-UART5"; pinctrl-names =3D "default"; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boo= t/dts/st/stm32mp15xx-dhcor-som.dtsi index 89881a26c614..3d469e29d41a 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi @@ -63,6 +63,30 @@ retram: retram@38000000 { }; }; =20 +&bsec { + bootph-all; +}; + +&clk_hse { + bootph-all; +}; + +&clk_hsi { + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_lsi { + bootph-all; +}; + +&clk_csi { + bootph-all; +}; + &crc1 { status =3D "okay"; }; @@ -71,11 +95,61 @@ &dts { status =3D "okay"; }; =20 +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + &i2c4 { pinctrl-names =3D "default"; pinctrl-0 =3D <&i2c4_pins_a>; i2c-scl-rising-time-ns =3D <185>; i2c-scl-falling-time-ns =3D <20>; + bootph-all; + bootph-pre-ram; status =3D "okay"; /delete-property/dmas; /delete-property/dma-names; @@ -86,6 +160,8 @@ pmic: stpmic@33 { interrupts-extended =3D <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells =3D <2>; + bootph-all; + bootph-pre-ram; status =3D "okay"; =20 regulators { @@ -98,6 +174,7 @@ regulators { ldo6-supply =3D <&v3v3>; pwr_sw1-supply =3D <&bst_out>; pwr_sw2-supply =3D <&bst_out>; + bootph-pre-ram; =20 vddcore: buck1 { regulator-name =3D "vddcore"; @@ -215,12 +292,20 @@ watchdog { }; }; =20 +&i2c4_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + &ipcc { status =3D "okay"; }; =20 &iwdg2 { timeout-sec =3D <32>; + bootph-all; status =3D "okay"; }; =20 @@ -234,9 +319,23 @@ &m4_rproc { status =3D "okay"; }; =20 +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&psci { + bootph-some-ram; +}; + &pwr_regulators { vdd-supply =3D <&vdd>; vdd_3v3_usbfs-supply =3D <&vdd_usb>; + bootph-all; + bootph-pre-ram; }; =20 &qspi { @@ -250,6 +349,7 @@ &qspi_bk1_sleep_pins_a reg =3D <0x58003000 0x1000>, <0x70000000 0x200000>; #address-cells =3D <1>; #size-cells =3D <0>; + bootph-pre-ram; status =3D "okay"; =20 flash0: flash@0 { @@ -262,6 +362,35 @@ flash0: flash@0 { }; }; =20 +&qspi_clk_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&qspi_bk1_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&qspi_cs1_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +®11 { + bootph-pre-ram; +}; + +®18 { + bootph-pre-ram; +}; + &rng1 { status =3D "okay"; }; @@ -269,3 +398,31 @@ &rng1 { &rtc { status =3D "okay"; }; + +&usb33 { + bootph-pre-ram; +}; + +&usbotg_hs_pins_a { + bootph-pre-ram; +}; + +&usbotg_hs { + bootph-pre-ram; +}; + +&usbphyc { + bootph-pre-ram; +}; + +&usbphyc_port0 { + bootph-pre-ram; +}; + +&usbphyc_port1 { + bootph-pre-ram; +}; + +&vdd_usb { + bootph-pre-ram; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi b/arch/a= rm/boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi index 6e79c4b6fe32..3b5debd0ffc9 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi @@ -131,9 +131,30 @@ &sdmmc1 { bus-width =3D <4>; vmmc-supply =3D <&vdd_sd>; vqmmc-supply =3D <&sd_switch>; + bootph-pre-ram; status =3D "okay"; }; =20 +&sdmmc1_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&sdmmc1_dir_pins_b { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + &sdmmc2 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; @@ -147,17 +168,46 @@ &sdmmc2 { st,neg-edge; vmmc-supply =3D <&v3v3>; vqmmc-supply =3D <&v3v3>; + bootph-pre-ram; status =3D "okay"; }; =20 +&sdmmc2_b4_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&sdmmc2_d47_pins_c { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + &uart4 { pinctrl-names =3D "default"; pinctrl-0 =3D <&uart4_pins_b>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; =20 +&uart4_pins_b { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &uart7 { pinctrl-names =3D "default"; pinctrl-0 =3D <&uart7_pins_a>; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/= st/stm32mp15xx-dkx.dtsi index 7ed2b01958fe..036d37366f2a 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi @@ -144,6 +144,10 @@ channel@19 { }; }; =20 +&bsec { + bootph-all; +}; + &cec { pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&cec_pins_b>; @@ -151,6 +155,26 @@ &cec { status =3D "okay"; }; =20 +&clk_hse { + bootph-all; +}; + +&clk_hsi { + bootph-all; +}; + +&clk_lse { + bootph-all; +}; + +&clk_lsi { + bootph-all; +}; + +&clk_csi { + bootph-all; +}; + &crc1 { status =3D "okay"; }; @@ -159,6 +183,54 @@ &dts { status =3D "okay"; }; =20 +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + ðernet0 { status =3D "okay"; pinctrl-0 =3D <ðernet0_rgmii_pins_a>; @@ -264,6 +336,7 @@ &i2c4 { i2c-scl-rising-time-ns =3D <185>; i2c-scl-falling-time-ns =3D <20>; clock-frequency =3D <400000>; + bootph-all; status =3D "okay"; /* spare dmas for other usage */ /delete-property/dmas; @@ -299,6 +372,7 @@ pmic: stpmic@33 { interrupts-extended =3D <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells =3D <2>; + bootph-all; status =3D "okay"; =20 regulators { @@ -437,6 +511,13 @@ watchdog { }; }; =20 +&i2c4_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + &i2c5 { pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&i2c5_pins_a>; @@ -473,6 +554,7 @@ &ipcc { =20 &iwdg2 { timeout-sec =3D <32>; + bootph-all; status =3D "okay"; }; =20 @@ -480,6 +562,7 @@ <dc { pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <<dc_pins_a>; pinctrl-1 =3D <<dc_sleep_pins_a>; + bootph-some-ram; status =3D "okay"; =20 port { @@ -501,9 +584,26 @@ &m4_rproc { status =3D "okay"; }; =20 +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&psci { + bootph-some-ram; +}; + &pwr_regulators { vdd-supply =3D <&vdd>; vdd_3v3_usbfs-supply =3D <&vdd_usb>; + bootph-all; +}; + +&rcc { + bootph-all; }; =20 &rng1 { @@ -568,9 +668,20 @@ &sdmmc1 { st,neg-edge; bus-width =3D <4>; vmmc-supply =3D <&v3v3>; + bootph-pre-ram; status =3D "okay"; }; =20 +&sdmmc1_b4_pins_a { + bootph-pre-ram; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: +BxFQ0KklLuBJntYn61GoIJwVo0GZde0PVs8+oH8eD4FM5spf5grg3MYzuy8F6rVrnffBTIAK5EYNeaeCEPN3kCJqrN68vJUGEqN4SawTYr1hVrBzhJzKt4kqrqHOUa7UQsOPU8vd/vRpN5iKi0g8oqHSQ1esCEHFfDPYKbvXh+6knQxWC9xt8cvYrN0HGxa6BR8nAa9nPsLClpkR9dO1XXn6+E/B8nMzs6XyVkfxjZpz4taZNgo4V3Z9iqL0v13h1jOlliDeRUd3FnQ0/+pAI01S0pyT1fLvdmIkWMrTXOBwpAQ/cfnCiLIIvMEBvaSdjQKQq3BO7qkeLV90yMOVkW6MYjzn0u3aT09MyfNw5kAQBI8R0EUsFDMcZowNNIALQfc9EBPe/eCMK8G7eJTeRbOcofZT1N8A4aRr+gk9uSTzjmD3HYOu241WCI2VHpn X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2026 14:28:11.7790 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d1f2e7a4-3a2b-4c08-071b-08de633075c7 X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.59];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: AMS1EPF0000004A.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GVXPR10MB9663 The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard --- arch/arm64/boot/dts/st/stm32mp211.dtsi | 4 +- arch/arm64/boot/dts/st/stm32mp215f-dk.dts | 29 ++++++++ arch/arm64/boot/dts/st/stm32mp231.dtsi | 4 +- arch/arm64/boot/dts/st/stm32mp235f-dk.dts | 95 ++++++++++++++++++++++++++ arch/arm64/boot/dts/st/stm32mp251.dtsi | 4 +- arch/arm64/boot/dts/st/stm32mp255.dtsi | 2 +- arch/arm64/boot/dts/st/stm32mp257f-dk.dts | 103 +++++++++++++++++++++++++= +++ arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 105 +++++++++++++++++++++++++= ++++ 8 files changed, 339 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/st/stm32mp211.dtsi b/arch/arm64/boot/dts/s= t/stm32mp211.dtsi index cd078a16065e..7ddda11a6cc9 100644 --- a/arch/arm64/boot/dts/st/stm32mp211.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp211.dtsi @@ -47,7 +47,7 @@ ck_flexgen_51: clock-200000000 { }; =20 firmware { - optee { + optee: optee { compatible =3D "linaro,optee-tz"; method =3D "smc"; }; @@ -70,7 +70,7 @@ scmi_reset: protocol@16 { }; }; =20 - psci { + psci: psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; }; diff --git a/arch/arm64/boot/dts/st/stm32mp215f-dk.dts b/arch/arm64/boot/dt= s/st/stm32mp215f-dk.dts index 7bdaeaa5ab0f..6841433199eb 100644 --- a/arch/arm64/boot/dts/st/stm32mp215f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp215f-dk.dts @@ -44,6 +44,35 @@ &arm_wdt { status =3D "okay"; }; =20 +&optee { + bootph-all; +}; + +&psci { + bootph-all; +}; + +&rifsc { + bootph-all; +}; + +&scmi { + bootph-all; +}; + +&scmi_clk { + bootph-all; +}; + +&scmi_reset { + bootph-all; +}; + +&syscfg { + bootph-all; +}; + &usart2 { + bootph-all; status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/s= t/stm32mp231.dtsi index b5d81d1ee153..142a57006823 100644 --- a/arch/arm64/boot/dts/st/stm32mp231.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi @@ -59,7 +59,7 @@ optee: optee { interrupts =3D ; }; =20 - scmi { + scmi: scmi { compatible =3D "linaro,scmi-optee"; #address-cells =3D <1>; #size-cells =3D <0>; @@ -111,7 +111,7 @@ scmi_vdda18adc: regulator@7 { }; }; =20 - psci { + psci: psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 diff --git a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts b/arch/arm64/boot/dt= s/st/stm32mp235f-dk.dts index 5ecc5ef61590..2f6157957d13 100644 --- a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts @@ -95,6 +95,10 @@ &arm_wdt { status =3D "okay"; }; =20 +&bsec { + bootph-all; +}; + ðernet1 { pinctrl-0 =3D <ð1_rgmii_pins_b>; pinctrl-1 =3D <ð1_rgmii_sleep_pins_b>; @@ -117,6 +121,78 @@ phy1_eth1: ethernet-phy@1 { }; }; =20 +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + +&optee { + bootph-all; +}; + +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&psci { + bootph-all; +}; + +&rcc { + bootph-all; +}; + +&rifsc { + bootph-all; +}; + +&scmi { + bootph-all; +}; + +&scmi_clk { + bootph-all; +}; + &scmi_regu { scmi_vddio1: regulator@0 { regulator-min-microvolt =3D <1800000>; @@ -128,6 +204,10 @@ scmi_vdd_sdcard: regulator@23 { }; }; =20 +&scmi_reset { + bootph-all; +}; + &sdmmc1 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc1_b4_pins_a>; @@ -142,12 +222,27 @@ &sdmmc1 { status =3D "okay"; }; =20 +&syscfg { + bootph-all; +}; + &usart2 { pinctrl-names =3D "default", "idle", "sleep"; pinctrl-0 =3D <&usart2_pins_a>; pinctrl-1 =3D <&usart2_idle_pins_a>; pinctrl-2 =3D <&usart2_sleep_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; + +&usart2_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 8b925ed0d881..80ff8a43801e 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -68,7 +68,7 @@ optee: optee { interrupts =3D ; }; =20 - scmi { + scmi: scmi { compatible =3D "linaro,scmi-optee"; #address-cells =3D <1>; #size-cells =3D <0>; @@ -139,7 +139,7 @@ v2m0: v2m@48090000 { }; }; =20 - psci { + psci: psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; =20 diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/s= t/stm32mp255.dtsi index 7a598f53a2a0..3ba4e6166586 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -40,4 +40,4 @@ venc: venc@480e0000 { clocks =3D <&rcc CK_BUS_VENC>; access-controllers =3D <&rifsc 90>; }; -}; \ No newline at end of file +}; diff --git a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts b/arch/arm64/boot/dt= s/st/stm32mp257f-dk.dts index 4135e7c0d9a3..a6853d4aa45b 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts @@ -102,6 +102,10 @@ &arm_wdt { status =3D "okay"; }; =20 +&bsec { + bootph-all; +}; + ðernet1 { pinctrl-0 =3D <ð1_rgmii_pins_b>; pinctrl-1 =3D <ð1_rgmii_sleep_pins_b>; @@ -124,6 +128,86 @@ phy1_eth1: ethernet-phy@1 { }; }; =20 +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + +&optee { + bootph-all; +}; + +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&psci { + bootph-all; +}; + +&rcc { + bootph-all; +}; + +&rifsc { + bootph-all; +}; + +&scmi { + bootph-all; +}; + +&scmi_clk { + bootph-all; +}; + &scmi_regu { scmi_vddio1: regulator@0 { regulator-min-microvolt =3D <1800000>; @@ -135,6 +219,10 @@ scmi_vdd_sdcard: regulator@23 { }; }; =20 +&scmi_reset { + bootph-all; +}; + &sdmmc1 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc1_b4_pins_a>; @@ -149,12 +237,27 @@ &sdmmc1 { status =3D "okay"; }; =20 +&syscfg { + bootph-all; +}; + &usart2 { pinctrl-names =3D "default", "idle", "sleep"; pinctrl-0 =3D <&usart2_pins_a>; pinctrl-1 =3D <&usart2_idle_pins_a>; pinctrl-2 =3D <&usart2_sleep_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; + +&usart2_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/d= ts/st/stm32mp257f-ev1.dts index 852a73b0c516..cbf08d4304f3 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -167,6 +167,10 @@ &arm_wdt { status =3D "okay"; }; =20 +&bsec { + bootph-all; +}; + &combophy { clocks =3D <&rcc CK_BUS_USB3PCIEPHY>, <&rcc CK_KER_USB3PCIEPHY>, <&pad_cl= k>; clock-names =3D "apb", "ker", "pad"; @@ -253,6 +257,54 @@ phy0_eth2: ethernet-phy@1 { }; }; =20 +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + &i2c2 { pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&i2c2_pins_a>; @@ -338,6 +390,7 @@ timer { }; =20 <dc { + bootph-all; status =3D "okay"; port { ltdc_ep0_out: endpoint { @@ -347,6 +400,7 @@ ltdc_ep0_out: endpoint { }; =20 &lvds { + bootph-all; status =3D "okay"; ports { #address-cells =3D <1>; @@ -368,6 +422,10 @@ lvds_out0: endpoint { }; }; =20 +&optee { + bootph-all; +}; + &pcie_ep { pinctrl-names =3D "default", "init"; pinctrl-0 =3D <&pcie_pins_a>; @@ -389,10 +447,38 @@ pcie@0,0 { }; }; =20 +&pinctrl { + bootph-all; +}; + +&pinctrl_z { + bootph-all; +}; + +&psci { + bootph-all; +}; + +&rcc { + bootph-all; +}; + &rtc { status =3D "okay"; }; =20 +&rifsc { + bootph-all; +}; + +&scmi { + bootph-all; +}; + +&scmi_clk { + bootph-all; +}; + &scmi_regu { scmi_vddio1: regulator@0 { regulator-min-microvolt =3D <1800000>; @@ -424,6 +510,10 @@ scmi_vdd_sdcard: regulator@23 { }; }; =20 +&scmi_reset { + bootph-all; +}; + &sdmmc1 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc1_b4_pins_a>; @@ -438,6 +528,10 @@ &sdmmc1 { status =3D "okay"; }; =20 +&syscfg { + bootph-all; +}; + &spi3 { pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&spi3_pins_a>; @@ -515,11 +609,22 @@ &usart2 { pinctrl-0 =3D <&usart2_pins_a>; pinctrl-1 =3D <&usart2_idle_pins_a>; pinctrl-2 =3D <&usart2_sleep_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; =20 +&usart2_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usart6 { pinctrl-names =3D "default", "idle", "sleep"; pinctrl-0 =3D <&usart6_pins_a>; --=20 2.43.0