From nobody Tue Feb 10 00:58:53 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B10B1242D78; Tue, 3 Feb 2026 03:31:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770089471; cv=none; b=A1Dv4Wd1UNPHO25Wl+PD1c0uAP30nQJ6SAXWPNY4AesCIa/U0KdRYANTMiTg+ttHErXpWZxeTvlrWxPhkORV/5MO5jHBh9oJnLQL3MhuPkWSbNeqoghoT4ZteqQOXegtXx+xSlxJ9OCirj7KdxbsJTXksdvr9AqmKtOLuocNyu0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770089471; c=relaxed/simple; bh=nSo81XDH3g+0IhsQkmlg4apJPpZay88RgQZ5h1VpL2k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=R82cRzmkELChLGhdl7wPZ1m0JhwiPCActp0doiVADZsonA89/ang6Mgi0Und4seY3dBSoBLWLJ7BVykVg9y0ve/BkA7xrelUcVX41qSJAoSuP16yZLVM3zN6lVsU2afae+LnoV0a/RgY6pKi0k1qZ5BDbJ+2ks+0jcZP1bNai4c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 3 Feb 2026 11:31:04 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 3 Feb 2026 11:31:04 +0800 From: Jacky Chou Date: Tue, 3 Feb 2026 11:30:53 +0800 Subject: [PATCH RESEND v9 1/3] dt-bindings: phy: aspeed: Add ASPEED PCIe PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260203-upstream_pcie_rc-v9-1-899ee4efe94e@aspeedtech.com> References: <20260203-upstream_pcie_rc-v9-0-899ee4efe94e@aspeedtech.com> In-Reply-To: <20260203-upstream_pcie_rc-v9-0-899ee4efe94e@aspeedtech.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , "Andrew Jeffery" CC: , , , , , Jacky Chou X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770089464; l=1554; i=jacky_chou@aspeedtech.com; s=20251031; h=from:subject:message-id; bh=nSo81XDH3g+0IhsQkmlg4apJPpZay88RgQZ5h1VpL2k=; b=EpOlOH6dAdG3xn3L59ETFlwWx4735wKZK8l4QYz3heoFxGnMWb1RSAldXKGknJ+uDgu7HbTDu Q8Tzg7MVvj8AHBIEDbCPoJS6PawWjxmlWuZxWASlNijDD9vSYUgSFmJ X-Developer-Key: i=jacky_chou@aspeedtech.com; a=ed25519; pk=8XBx7KFM1drEsfCXTH9QC2lbMlGU4XwJTA6Jt9Mabdo= Introduce device-binding for ASPEED AST2600/2700 PCIe PHY. The PCIe PHY is used for PCIe RC to configure as RC mode. Signed-off-by: Jacky Chou Reviewed-by: Rob Herring (Arm) --- .../bindings/phy/aspeed,ast2600-pcie-phy.yaml | 42 ++++++++++++++++++= ++++ 1 file changed, 42 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/aspeed,ast2600-pcie-phy.= yaml b/Documentation/devicetree/bindings/phy/aspeed,ast2600-pcie-phy.yaml new file mode 100644 index 000000000000..71a5cd91fb3f --- /dev/null +++ b/Documentation/devicetree/bindings/phy/aspeed,ast2600-pcie-phy.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/aspeed,ast2600-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED PCIe PHY + +maintainers: + - Jacky Chou + +description: + The ASPEED PCIe PHY provides the physical layer functionality for PCIe + controllers in the SoC. + +properties: + compatible: + items: + - enum: + - aspeed,ast2600-pcie-phy + - aspeed,ast2700-pcie-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@1e6ed200 { + compatible =3D "aspeed,ast2600-pcie-phy"; + reg =3D <0x1e6ed200 0x100>; + #phy-cells =3D <0>; + }; --=20 2.34.1