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[61.220.246.151]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c642a336a1csm17535332a12.19.2026.02.03.01.50.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Feb 2026 01:50:42 -0800 (PST) From: Potin Lai Date: Tue, 03 Feb 2026 17:48:14 +0800 Subject: [PATCH v2 1/2] dt-bindings: arm: aspeed: add Meta SanMiguel BMC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260203-sanmiguel_init_dts-v2-1-6a5682c32b38@gmail.com> References: <20260203-sanmiguel_init_dts-v2-0-6a5682c32b38@gmail.com> In-Reply-To: <20260203-sanmiguel_init_dts-v2-0-6a5682c32b38@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Patrick Williams Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, Cosmo Chou , Mike Hsieh , Potin Lai , Roger Kan , Potin Lai X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770112237; l=841; i=potin.lai.pt@gmail.com; s=20240724; h=from:subject:message-id; bh=awDe2howAZDyvltIFZvQ9S1Z3NdAcsc3EqMeuy1puZc=; b=6Btw6wU97hhwe3vFKaiSmnwtqfWoR5H5FeSRtHNAThM6D2qJ/ppeb7Nl+1bqScZU3xQ3yYFxs zv5FMUtvvQvDlQMXkVYE35LS2ReTJrYjkluEoxdLbqAdirSmUJXIhQc X-Developer-Key: i=potin.lai.pt@gmail.com; a=ed25519; pk=6Z4H4V4fJwLteH/WzIXSsx6TkuY5FOcBBP+4OflJ5gM= Add Meta (Facebook) SanMiguel BMC board compatible. Signed-off-by: Potin Lai Acked-by: Conor Dooley --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Doc= umentation/devicetree/bindings/arm/aspeed/aspeed.yaml index 9298c1a75dd1..6c84e6c80978 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -91,6 +91,7 @@ properties: - facebook,greatlakes-bmc - facebook,harma-bmc - facebook,minerva-cmc + - facebook,sanmiguel-bmc - facebook,santabarbara-bmc - facebook,yosemite4-bmc - facebook,yosemite5-bmc --=20 2.31.1 From nobody Sat Feb 7 07:15:15 2026 Received: from mail-pg1-f172.google.com (mail-pg1-f172.google.com [209.85.215.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8870A39A808 for ; Tue, 3 Feb 2026 09:50:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770112248; cv=none; b=VrpSkbdYMzPB31AD5Z2NoXjBERpIXzIklB/61RiITMauJE4FeUrVXL6rdUUoY3woFTBSnjJPSlFLG1NGxcRfpa320WbIw1TEyevUY1kd9pOitwgwI9y4sBNomB/qVYBN3YKiIgksWytvZAyjwuRdJ0IFaPBoKtGaIhEy5jNagYo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770112248; c=relaxed/simple; bh=6CEMF0J24xTyya+kAavoNDL7Gxazys4V8KtyCAr6uQI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=S04NlPek9NDO3lxjlALvB0sSSKBV+YC0+7HWFYo8RGyGE95oyzxaYU+BagA1WCArplwLohU0rSkRHyMD87etIJ0oQFuDeS+EgYo0LmVPHvGwsYb2Xnt/ZLLE/frV1gKldCZh3D84JFIowrmi1FJkScFx2GoSUO5MfZ5gsRj467Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=jLqEO2vc; arc=none smtp.client-ip=209.85.215.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="jLqEO2vc" Received: by mail-pg1-f172.google.com with SMTP id 41be03b00d2f7-c626bd75628so2010276a12.3 for ; Tue, 03 Feb 2026 01:50:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770112246; x=1770717046; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=1Yh+3ZR5JSz7a16w/q3BwxHacvTB8f4NyfsXjqmmx1c=; b=jLqEO2vcp1G6cyHTdWQ5IclCjFqH2MkopdS8T+anANCi9nFYUFNJf31LejRmG3UYUN hUiWc8wRKALwfhuxWmxpsYZvoTYEal3yT+pU3f3nZGn9cYEarwd6mWWE+qZDydXngI8t YDCs7/S1tw9tPQKydKoyNZjJJxRbYLBerGpDKn9B/F+pMiZHeymE6BL13lx83AUhMKZ4 EyIl3F5Pu+aS2bWUdII/nxzAiFTJX4rh+ZkpTP4Q6aWYNv53WTi1uLRzZjWbKRlfOO9w OiasvK1CVNFhkRu4oAPbRNW5WiQ1225y+2sH836Zy/wTF3hzQSUi8z1CMdG8SNzi65f5 15FQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770112246; x=1770717046; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=1Yh+3ZR5JSz7a16w/q3BwxHacvTB8f4NyfsXjqmmx1c=; b=AxVM4XOqHIYiMvq+/VVPRNylxrH8Vcw5x2jyDty4/W6Xlkx+m60rHN7aZjt779Pn+S hPIxluV89T2aNoeLOElrGT7gLr/FTa+Immw/q4EB6FIGx+Q1gueh6gcNEBa2zNYwPw21 B53xZoGIpD1KxJAe4sUZSlwp1+BBmNRhFgQs0HIUH6qeGzlA82VJWAMJcg7CVFS4xyLs iZTacKPWxWWNYvDOuEXV5Kb07Q4o+j1rdxl30MSBRGkDBmwKadeRj11n22S4L2QVJGJE lGb6ooKp5wPYNq76/ug3OHEGAZEiD4lQp6fb7bvWQUMUeAYCC9wXbWQ5Kty3AWmjVfO/ 2ENA== X-Forwarded-Encrypted: i=1; AJvYcCWt+b9Olg3Ka9ICEIpULfoPu8NE2JIWkSxO8pJvBz0FhRbj+hCcPOc1lQeD3gBhOs/lfR1PSFcsoYmju6w=@vger.kernel.org X-Gm-Message-State: AOJu0Yzf83GVo3HEbok6eG3wmoogpqRd/qn5h4WdKJMQEJyq07ik0x0S AB2m8fAWja+6SmqUPA9B45VL62kmIDfQ4uHLuOLVGVxEoU5zTxmenxlj X-Gm-Gg: AZuq6aJiJQ3TKaOmuPYYMA+zvg6n6MgtYhFVbfDidkI13ZuAPduCOB+S7fxcRTPnz0H Z3LQhNxVuAH5Y/QrTUyQAU4QrXJILJiLiVlWn7QvwEqP8PqFMeLhZDh1AS4XRfScANkUVQAOxVW EkCuxIw0loXp5RpIkhj1BOgn/z2DETbd3AJ9nq+/seV6UunLscr7ldXPyb2rHxEDsHPuYazwzHg PAlCoVUlw+uJ+bTD/i2Wp5xUoChlxGqyOljoqvz0GSSNDzH7jjfJdMiuDtne7MX8v3jw9d3y5HY wnzE3WXW3MQLx9TBRPoHO1bQ+K0WUjfodVyIRkkbZ940xRQ6cZFe8W5hWnmq4ZPbygtK6fFGiYA JiLAKakcwR/E6bF6OGi28vAZZKpLEX6QMNnVSWWP66rq3bXpa10ddC1G1S+NzQLLyinbw1l2PCC eUcRpL/g5ZriDqZ6bWg4cVJv+7tZHVdsgM1az+j9z6in5SRxJ1IK4AWgs3zGd0xFw= X-Received: by 2002:a05:6a21:3286:b0:38c:4371:23f8 with SMTP id adf61e73a8af0-392e014f157mr14080449637.67.1770112245669; Tue, 03 Feb 2026 01:50:45 -0800 (PST) Received: from localhost.localdomain (61-220-246-151.hinet-ip.hinet.net. [61.220.246.151]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c642a336a1csm17535332a12.19.2026.02.03.01.50.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Feb 2026 01:50:45 -0800 (PST) From: Potin Lai Date: Tue, 03 Feb 2026 17:48:15 +0800 Subject: [PATCH v2 2/2] ARM: dts: aspeed: add Meta SanMiguel BMC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260203-sanmiguel_init_dts-v2-2-6a5682c32b38@gmail.com> References: <20260203-sanmiguel_init_dts-v2-0-6a5682c32b38@gmail.com> In-Reply-To: <20260203-sanmiguel_init_dts-v2-0-6a5682c32b38@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Patrick Williams Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, Cosmo Chou , Mike Hsieh , Potin Lai , Roger Kan , Potin Lai X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770112237; l=28554; i=potin.lai.pt@gmail.com; s=20240724; h=from:subject:message-id; bh=6CEMF0J24xTyya+kAavoNDL7Gxazys4V8KtyCAr6uQI=; b=nHZbskH5tZkpgAgxoB9YacFOnsyntV7cR+uf2xzP5lT9XPfvTitQVc5eHjAN/HipPCJRA4XCT JT8lxY0H6txDJ3pbMtdPGQKrAeU1xdq0AZXhZsHC2kHI3oZvEH29EeZ X-Developer-Key: i=potin.lai.pt@gmail.com; a=ed25519; pk=6Z4H4V4fJwLteH/WzIXSsx6TkuY5FOcBBP+4OflJ5gM= Add linux device tree entry for Meta (Facebook) SanMiguel compute-tray BMC using AT2620 SoC. Signed-off-by: Potin Lai --- arch/arm/boot/dts/aspeed/Makefile | 1 + .../dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts | 1161 ++++++++++++++++= ++++ 2 files changed, 1162 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/M= akefile index 9adf9278dc94..ab2effc29f6f 100644 --- a/arch/arm/boot/dts/aspeed/Makefile +++ b/arch/arm/boot/dts/aspeed/Makefile @@ -30,6 +30,7 @@ dtb-$(CONFIG_ARCH_ASPEED) +=3D \ aspeed-bmc-facebook-harma.dtb \ aspeed-bmc-facebook-minerva.dtb \ aspeed-bmc-facebook-minipack.dtb \ + aspeed-bmc-facebook-sanmiguel.dtb \ aspeed-bmc-facebook-santabarbara.dtb \ aspeed-bmc-facebook-tiogapass.dtb \ aspeed-bmc-facebook-wedge40.dtb \ diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts b/a= rch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts new file mode 100644 index 000000000000..39b2b79cfefe --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts @@ -0,0 +1,1161 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2025 Facebook Inc. + +/dts-v1/; +#include "aspeed-g6.dtsi" +#include +#include +#include +#include +#include +#include + +/ { + model =3D "AST2600 VR NVL144 BMC"; + compatible =3D "aspeed,ast2600"; + + aliases { + serial0 =3D &uart1; + serial1 =3D &uart2; + serial2 =3D &uart3; + serial3 =3D &uart4; + serial4 =3D &uart5; + i2c16 =3D &imux16; + i2c17 =3D &imux17; + i2c18 =3D &imux18; + i2c19 =3D &imux19; + i2c20 =3D &i2c20; + i2c21 =3D &i2c21; + }; + + chosen { + stdout-path =3D "serial4:57600n8"; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x80000000 0x80000000>; + }; + + iio-hwmon { + compatible =3D "iio-hwmon"; + io-channels =3D <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, + <&adc0 4>, <&adc0 5>, <&adc0 6>; + }; + + spi2_gpio: spi { + compatible =3D "spi-gpio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + sck-gpios =3D <&gpio0 ASPEED_GPIO(X, 3) GPIO_ACTIVE_HIGH>; + mosi-gpios =3D <&gpio0 ASPEED_GPIO(X, 4) GPIO_ACTIVE_HIGH>; + miso-gpios =3D <&gpio0 ASPEED_GPIO(X, 5) GPIO_ACTIVE_HIGH>; + cs-gpios =3D <&gpio0 ASPEED_GPIO(X, 2) GPIO_ACTIVE_LOW>; + num-chipselects =3D <1>; + + tpm@0 { + compatible =3D "infineon,slb9670", "tcg,tpm_tis-spi"; + spi-max-frequency =3D <33000000>; + reg =3D <0>; + }; + }; + + standby_power_regulator: standby-power-regulator { + status =3D "okay"; + compatible =3D "regulator-fixed"; + regulator-name =3D "standby_power"; + gpio =3D <&gpio0 ASPEED_GPIO(M, 3) GPIO_ACTIVE_HIGH>; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + scm-leds { + compatible =3D "gpio-leds"; + led-0 { + label =3D "bmc_heartbeat_amber"; + gpios =3D <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; + linux,default-trigger =3D "heartbeat"; + }; + }; + + fio-leds { + compatible =3D "gpio-leds"; + led-0 { + label =3D "power_blue"; + gpios =3D <&fio_ioexp 4 GPIO_ACTIVE_HIGH>; + }; + led-1 { + label =3D "power_amber"; + gpios =3D <&fio_ioexp 5 GPIO_ACTIVE_LOW>; + }; + led-2 { + label =3D "id_blue"; + gpios =3D <&fio_ioexp 6 GPIO_ACTIVE_HIGH>; + }; + led-3 { + label =3D "id_amber"; + gpios =3D <&fio_ioexp 7 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&fmc { + status =3D "okay"; + flash@0 { + status =3D "okay"; + m25p,fast-read; + label =3D "bmc"; + spi-max-frequency =3D <50000000>; +#include "openbmc-flash-layout-128.dtsi" + }; + flash@1 { + status =3D "okay"; + m25p,fast-read; + label =3D "alt-bmc"; + spi-max-frequency =3D <50000000>; + }; +}; + +&uart1 { + status =3D "okay"; +}; + +&uart3 { + status =3D "okay"; +}; + +&uart5 { + status =3D "okay"; +}; + +&uart_routing { + status =3D "okay"; +}; + +&mdio0 { + status =3D "okay"; + ethphy0: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0>; + }; +}; + +&mac0 { + status =3D "okay"; + pinctrl-names =3D "default"; + phy-mode =3D "rgmii-id"; + phy-handle =3D <ðphy0>; + pinctrl-0 =3D <&pinctrl_rgmii1_default>; +}; + +&ehci1 { + status =3D "okay"; + hub@1 { + reg =3D <1>; + hub@2 { + reg =3D <2>; + hub@1 { + reg =3D <1>; + device@1 { + reg =3D <1>; + cp2112a: interface@1 { + reg =3D <1 1>; + + gpio-controller; + interrupt-controller; + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + + i2c20: i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + }; + hub@3 { + reg =3D <3>; + cp2112c: device@2 { + reg =3D <2>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + + gpio-line-names =3D + "IOB0_MCP_P0_2-B", + "IOB0_MCU_RST_L-O", + "IOB0_MCU_RECOVERY_L-O", + "IOB0_GLOBAL_WP-O", + "IOB0_GLOBAL_ADDR_L_R-O", + "IOB0_GLOBAL_ADDR_U_D-O", + "IOB0_PWR_EN-O", + "IOB0_MCU_READY_STATUS-I"; + }; + }; + hub@4 { + reg =3D <4>; + cp2112d: device@2 { + reg =3D <2>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + + gpio-line-names =3D + "IOB1_MCP_P0_2-B", + "IOB1_MCU_RST_L-O", + "IOB1_MCU_RECOVERY_L-O", + "IOB1_GLOBAL_WP-O", + "IOB1_GLOBAL_ADDR_L_R-O", + "IOB1_GLOBAL_ADDR_U_D-O", + "IOB1_PWR_EN-O", + "IOB1_MCU_READY_STATUS-I"; + }; + }; + }; + hub@2 { + reg =3D <2>; + device@1 { + reg =3D <1>; + cp2112b: interface@1 { + reg =3D <1 1>; + + gpio-controller; + interrupt-controller; + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + + i2c21: i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + }; + hub@3 { + reg =3D <3>; + cp2112e: device@2 { + reg =3D <2>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + + gpio-line-names =3D + "IOB2_MCP_P0_2-B", + "IOB2_MCU_RST_L-O", + "IOB2_MCU_RECOVERY_L-O", + "IOB2_GLOBAL_WP-O", + "IOB2_GLOBAL_ADDR_L_R-O", + "IOB2_GLOBAL_ADDR_U_D-O", + "IOB2_PWR_EN-O", + "IOB2_MCU_READY_STATUS-I"; + }; + }; + hub@4 { + reg =3D <4>; + cp2112f: device@2 { + reg =3D <2>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + + gpio-line-names =3D + "IOB3_MCP_P0_2-B", + "IOB3_MCU_RST_L-O", + "IOB3_MCU_RECOVERY_L-O", + "IOB3_GLOBAL_WP-O", + "IOB3_GLOBAL_ADDR_L_R-O", + "IOB3_GLOBAL_ADDR_U_D-O", + "IOB3_PWR_EN-O", + "IOB3_MCU_READY_STATUS-I"; + }; + }; + }; + }; + }; +}; + +&adc0 { + aspeed,int-vref-microvolt =3D <2500000>; + status =3D "okay"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default>; +}; + +&wdt1 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_wdtrst1_default>; + aspeed,reset-type =3D "soc"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + aspeed,ext-pulse-duration =3D <256>; +}; + +&i2c0 { + status =3D "okay"; + aspeed,enable-byte; + + ssif-bmc@10 { + compatible =3D "ssif-bmc"; + reg =3D <0x10>; + alert-gpios =3D <&gpio1 ASPEED_GPIO(D, 7) GPIO_ACTIVE_LOW>; + timeout-ms =3D <5000>; + }; +}; + +&i2c1 { + status =3D "okay"; +}; + +&i2c2 { + status =3D "okay"; + + hpm0_ioexp_20: gpio@20 { + compatible =3D "nxp,pca9555"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gpio1>; + interrupts =3D ; + vcc-supply =3D <&standby_power_regulator>; + gpio-line-names =3D + "B0_M0_SHDN_FORCE_L-O", + "B0_M0_STBY_POWER_PG-I", + "B0_M0_THERM_OVERT_L-I", + "B0_M0_THERM_WARN_L-I", + "B0_M0_GLOBAL_WP-O", + "B0_M0_USB_HUB0_RST_L-O", + "B0_M0_PRE_SYS_RST_L-O", + "B0_M0_LEAK_DETECT_ALERT_L-I", + "B0_M0_RUN_POWER_EN-O", + "B0_M0_RUN_POWER_PG-I", + "B0_M0_CPU_CHIPTHROT_L-O", + "B0_M0_SHDN_REQ_L-O", + "B0_M0_CPU_SHDN_OK_L-I", + "B0_M0_CPLD_READY-I", + "B0_M0_PWR_BRAKE_L-O", + "B0_M0_PWR_BRAKE_STATUS_L-I"; + }; + + hpm0_ioexp_21: gpio@21 { + compatible =3D "nxp,pca9555"; + reg =3D <0x21>; + gpio-controller; + #gpio-cells =3D <2>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gpio1>; + interrupts =3D ; + vcc-supply =3D <&standby_power_regulator>; + + gpio-line-names =3D + "B0_M0_I2C_BUS_MUX_RESET_L-O", + "B0_M0_HPM_MCU_OK-I", + "B0_M0_AIC_USB_EN-O", + "B0_M0_C0_SOCAMM_DAC_SEL0-O", + "B0_M0_C1_SOCAMM_DAC_SEL1-O", + "B0_M0_C0_SOCAMM_I2C_SEL_R-O", + "B0_M0_C1_SOCAMM_I2C_SEL_R-O", + "B0_M0_EEPROM_POWER_DISABLE-O", + "B0_M0_L0L1_RST_L-I", + "B0_M0_L2_RST_L-I", + "B0_M0_BRD_ID_0-I", + "B0_M0_BRD_ID_1-I", + "B0_M0_BMC_LEAK_TEST_L-O", + "B0_M0_MCU_BMC_ALERT_L-I", + "B0_M0_CPU_BOOT_COMPLETE_3V3-I", + "B0_M0_BRD_ID_2-I"; + }; +}; + +&i2c3 { + status =3D "ok"; + + hmc_fru: eeprom@51 { + compatible =3D "atmel,24c02"; + reg =3D <0x51>; + }; + + hpm0_fru: eeprom@52 { + compatible =3D "atmel,24c02"; + reg =3D <0x52>; + }; + + hpm1_fru: eeprom@53 { + compatible =3D "atmel,24c02"; + reg =3D <0x53>; + }; +}; + +&i2c4 { + status =3D "okay"; +}; + +&i2c5 { + status =3D "okay"; + + smm_ioexp_20: gpio@20 { + compatible =3D "nxp,pca9555"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gpio1>; + interrupts =3D ; + gpio-line-names =3D + "HMC_RST_R_L-O", "HMC_RECOVERY_R-O", + "HMC_SPI_MUX_R_SEL-O", "GLOBAL_WP-O", + "HMC_READY-I", "HMC_PRSNT_R-I", + "BMC_SELF_PWR_CYCLE-O", "EEDO_LED2-O", + "PWR_LED_L-O", "PWR_BTN_L-I", + "UID_LED_L-O", "UID_BTN_L-I", + "FAULT_LED_L-O", "USB2_HUB_RST_L-O", + "IOX_GPIO_P16_TP", "WARN_LED_L-O"; + }; + + smm_ioexp_21: gpio@21 { + compatible =3D "nxp,pca9555"; + reg =3D <0x21>; + gpio-controller; + #gpio-cells =3D <2>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gpio1>; + interrupts =3D ; + gpio-line-names =3D + "BMC_HMC_MUX_SEL-O", "BMC_TPM_MUX_SEL-O", + "BMC_USB2_MUX_SEL-O", "HMC_PGOOD_3V3-I", + "BF3_AOC_NCSI_PRSNT_L-I", "HDR_SPI_PRSNT_L-I", + "SW_NRESET_R_L-O", "MUX_I2C_ESPI_SEL-O", + "I2C_BUS_MUX_RESET_L-O", "USB_MUX_EN-O", + "PDB_TRAY_RST-O", "USB_PWR_EN-O", + "RTC_CLR_L-O", "I2C_RTC_ALERT_L-I", + "I2C_PDB_ALERT_L-I", "BMC_MUX_PI3DP_SEL-O"; + }; + + smm_temp: temperature-sensor@4e { + compatible =3D "national,lm75"; + reg =3D <0x4e>; + }; + + smm_fru: eeprom@50 { + compatible =3D "atmel,24c02"; + reg =3D <0x50>; + }; + + rtc@6f { + compatible =3D "nuvoton,nct3018y"; + reg =3D <0x6f>; + }; +}; + +&i2c6 { + status =3D "okay"; + + hmc_ioexp: gpio@20 { + compatible =3D "ti,tca6408"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + + gpio-line-names =3D + "", "", "HMC_EROT_FATAL_ERROR_L-I", "", + "", "HMC_EROT_RECOVERY_L-O", "HMC_EROT_RESET_L-O", ""; + }; + + i2c-mux@70 { + compatible =3D "nxp,pca9546"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x70>; + i2c-mux-idle-disconnect; + + imux16: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + }; + + imux17: i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + }; + + imux18: i2c@2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <2>; + }; + + imux19: i2c@3 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <3>; + + rtc@6f { + compatible =3D "nuvoton,nct3018y"; + reg =3D <0x6f>; + }; + }; + }; +}; + +&i2c7 { + status =3D "okay"; + + hpm1_ioexp_20: gpio@20 { + compatible =3D "nxp,pca9555"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gpio1>; + interrupts =3D ; + vcc-supply =3D <&standby_power_regulator>; + gpio-line-names =3D + "B1_M0_SHDN_FORCE_L-O", + "B1_M0_STBY_POWER_PG-I", + "B1_M0_THERM_OVERT_L-I", + "B1_M0_THERM_WARN_L-I", + "B1_M0_GLOBAL_WP-O", + "B1_M0_USB_HUB0_RST_L-O", + "B1_M0_PRE_SYS_RST_L-O", + "B1_M0_LEAK_DETECT_ALERT_L-I", + "B1_M0_RUN_POWER_EN-O", + "B1_M0_RUN_POWER_PG-I", + "B1_M0_CPU_CHIPTHROT_L-O", + "B1_M0_SHDN_REQ_L-O", + "B1_M0_CPU_SHDN_OK_L-I", + "B1_M0_CPLD_READY-I", + "B1_M0_PWR_BRAKE_L-O", + "B1_M0_PWR_BRAKE_STATUS_L-I"; + }; + + hpm1_ioexp_21: gpio@21 { + compatible =3D "nxp,pca9555"; + reg =3D <0x21>; + gpio-controller; + #gpio-cells =3D <2>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gpio1>; + interrupts =3D ; + vcc-supply =3D <&standby_power_regulator>; + + gpio-line-names =3D + "B1_M0_I2C_BUS_MUX_RESET_L-O", + "B1_M0_HPM_MCU_OK-I", + "B1_M0_AIC_USB_EN-O", + "B1_M0_C0_SOCAMM_DAC_SEL0-O", + "B1_M0_C1_SOCAMM_DAC_SEL1-O", + "B1_M0_C0_SOCAMM_I2C_SEL_R-O", + "B1_M0_C1_SOCAMM_I2C_SEL_R-O", + "B1_M0_EEPROM_POWER_DISABLE-O", + "B1_M0_L0L1_RST_L-I", + "B1_M0_L2_RST_L-I", + "B1_M0_BRD_ID_0-I", + "B1_M0_BRD_ID_1-I", + "B1_M0_BMC_LEAK_TEST_L-O", + "B1_M0_MCU_BMC_ALERT_L-I", + "B1_M0_CPU_BOOT_COMPLETE_3V3-I", + "B1_M0_BRD_ID_2-I"; + }; +}; + +&i2c8 { + status =3D "okay"; +}; + +&i2c9 { + status =3D "okay"; + + pdb_mps_hsc1: power-monitor@10 { + compatible =3D "mps,mp5926"; + reg =3D <0x10>; + }; + + pdb_ti_hsc1: power-monitor@11 { + compatible =3D "ti,lm5066i"; + reg =3D <0x11>; + shunt-resistor-micro-ohms =3D <763>; + }; + + pdb_mps_hsc2: power-monitor@12 { + compatible =3D "mps,mp5926"; + reg =3D <0x12>; + }; + + pdb_ti_hsc2: power-monitor@13 { + compatible =3D "ti,lm5066i"; + reg =3D <0x13>; + shunt-resistor-micro-ohms =3D <294>; + }; + + pdb_mps_hsc3: power-monitor@14 { + compatible =3D "mps,mp5926"; + reg =3D <0x14>; + }; + + pdb_ti_hsc3: power-monitor@15 { + compatible =3D "ti,lm5066i"; + reg =3D <0x15>; + shunt-resistor-micro-ohms =3D <294>; + }; + + pdb_mps_hsc4: power-monitor@16 { + compatible =3D "mps,mp5926"; + reg =3D <0x16>; + }; + + pdb_ti_hsc4: power-monitor@17 { + compatible =3D "ti,lm5066i"; + reg =3D <0x17>; + shunt-resistor-micro-ohms =3D <381>; + }; + + pdb_temp: temperature-sensor@4e { + compatible =3D "national,lm75"; + reg =3D <0x4e>; + }; + + pdb_fru: eeprom@50 { + compatible =3D "atmel,24c02"; + reg =3D <0x50>; + }; + + pdb_ioexp_20: gpio@20 { + compatible =3D "nxp,pca9555"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gpio1>; + interrupts =3D ; + + gpio-line-names =3D + "PDB_STRAP-I", "STBY_POWER_EN-O", "STBY_PWR_OK-I", "", + "", "MAIN_PWR_EN-O", "MAIN_PWR_OK-I", "GLOBAL_WP-O", + "PDB_PWR_BRK_L-I", "FAN_PRSNT-I", "", "", + "", "", "", ""; + }; + + pdb_ioexp_75: gpio@75 { + compatible =3D "nxp,pca9555"; + reg =3D <0x75>; + gpio-controller; + #gpio-cells =3D <2>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gpio1>; + interrupts =3D ; + gpio-line-names =3D + "SNN_PDB_RUN_IO0_A_R_PG-I", "RST_STBY_R_L-O", + "SNN_PDB_RUN_IO0_B_R_EN-O", "PSU1_PRSNT_R_N-O", + "PSU2_PRSNT_R_N-O", "PSU3_PRSNT_R_N-O", + "PSU4_PRSNT_R_N-O", "PDB_12V_PG_R-I", + "PDB_12V_2_PG_R-I", "PDB_12V_2_EN_R-O", + "PDB_12V_EN_N_R-O", "", + "HSC_PG_VIN_PG_R-I", "PDB_PSU_SMB_ALERT_L_R-O", + "SNN_JSB2_17_R-I", "TRAY_RST_L_R-I"; + }; +}; + +&i2c10 { + status =3D "okay"; + + scm_temp: temperature-sensor@48 { + compatible =3D "national,lm75"; + reg =3D <0x48>; + }; + + scm_fru: eeprom@50 { + compatible =3D "atmel,24c128"; + reg =3D <0x50>; + }; +}; + +&i2c11 { + status =3D "ok"; + + sw_config: eeprom@50 { + compatible =3D "atmel,24c64"; + reg =3D <0x50>; + }; +}; + +&i2c12 { + status =3D "ok"; +}; + +&i2c13 { + status =3D "ok"; + mctp-controller; + multi-master; + + mctp@10 { + compatible =3D "mctp-i2c-controller"; + reg =3D <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + smm_ext_ioexp: gpio@38 { + compatible =3D "nxp,pca9554"; + reg =3D <0x38>; + gpio-controller; + #gpio-cells =3D <2>; + + gpio-line-names =3D + "SSD0_PRSNT_L-I", "E1S_PWR_EN-O", + "SSD0_PWRDIS-O", "I2C_PDB_ALERT_L-I", + "BMC_SSD0_RST_L-O", "GLOBAL_WP_E1S-O", + "12V_SSD0_PGD-I", "SSD0_LED-O"; + }; + + smm_ext_fru: eeprom@55 { + compatible =3D "atmel,24c02"; + reg =3D <0x55>; + }; +}; + +&i2c14 { + status =3D "okay"; + + fio_ioexp: gpio@20 { + compatible =3D "nxp,pca9555"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gpio1>; + interrupts =3D ; + gpio-line-names =3D + "", "", "", "", + "PWR_LED_BLUE", "PWR_LED_AMBER_R_N", + "BEEP_ID_LED_BLUE", "BEEP_ID_LED_AMBER_R_N", + "", "", "", "", + "FM_MAIN_PWREN_RMC_ISO_EN_N", "LEAK_DETECT_RMC_N", + "PWRGD_RMC_N", "SMALL_LEAK_RMC_N"; + + pwrgd-rmc-hog { + gpio-hog; + gpios =3D <14 GPIO_ACTIVE_LOW>; + output-low; + }; + }; + + fio_fru: eeprom@50 { + compatible =3D "atmel,24c64"; + reg =3D <0x50>; + }; +}; + +&i2c15 { + status =3D "okay"; +}; + +&gpio0 { + gpio-line-names =3D + /*A0-A7*/ "", "", "", "", "", "", "", "", + /*B0-B7*/ "", "", "", "", "", "", "", "", + /*C0-C7*/ "", "", "", "", "", "", "", "", + /*D0-D7*/ "", "", "", "", "", "FPGA_PEX_RST_L", "", "", + /*E0-E7*/ "RTL8221_PHY_RST_L-O", "RTL8211_PHY_INT_L-I", "", "", + "", "", "", "MUX_SGPIO_SEL-O", + /*F0-F7*/ "", "", "", "", "", "", "", "", + /*G0-G7*/ "", "", "", "", "", "", "", "", + /*H0-H7*/ "", "", "", "", "", "", "", "", + /*I0-I7*/ "", "", "", "", + "", "QSPI2_RST_L-O", + "GLOBAL_WP_BMC-I", "BMC_DDR4_TEN-O", + /*J0-J7*/ "", "", "", "", "", "", "", "", + /*K0-K7*/ "", "", "", "", "", "", "", "", + /*L0-L7*/ "", "", "", "", "", "", "", "", + /*M0-M7*/ "USB_HUB_RST_N-O", "BMC_FRU_WP-O", + "", "HMC_STBY_POWER_EN-O", + "STBY_POWER_PG-I", "PCIE_EP_RST_L-O", "", "", + /*N0-N7*/ "", "", "", "", "", "", "", "", + /*O0-O7*/ "", "", "", "", "", "", "", "", + /*P0-P7*/ "", "", "", "", "", "", "", "", + /*Q0-Q7*/ "", "", "", "", "", "", "", "", + /*R0-R7*/ "", "SP0_AP_INTR_N-I", "", "", "", "", "", "", + /*S0-S7*/ "", "", "", "", "", "", "", "", + /*T0-T7*/ "", "", "", "", "", "", "", "", + /*U0-U7*/ "", "", "", "", "", "", "", "", + /*V0-V7*/ "", "", "", "", "", "PCB_TEMP_ALERT-I", "", "", + /*W0-W7*/ "", "", "", "", "", "", "", "CPU_RST_L-I", + /*X0-X7*/ "", "", "", "", "", "", "", "", + /*Y0-Y7*/ "", "", "", "EMMC_RST-O", "", "", "", "", + /*Z0-Z7*/ "HMC_EROT_SPI_INT_L-I", "", "", "", "", "", "", ""; +}; + +&gpio1 { + /* 36 1.8V GPIOs */ + gpio-line-names =3D + /*A0-A7*/ "", "", "", "", "", "", "", "", + /*B0-B7*/ "", "", "", "", + "AP_EROT_REQ-O", "EROT_AP_GNT-I", + "IO_EXPANDER_INT_L-I", "", + /*C0-C7*/ "", "", "", "", "", "", "", "", + /*D0-D7*/ "", "", "", "", "", "", "", "I2C_SSIF_ALERT_L-I", + /*E0-E7*/ "", "", "", "", "", "", "", ""; +}; + +&i2c20 { + hpm0_sma_ioexp_50: gpio@50 { + compatible =3D "nxp,pca9555"; + reg =3D <0x50>; + gpio-controller; + #gpio-cells =3D <2>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&cp2112a>; + interrupts =3D <0 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names =3D + "CPU0_IROT_RECOVERY_L_3V3-I", + "CPU0_IROT_FATAL_ERR_L_3V3-I", + "CPU0_OVERT_L-I", + "C0_THERM_WARN_N-I", + "C0_SOC_THERM_OVERT_N-I", + "CPU0_CHIPTHROT_L-I", + "C0_SOCAMM_0_ID_PRSNT_N-I", + "C0_SOCAMM_1_ID_PRSNT_N-I", + "C0_SOCAMM_2_ID_PRSNT_N-I", + "C0_SOCAMM_3_ID_PRSNT_N-I", + "C0_SOCAMM_4_ID_PRSNT_N-I", + "C0_SOCAMM_5_ID_PRSNT_N-I", + "C0_SOCAMM_6_ID_PRSNT_N-I", + "C0_SOCAMM_7_ID_PRSNT_N-I", + "JTAG_BYPASS_CPU0_S_DIE-O", + "JTAG_BYPASS_CPU0_C_DIE-O"; + }; + hpm0_sma_ioexp_51: gpio@51 { + compatible =3D "nxp,pca9555"; + reg =3D <0x51>; + gpio-controller; + #gpio-cells =3D <2>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&cp2112a>; + interrupts =3D <1 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names =3D + "C0_UPHY0_PRSNT0_L-I", + "C0_UPHY0_PRSNT2_L-I", + "C0_UPHY_PRSNT1_L-I", + "C0_UPHY2_PRSNT0_L-I", + "C0_UPHY2_PRSNT2_L-I", + "C0_UPHY3_PRSNT0_L-I", + "C0_UPHY3_PRSNT1_L-I", + "GPU_THERM_WARN_N-I", + "JTAG_BYPASS_GPU1-O", + "JTAG_BYPASS_GPU2-O", + "C0_ALL_SOCAMM_PGOOD-I", + "DDR_VDDQ_PGOOD-I", + "CPU0_OOB_CS1_L-O", + "CPU0_OOB_CS0_L-O", + "LEAK_SELF_TEST_L-I", + "TRAY_FAST_SHDN_L-I"; + }; + hpm0_sma_ioexp_52: gpio@52 { + compatible =3D "nxp,pca9555"; + reg =3D <0x52>; + gpio-controller; + #gpio-cells =3D <2>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&cp2112a>; + interrupts =3D <2 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names =3D + "C0_WAKE_L-I", + "MCU_THERM_OVERT_N-I", + "MCU_THERM_WARN_N-I", + "PRIMARY_NODE_L-I", + "GLOBAL_WP-I", + "PCIE_CLKBUF_LOS-I", + "LEAK_DETECT_L-I", + "vLeakDetect1Status0-I", + "vLeakDetect1Status1-I", + "vLeakDetect2Status0-I", + "vLeakDetect2Status1-I", + "BMC_IOX_INT_L-I", + "MCU_BMC_ALERT_L-I", + "MCU_HMC_ALERT_L-I", + "MCU_USER_STRAP-I", + "HPM_MCU_OK-I"; + }; + hpm0_sma_ioexp_53: gpio@53 { + compatible =3D "nxp,pca9555"; + reg =3D <0x53>; + gpio-controller; + #gpio-cells =3D <2>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&cp2112a>; + interrupts =3D <3 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names =3D + "CPLD_RESET_L-I", + "CPLD_PSEQ_FAULT-I", + "CPLD_READY-I", + "CPLD_PROGRAM-I", + "MCU_12V_HSCC_PGOOD-I", + "RUN_PWR_EN-I", + "MODULE_PWR_GOOD-I", + "VDD_1V8_PGOOD-I", + "VDD_3V3_PGOOD-I", + "C0_CVDD_PGOOD-I", + "C0_5V_SOCAMM_PGOOD-I", + "OOB_MUX_CTRL1-O", + "OOB_MUX_CTRL0-O", + "C2CVDD_PGOOD-I", + "SLOT_PWR_BRAKE_EN_L-I", + "MCU_I2C_RTC_ALERT_L-I"; + }; + hpm0_sma_ioexp_54: gpio@54 { + compatible =3D "nxp,pca9555"; + reg =3D <0x54>; + gpio-controller; + #gpio-cells =3D <2>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&cp2112a>; + interrupts =3D <4 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names =3D + "JTAG_SEL_MCU-O", + "JTAG_TCK_MCU-O", + "JTAG_TMS_MCU-O", + "JTAG_TDO_MCU-I", + "JTAG_TDI_MCU-O", + "JTAG_TRST_L_MCU-O", + "CPU0_SSIF_ALERT_L_3V3-O", + "USB_HMC_TO_CPU_FORCE_EN-O", + "MCU_RECOVERY_L-I", + "v_BUS_BAR_OVERT-I", + "v_CPLD_AUTH_FAIL-I", + "", + "", + "", + "", + ""; + }; +}; + +&i2c21 { + hpm1_sma_ioexp_50: gpio@50 { + compatible =3D "nxp,pca9555"; + reg =3D <0x50>; + gpio-controller; + #gpio-cells =3D <2>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&cp2112b>; + interrupts =3D <0 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names =3D + "SEC_CPU0_IROT_RECOVERY_L_3V3-I", + "SEC_CPU0_IROT_FATAL_ERR_L_3V3-I", + "SEC_CPU0_OVERT_L-I", + "SEC_C0_THERM_WARN_N-I", + "SEC_C0_SOC_THERM_OVERT_N-I", + "SEC_CPU0_CHIPTHROT_L-I", + "SEC_C0_SOCAMM_0_ID_PRSNT_N-I", + "SEC_C0_SOCAMM_1_ID_PRSNT_N-I", + "SEC_C0_SOCAMM_2_ID_PRSNT_N-I", + "SEC_C0_SOCAMM_3_ID_PRSNT_N-I", + "SEC_C0_SOCAMM_4_ID_PRSNT_N-I", + "SEC_C0_SOCAMM_5_ID_PRSNT_N-I", + "SEC_C0_SOCAMM_6_ID_PRSNT_N-I", + "SEC_C0_SOCAMM_7_ID_PRSNT_N-I", + "SEC_JTAG_BYPASS_CPU0_S_DIE-O", + "SEC_JTAG_BYPASS_CPU0_C_DIE-O"; + }; + hpm1_sma_ioexp_51: gpio@51 { + compatible =3D "nxp,pca9555"; + reg =3D <0x51>; + gpio-controller; + #gpio-cells =3D <2>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&cp2112b>; + interrupts =3D <1 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names =3D + "SEC_C0_UPHY0_PRSNT0_L-I", + "SEC_C0_UPHY0_PRSNT2_L-I", + "SEC_C0_UPHY_PRSNT1_L-I", + "SEC_C0_UPHY2_PRSNT0_L-I", + "SEC_C0_UPHY2_PRSNT2_L-I", + "SEC_C0_UPHY3_PRSNT0_L-I", + "SEC_C0_UPHY3_PRSNT1_L-I", + "SEC_GPU_THERM_WARN_N-I", + "SEC_JTAG_BYPASS_GPU1-O", + "SEC_JTAG_BYPASS_GPU2-O", + "SEC_C0_ALL_SOCAMM_PGOOD-I", + "SEC_DDR_VDDQ_PGOOD-I", + "SEC_CPU0_OOB_CS1_L-O", + "SEC_CPU0_OOB_CS0_L-O", + "SEC_LEAK_SELF_TEST_L-I", + "SEC_TRAY_FAST_SHDN_L-I"; + }; + hpm1_sma_ioexp_52: gpio@52 { + compatible =3D "nxp,pca9555"; + reg =3D <0x52>; + gpio-controller; + #gpio-cells =3D <2>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&cp2112b>; + interrupts =3D <2 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names =3D + "SEC_C0_WAKE_L-I", + "SEC_MCU_THERM_OVERT_N-I", + "SEC_MCU_THERM_WARN_N-I", + "SEC_PRIMARY_NODE_L-I", + "SEC_GLOBAL_WP-I", + "SEC_PCIE_CLKBUF_LOS-I", + "SEC_LEAK_DETECT_L-I", + "SEC_vLeakDetect1Status0-I", + "SEC_vLeakDetect1Status1-I", + "SEC_vLeakDetect2Status0-I", + "SEC_vLeakDetect2Status1-I", + "SEC_BMC_IOX_INT_L-I", + "SEC_MCU_BMC_ALERT_L-I", + "SEC_MCU_HMC_ALERT_L-I", + "SEC_MCU_USER_STRAP-I", + "SEC_HPM_MCU_OK-I"; + }; + hpm1_sma_ioexp_53: gpio@53 { + compatible =3D "nxp,pca9555"; + reg =3D <0x53>; + gpio-controller; + #gpio-cells =3D <2>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&cp2112b>; + interrupts =3D <3 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names =3D + "SEC_CPLD_RESET_L-I", + "SEC_CPLD_PSEQ_FAULT-I", + "SEC_CPLD_READY-I", + "SEC_CPLD_PROGRAM-I", + "SEC_MCU_12V_HSCC_PGOOD-I", + "SEC_RUN_PWR_EN-I", + "SEC_MODULE_PWR_GOOD-I", + "SEC_VDD_1V8_PGOOD-I", + "SEC_VDD_3V3_PGOOD-I", + "SEC_C0_CVDD_PGOOD-I", + "SEC_C0_5V_SOCAMM_PGOOD-I", + "SEC_OOB_MUX_CTRL1-O", + "SEC_OOB_MUX_CTRL0-O", + "SEC_C2CVDD_PGOOD-I", + "SEC_SLOT_PWR_BRAKE_EN_L-I", + "SEC_MCU_I2C_RTC_ALERT_L-I"; + }; + hpm1_sma_ioexp_54: gpio@54 { + compatible =3D "nxp,pca9555"; + reg =3D <0x54>; + gpio-controller; + #gpio-cells =3D <2>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&cp2112b>; + interrupts =3D <4 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names =3D + "SEC_JTAG_SEL_MCU-O", + "SEC_JTAG_TCK_MCU-O", + "SEC_JTAG_TMS_MCU-O", + "SEC_JTAG_TDO_MCU-I", + "SEC_JTAG_TDI_MCU-O", + "SEC_JTAG_TRST_L_MCU-O", + "SEC_CPU0_SSIF_ALERT_L_3V3-O", + "SEC_USB_HMC_TO_CPU_FORCE_EN-O", + "SEC_MCU_RECOVERY_L-I", + "SEC_v_BUS_BAR_OVERT-I", + "SEC_v_CPLD_AUTH_FAIL-I", + "", + "", + "", + "", + ""; + }; +}; --=20 2.31.1