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Mon, 2 Feb 2026 10:19:52 +0000 (GMT) From: Raghav Sharma To: krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, conor+dt@kernel.org, sunyeal.hong@samsung.com, shin.son@samsung.com Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, chandan.vn@samsung.com, dev.tailor@samsung.com, karthik.sun@samsung.com, Raghav Sharma Subject: [PATCH 1/3] dt-bindings: clock: exynosautov920: add G3D clock definitions Date: Mon, 2 Feb 2026 16:05:53 +0530 Message-Id: <20260202103555.2089376-2-raghav.s@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260202103555.2089376-1-raghav.s@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20260202101954epcas5p27735b03488efceba5d7f970931905ec5 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P cpgsPolicy: CPGSC10-543,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20260202101954epcas5p27735b03488efceba5d7f970931905ec5 References: <20260202103555.2089376-1-raghav.s@samsung.com> Add device tree clock binding definitions for CMU_G3D Signed-off-by: Raghav Sharma --- .../clock/samsung,exynosautov920-clock.yaml | 21 +++++++++++++++++++ .../clock/samsung,exynosautov920.h | 6 ++++++ 2 files changed, 27 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/samsung,exynosautov920= -clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynosautov92= 0-clock.yaml index 1318720193b3..6b1fc61a2ff9 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.= yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.= yaml @@ -35,6 +35,7 @@ properties: - samsung,exynosautov920-cmu-cpucl0 - samsung,exynosautov920-cmu-cpucl1 - samsung,exynosautov920-cmu-cpucl2 + - samsung,exynosautov920-cmu-g3d - samsung,exynosautov920-cmu-hsi0 - samsung,exynosautov920-cmu-hsi1 - samsung,exynosautov920-cmu-hsi2 @@ -287,6 +288,26 @@ allOf: - const: oscclk - const: noc =20 + - if: + properties: + compatible: + contains: + const: samsung,exynosautov920-cmu-g3d + + then: + properties: + clocks: + items: + - description: External reference clock (38.4 MHz) + - description: CMU_G3D SWITCH clock (from CMU_TOP) + - description: CMU_G3D NOCP clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: switch + - const: nocp + required: - compatible - "#clock-cells" diff --git a/include/dt-bindings/clock/samsung,exynosautov920.h b/include/d= t-bindings/clock/samsung,exynosautov920.h index 06dec27a8c77..f2628c220b22 100644 --- a/include/dt-bindings/clock/samsung,exynosautov920.h +++ b/include/dt-bindings/clock/samsung,exynosautov920.h @@ -309,4 +309,10 @@ #define CLK_MOUT_MFD_NOC_USER 1 #define CLK_DOUT_MFD_NOCP 2 =20 +/* CMU_G3D */ +#define FOUT_PLL_G3D 1 +#define CLK_MOUT_G3D_NOC 2 +#define CLK_MOUT_G3D_SWITCH_USER 3 +#define CLK_MOUT_G3D_NOCP_USER 4 + #endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H */ --=20 2.34.1 From nobody Sun Feb 8 10:03:44 2026 Received: from mailout3.samsung.com (mailout3.samsung.com [203.254.224.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A26C73596E8 for ; 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Mon, 2 Feb 2026 10:19:59 +0000 (GMT) Received: from epcas5p1.samsung.com (unknown [182.195.38.95]) by epsnrtp01.localdomain (Postfix) with ESMTP id 4f4N0G5Sbfz6B9m6; Mon, 2 Feb 2026 10:19:58 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p2.samsung.com (KnoxPortal) with ESMTPA id 20260202101957epcas5p224b18e84c561e542c39096b2bd7f29a7~QZrjdPMz70827008270epcas5p2B; Mon, 2 Feb 2026 10:19:57 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20260202101955epsmtip19544b13693357c191df1fa79e02a89a4~QZrg-_XPW1761017610epsmtip1Y; Mon, 2 Feb 2026 10:19:54 +0000 (GMT) From: Raghav Sharma To: krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, conor+dt@kernel.org, sunyeal.hong@samsung.com, shin.son@samsung.com Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, chandan.vn@samsung.com, dev.tailor@samsung.com, karthik.sun@samsung.com, Raghav Sharma Subject: [PATCH 2/3] clk: samsung: exynosautov920: add block G3D clock support Date: Mon, 2 Feb 2026 16:05:54 +0530 Message-Id: <20260202103555.2089376-3-raghav.s@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260202103555.2089376-1-raghav.s@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20260202101957epcas5p224b18e84c561e542c39096b2bd7f29a7 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P cpgsPolicy: CPGSC10-543,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20260202101957epcas5p224b18e84c561e542c39096b2bd7f29a7 References: <20260202103555.2089376-1-raghav.s@samsung.com> Add support for CMU_G3D which provides clocks to G3D block, and register the required compatible and cmu_info for the same. Signed-off-by: Raghav Sharma --- drivers/clk/samsung/clk-exynosautov920.c | 52 ++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/drivers/clk/samsung/clk-exynosautov920.c b/drivers/clk/samsung= /clk-exynosautov920.c index d0617c7fff3a..c38b103721f0 100644 --- a/drivers/clk/samsung/clk-exynosautov920.c +++ b/drivers/clk/samsung/clk-exynosautov920.c @@ -30,6 +30,7 @@ #define CLKS_NR_M2M (CLK_DOUT_M2M_NOCP + 1) #define CLKS_NR_MFC (CLK_DOUT_MFC_NOCP + 1) #define CLKS_NR_MFD (CLK_DOUT_MFD_NOCP + 1) +#define CLKS_NR_G3D (CLK_MOUT_G3D_NOCP_USER + 1) =20 /* ---- CMU_TOP ----------------------------------------------------------= -- */ =20 @@ -1942,6 +1943,54 @@ static const struct samsung_cmu_info mfd_cmu_info __= initconst =3D { .clk_name =3D "noc", }; =20 +/* ---- CMU_G3D --------------------------------------------------------- = */ + +/* Register Offset definitions for CMU_G3D (0x1a000000) */ +#define PLL_LOCKTIME_PLL_G3D 0x0 +#define PLL_CON3_PLL_G3D 0x10c +#define CLK_CON_MUX_MUX_CLK_G3D_NOC 0x1000 +#define PLL_CON0_MUX_CLKCMU_G3D_NOCP_USER 0x600 +#define PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER 0x610 + +static const unsigned long g3d_clk_regs[] __initconst =3D { + PLL_LOCKTIME_PLL_G3D, + PLL_CON3_PLL_G3D, + CLK_CON_MUX_MUX_CLK_G3D_NOC, + PLL_CON0_MUX_CLKCMU_G3D_NOCP_USER, + PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, +}; + +static const struct samsung_pll_clock g3d_pll_clks[] __initconst =3D { + /* CMU_G3D_PLL */ + PLL(pll_531x, FOUT_PLL_G3D, "fout_pll_g3d", "oscclk", + PLL_LOCKTIME_PLL_G3D, PLL_CON3_PLL_G3D, NULL), +}; + +/* List of parent clocks for Muxes in CMU_G3D */ +PNAME(mout_clk_g3d_noc_p) =3D { "oscclk", "fout_pll_g3d", "mout_clkcmu_g3d= _switch_user"}; +PNAME(mout_clkcmu_g3d_switch_user_p) =3D { "oscclk", "dout_clkcmu_g3d_swit= ch" }; +PNAME(mout_clkcmu_g3d_nocp_user_p) =3D { "oscclk", "dout_clkcmu_g3d_nocp" = }; + +static const struct samsung_mux_clock g3d_mux_clks[] __initconst =3D { + MUX(CLK_MOUT_G3D_NOC, "mout_clk_g3d_noc", + mout_clk_g3d_noc_p, CLK_CON_MUX_MUX_CLK_G3D_NOC, 0, 2), + MUX(CLK_MOUT_G3D_SWITCH_USER, "mout_clkcmu_g3d_switch_user", + mout_clkcmu_g3d_switch_user_p, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, 4= , 1), + MUX(CLK_MOUT_G3D_NOCP_USER, "mout_clkcmu_g3d_nocp_user", + mout_clkcmu_g3d_nocp_user_p, PLL_CON0_MUX_CLKCMU_G3D_NOCP_USER, 4, 1), +}; + +static const struct samsung_cmu_info g3d_cmu_info __initconst =3D { + .pll_clks =3D g3d_pll_clks, + .nr_pll_clks =3D ARRAY_SIZE(g3d_pll_clks), + .mux_clks =3D g3d_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(g3d_mux_clks), + .nr_clk_ids =3D CLKS_NR_G3D, + .clk_regs =3D g3d_clk_regs, + .nr_clk_regs =3D ARRAY_SIZE(g3d_clk_regs), + .clk_name =3D "noc", +}; + static int __init exynosautov920_cmu_probe(struct platform_device *pdev) { const struct samsung_cmu_info *info; @@ -1981,6 +2030,9 @@ static const struct of_device_id exynosautov920_cmu_o= f_match[] =3D { }, { .compatible =3D "samsung,exynosautov920-cmu-mfd", .data =3D &mfd_cmu_info, + }, { + .compatible =3D "samsung,exynosautov920-cmu-g3d", + .data =3D &g3d_cmu_info, }, { } }; --=20 2.34.1 From nobody Sun Feb 8 10:03:44 2026 Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C78F5357A25 for ; Mon, 2 Feb 2026 10:20:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.34 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770027608; cv=none; b=j2YtrW1EFxCr8hJfHmEf4d5ur3dc1thrv0Dx7prmMpoFuPBUO7POS4+MM5F8KJGbtkCZd21Wo30XcQ8kCsyUj2XUPajenzkDeTbbkx5rBAYnE7JCID8qgKcI4p/+9vyCH9WEgZaisQFLR5Ktls6lZM0h+JSgoVzl+SVVYAmvQzc= ARC-Message-Signature: i=1; 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Mon, 2 Feb 2026 10:20:01 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20260202101957epsmtip1e09470b86119a79abd6a8782573d0112~QZrjm2sU61774317743epsmtip1T; Mon, 2 Feb 2026 10:19:57 +0000 (GMT) From: Raghav Sharma To: krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, conor+dt@kernel.org, sunyeal.hong@samsung.com, shin.son@samsung.com Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, chandan.vn@samsung.com, dev.tailor@samsung.com, karthik.sun@samsung.com, Raghav Sharma Subject: [PATCH 3/3] arm64: dts: exynosautov920: add CMU_G3D clock DT nodes Date: Mon, 2 Feb 2026 16:05:55 +0530 Message-Id: <20260202103555.2089376-4-raghav.s@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260202103555.2089376-1-raghav.s@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20260202102001epcas5p4ebe15ce1cec50c6ca024464ffdbe9d79 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P cpgsPolicy: CPGSC10-543,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20260202102001epcas5p4ebe15ce1cec50c6ca024464ffdbe9d79 References: <20260202103555.2089376-1-raghav.s@samsung.com> Add required dt node for cmu_g3d block, which provides clocks for G3D IP Signed-off-by: Raghav Sharma --- arch/arm64/boot/dts/exynos/exynosautov920.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/bo= ot/dts/exynos/exynosautov920.dtsi index 02bf2ca52fdc..0bf7c4cb9846 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -1473,6 +1473,19 @@ cmu_mfd: clock-controller@19e00000 { "noc"; }; =20 + cmu_g3d: clock-controller@1a000000 { + compatible =3D "samsung,exynosautov920-cmu-g3d"; + reg =3D <0x1a000000 0x8000>; + #clock-cells =3D <1>; + + clocks =3D <&xtcxo>, + <&cmu_top DOUT_CLKCMU_G3D_SWITCH>, + <&cmu_top DOUT_CLKCMU_G3D_NOCP>; + clock-names =3D "oscclk", + "switch", + "nocp"; + }; + pinctrl_aud: pinctrl@1a460000 { compatible =3D "samsung,exynosautov920-pinctrl"; reg =3D <0x1a460000 0x10000>; --=20 2.34.1