From nobody Sun Feb 8 02:26:20 2026 Received: from sg-1-107.ptr.blmpb.com (sg-1-107.ptr.blmpb.com [118.26.132.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E51EC142E83 for ; Mon, 2 Feb 2026 09:42:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=118.26.132.107 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770025356; cv=none; b=P9Z2hjtlp/c6Ssok6enHb/6P4h8Jb/27GyRX0x+tdhAGAPIRLL1ytQUQZfJdxX6/0o+fTixemMs8FzT4kRmVLMl4uCCAfk4L2h6c9XFKxZrrjknUZLKfCMsoxF1XMWfoRnmi6uwB1gE+xOUz2yTmWjh0z2pHh+oxYvtQAGIlRQU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770025356; c=relaxed/simple; bh=tg1vTMFqVPNVY+um7xYJoQ73ON6oPn9ZZCPy8T75IfE=; h=To:Message-Id:Date:Mime-Version:Content-Type:Cc:Subject:From; b=Q1lBvjagFC8dzO0KIHXfePLfDpw9jRZvQ7kaZBlURnGkSg2cK0Jj8zYEVkygO0+/YKPrkGsh8AkpjCyqpnuCetD5ht+OVfYZAIQJxvvF7ym8Xhw+FImbLBLcVNkqwh7oHlPH8CgSKrosrs6gBsCCqmk1+MuBAv8W78UxTgvBnoc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=bytedance.com; spf=pass smtp.mailfrom=bytedance.com; dkim=pass (2048-bit key) header.d=bytedance.com header.i=@bytedance.com header.b=B3ONIYjf; arc=none smtp.client-ip=118.26.132.107 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=bytedance.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bytedance.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bytedance.com header.i=@bytedance.com header.b="B3ONIYjf" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=2212171451; d=bytedance.com; t=1770025335; h=from:subject: mime-version:from:date:message-id:subject:to:cc:reply-to:content-type: mime-version:in-reply-to:message-id; bh=CixEHNZ+yVLBGfbMvIESwy7kUtGWgF6cLrpSlMLvomg=; b=B3ONIYjfUE5j49SxApzTw6XtjTF4IWbZYvFZhRMgrN7iuc4YlcPZhNPppgziit1nQFhXPB mvTle1ZlmkOAUhx7F9KhKLpFoLtqpjPU3tNiAXF5IRLP9tSUgIsSJaEzE0/TDqzbu6sJLj 2QyMYjNgGpOq5ARO4dyVBi+WYnGGpxZ6jVSUIAe7HloCyKhW5eI6YYnDmcfF8k8xWu8A3v 6wiIh5ZEo/OJqfBLx0nXyvx3L5FB/slakq7+6MT54oK2JedykRngG6sLzVoHDC24d4Fozd /dI85efawLe6a5bvikiLRqIfokIl/jj88y+lEZVGkwd/dRqwP8/U/01qeA5gtQ== Content-Transfer-Encoding: quoted-printable X-Lms-Return-Path: To: Message-Id: <20260202094200.53735-1-qirui.001@bytedance.com> Date: Mon, 2 Feb 2026 17:42:00 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 X-Mailer: git-send-email 2.52.0 Cc: , "Rui Qi" Subject: [PATCH v1] riscv: add hardware error trap handler support From: "\"$(name)\" <$(mail address)>" X-Original-From: "$(name)" <$(mail address)> Content-Type: text/plain; charset="utf-8" From: Rui Qi adds support for handling hardware error traps (exception code 19) in the RISC-V architecture. The changes include: - Add do_trap_hardware_error function declaration in asm-prototypes.h - Add hardware error trap vector entry in entry.S exception vector table - Implement do_trap_hardware_error handler in traps.c that generates SIGBUS with BUS_MCEERR_AR for hardware errors This enables proper handling of hardware error exceptions that may occur in RISC-V systems, providing appropriate error reporting and signal generation for user space processes. Signed-off-by: Rui Qi --- arch/riscv/include/asm/asm-prototypes.h | 1 + arch/riscv/kernel/entry.S | 1 + arch/riscv/kernel/traps.c | 2 ++ 3 files changed, 4 insertions(+) diff --git a/arch/riscv/include/asm/asm-prototypes.h b/arch/riscv/include/a= sm/asm-prototypes.h index 41ec5cdec367..5b90ba5314ee 100644 --- a/arch/riscv/include/asm/asm-prototypes.h +++ b/arch/riscv/include/asm/asm-prototypes.h @@ -40,6 +40,7 @@ asmlinkage void riscv_v_context_nesting_end(struct pt_reg= s *regs); #define DECLARE_DO_ERROR_INFO(name) asmlinkage void name(struct pt_regs *r= egs) =20 DECLARE_DO_ERROR_INFO(do_trap_unknown); +DECLARE_DO_ERROR_INFO(do_trap_hardware_error); DECLARE_DO_ERROR_INFO(do_trap_insn_misaligned); DECLARE_DO_ERROR_INFO(do_trap_insn_fault); DECLARE_DO_ERROR_INFO(do_trap_insn_illegal); diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 60eb221296a6..d011fb51c59a 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -498,6 +498,7 @@ SYM_DATA_START_LOCAL(excp_vect_table) RISCV_PTR do_trap_unknown /* cause=3D16 */ RISCV_PTR do_trap_unknown /* cause=3D17 */ RISCV_PTR do_trap_software_check /* cause=3D18 is sw check exception */ + RISCV_PTR do_trap_hardware_error /* hardware error (19) */ SYM_DATA_END_LABEL(excp_vect_table, SYM_L_LOCAL, excp_vect_table_end) =20 #ifndef CONFIG_MMU diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 5fb57fad188a..7cdb5b26d03d 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -165,6 +165,8 @@ asmlinkage __visible __trap_section void name(struct pt= _regs *regs) \ =20 DO_ERROR_INFO(do_trap_unknown, SIGILL, ILL_ILLTRP, "unknown exception"); +DO_ERROR_INFO(do_trap_hardware_error, + SIGBUS, BUS_MCEERR_AR, "hardware error"); DO_ERROR_INFO(do_trap_insn_misaligned, SIGBUS, BUS_ADRALN, "instruction address misaligned"); DO_ERROR_INFO(do_trap_insn_fault, --=20 2.20.1