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Mon, 02 Feb 2026 00:05:50 -0800 (PST) From: Svyatoslav Ryhel To: Greg Kroah-Hartman , Mikko Perttunen , Thierry Reding , Jonathan Hunter , Svyatoslav Ryhel Cc: linux-usb@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 1/4] usb: phy: tegra: cosmetic fixes Date: Mon, 2 Feb 2026 10:05:23 +0200 Message-ID: <20260202080526.23487-2-clamor95@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260202080526.23487-1-clamor95@gmail.com> References: <20260202080526.23487-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Change TEGRA_USB_HOSTPC1_DEVLC_PTS_HSIC to its literal value instead of using the BIT macro, as it is an enumeration. Correct the spelling in the comment and rename uhsic_registers_shift to uhsic_registers_offset. These changes are cosmetic and do not affect code behavior. Signed-off-by: Svyatoslav Ryhel --- drivers/usb/phy/phy-tegra-usb.c | 12 ++++++------ include/linux/usb/tegra_usb_phy.h | 4 ++-- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/usb/phy/phy-tegra-usb.c b/drivers/usb/phy/phy-tegra-us= b.c index effa767ec019..3a7a74f01d1c 100644 --- a/drivers/usb/phy/phy-tegra-usb.c +++ b/drivers/usb/phy/phy-tegra-usb.c @@ -48,7 +48,7 @@ #define TEGRA_USB_HOSTPC1_DEVLC 0x1b4 #define TEGRA_USB_HOSTPC1_DEVLC_PTS(x) (((x) & 0x7) << 29) #define TEGRA_USB_HOSTPC1_DEVLC_PHCD BIT(22) -#define TEGRA_USB_HOSTPC1_DEVLC_PTS_HSIC BIT(2) +#define TEGRA_USB_HOSTPC1_DEVLC_PTS_HSIC 4 =20 /* Bits of PORTSC1, which will get cleared by writing 1 into them */ #define TEGRA_PORTSC1_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) @@ -169,7 +169,7 @@ /* * Tegra20 has no UTMIP registers on PHY2 and UHSIC registers start from 0= x800 * just where UTMIP registers should have been. This is the case only with= Tegra20 - * Tegra30+ have UTMIP registers at 0x800 and UHSIC registers shifter by 0= x400 + * Tegra30+ have UTMIP registers at 0x800 and UHSIC registers are shifted = by 0x400 * to 0xc00, but register layout is preserved. */ #define UHSIC_PLL_CFG1 0x804 @@ -873,7 +873,7 @@ static int ulpi_phy_power_off(struct tegra_usb_phy *phy) static u32 tegra_hsic_readl(struct tegra_usb_phy *phy, u32 reg) { void __iomem *base =3D phy->regs; - u32 shift =3D phy->soc_config->uhsic_registers_shift; + u32 shift =3D phy->soc_config->uhsic_registers_offset; =20 return readl_relaxed(base + shift + reg); } @@ -881,7 +881,7 @@ static u32 tegra_hsic_readl(struct tegra_usb_phy *phy, = u32 reg) static void tegra_hsic_writel(struct tegra_usb_phy *phy, u32 reg, u32 valu= e) { void __iomem *base =3D phy->regs; - u32 shift =3D phy->soc_config->uhsic_registers_shift; + u32 shift =3D phy->soc_config->uhsic_registers_offset; =20 writel_relaxed(value, base + shift + reg); } @@ -1469,7 +1469,7 @@ static const struct tegra_phy_soc_config tegra20_soc_= config =3D { .requires_usbmode_setup =3D false, .requires_extra_tuning_parameters =3D false, .requires_pmc_ao_power_up =3D false, - .uhsic_registers_shift =3D 0, + .uhsic_registers_offset =3D 0, .uhsic_tx_rtune =3D 0, /* 40 ohm */ }; =20 @@ -1479,7 +1479,7 @@ static const struct tegra_phy_soc_config tegra30_soc_= config =3D { .requires_usbmode_setup =3D true, .requires_extra_tuning_parameters =3D true, .requires_pmc_ao_power_up =3D true, - .uhsic_registers_shift =3D 0x400, + .uhsic_registers_offset =3D 0x400, .uhsic_tx_rtune =3D 8, /* 50 ohm */ }; =20 diff --git a/include/linux/usb/tegra_usb_phy.h b/include/linux/usb/tegra_us= b_phy.h index 1a8843bd1e95..fbdd2dcb3a2b 100644 --- a/include/linux/usb/tegra_usb_phy.h +++ b/include/linux/usb/tegra_usb_phy.h @@ -24,7 +24,7 @@ struct gpio_desc; * requires_extra_tuning_parameters: true if xcvr_hsslew, hssquelch_level * and hsdiscon_level should be set for adequate signal quality * requires_pmc_ao_power_up: true if USB AO is powered down by default - * uhsic_registers_shift: for Tegra30+ where HSIC registers were shifted + * uhsic_registers_offset: for Tegra30+ where HSIC registers were offset * comparing to Tegra20 by 0x400, since Tegra20 has no UTMIP on PHY2 * uhsic_tx_rtune: fine tuned 50 Ohm termination resistor for NMOS/PMOS dr= iver */ @@ -35,7 +35,7 @@ struct tegra_phy_soc_config { bool requires_usbmode_setup; bool requires_extra_tuning_parameters; bool requires_pmc_ao_power_up; - u32 uhsic_registers_shift; + u32 uhsic_registers_offset; u32 uhsic_tx_rtune; }; =20 --=20 2.51.0