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Mon, 02 Feb 2026 00:05:50 -0800 (PST) From: Svyatoslav Ryhel To: Greg Kroah-Hartman , Mikko Perttunen , Thierry Reding , Jonathan Hunter , Svyatoslav Ryhel Cc: linux-usb@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 1/4] usb: phy: tegra: cosmetic fixes Date: Mon, 2 Feb 2026 10:05:23 +0200 Message-ID: <20260202080526.23487-2-clamor95@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260202080526.23487-1-clamor95@gmail.com> References: <20260202080526.23487-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Change TEGRA_USB_HOSTPC1_DEVLC_PTS_HSIC to its literal value instead of using the BIT macro, as it is an enumeration. Correct the spelling in the comment and rename uhsic_registers_shift to uhsic_registers_offset. These changes are cosmetic and do not affect code behavior. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen --- drivers/usb/phy/phy-tegra-usb.c | 12 ++++++------ include/linux/usb/tegra_usb_phy.h | 4 ++-- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/usb/phy/phy-tegra-usb.c b/drivers/usb/phy/phy-tegra-us= b.c index effa767ec019..3a7a74f01d1c 100644 --- a/drivers/usb/phy/phy-tegra-usb.c +++ b/drivers/usb/phy/phy-tegra-usb.c @@ -48,7 +48,7 @@ #define TEGRA_USB_HOSTPC1_DEVLC 0x1b4 #define TEGRA_USB_HOSTPC1_DEVLC_PTS(x) (((x) & 0x7) << 29) #define TEGRA_USB_HOSTPC1_DEVLC_PHCD BIT(22) -#define TEGRA_USB_HOSTPC1_DEVLC_PTS_HSIC BIT(2) +#define TEGRA_USB_HOSTPC1_DEVLC_PTS_HSIC 4 =20 /* Bits of PORTSC1, which will get cleared by writing 1 into them */ #define TEGRA_PORTSC1_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) @@ -169,7 +169,7 @@ /* * Tegra20 has no UTMIP registers on PHY2 and UHSIC registers start from 0= x800 * just where UTMIP registers should have been. This is the case only with= Tegra20 - * Tegra30+ have UTMIP registers at 0x800 and UHSIC registers shifter by 0= x400 + * Tegra30+ have UTMIP registers at 0x800 and UHSIC registers are shifted = by 0x400 * to 0xc00, but register layout is preserved. */ #define UHSIC_PLL_CFG1 0x804 @@ -873,7 +873,7 @@ static int ulpi_phy_power_off(struct tegra_usb_phy *phy) static u32 tegra_hsic_readl(struct tegra_usb_phy *phy, u32 reg) { void __iomem *base =3D phy->regs; - u32 shift =3D phy->soc_config->uhsic_registers_shift; + u32 shift =3D phy->soc_config->uhsic_registers_offset; =20 return readl_relaxed(base + shift + reg); } @@ -881,7 +881,7 @@ static u32 tegra_hsic_readl(struct tegra_usb_phy *phy, = u32 reg) static void tegra_hsic_writel(struct tegra_usb_phy *phy, u32 reg, u32 valu= e) { void __iomem *base =3D phy->regs; - u32 shift =3D phy->soc_config->uhsic_registers_shift; + u32 shift =3D phy->soc_config->uhsic_registers_offset; =20 writel_relaxed(value, base + shift + reg); } @@ -1469,7 +1469,7 @@ static const struct tegra_phy_soc_config tegra20_soc_= config =3D { .requires_usbmode_setup =3D false, .requires_extra_tuning_parameters =3D false, .requires_pmc_ao_power_up =3D false, - .uhsic_registers_shift =3D 0, + .uhsic_registers_offset =3D 0, .uhsic_tx_rtune =3D 0, /* 40 ohm */ }; =20 @@ -1479,7 +1479,7 @@ static const struct tegra_phy_soc_config tegra30_soc_= config =3D { .requires_usbmode_setup =3D true, .requires_extra_tuning_parameters =3D true, .requires_pmc_ao_power_up =3D true, - .uhsic_registers_shift =3D 0x400, + .uhsic_registers_offset =3D 0x400, .uhsic_tx_rtune =3D 8, /* 50 ohm */ }; =20 diff --git a/include/linux/usb/tegra_usb_phy.h b/include/linux/usb/tegra_us= b_phy.h index 1a8843bd1e95..fbdd2dcb3a2b 100644 --- a/include/linux/usb/tegra_usb_phy.h +++ b/include/linux/usb/tegra_usb_phy.h @@ -24,7 +24,7 @@ struct gpio_desc; * requires_extra_tuning_parameters: true if xcvr_hsslew, hssquelch_level * and hsdiscon_level should be set for adequate signal quality * requires_pmc_ao_power_up: true if USB AO is powered down by default - * uhsic_registers_shift: for Tegra30+ where HSIC registers were shifted + * uhsic_registers_offset: for Tegra30+ where HSIC registers were offset * comparing to Tegra20 by 0x400, since Tegra20 has no UTMIP on PHY2 * uhsic_tx_rtune: fine tuned 50 Ohm termination resistor for NMOS/PMOS dr= iver */ @@ -35,7 +35,7 @@ struct tegra_phy_soc_config { bool requires_usbmode_setup; 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Mon, 02 Feb 2026 00:05:51 -0800 (PST) From: Svyatoslav Ryhel To: Greg Kroah-Hartman , Mikko Perttunen , Thierry Reding , Jonathan Hunter , Svyatoslav Ryhel Cc: linux-usb@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/4] usb: phy: tegra: return error value from utmi_wait_register Date: Mon, 2 Feb 2026 10:05:24 +0200 Message-ID: <20260202080526.23487-3-clamor95@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260202080526.23487-1-clamor95@gmail.com> References: <20260202080526.23487-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Return exact error value from utmi_wait_register during HSIC power on. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen --- drivers/usb/phy/phy-tegra-usb.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/usb/phy/phy-tegra-usb.c b/drivers/usb/phy/phy-tegra-us= b.c index 3a7a74f01d1c..6173b240c3ea 100644 --- a/drivers/usb/phy/phy-tegra-usb.c +++ b/drivers/usb/phy/phy-tegra-usb.c @@ -891,6 +891,7 @@ static int uhsic_phy_power_on(struct tegra_usb_phy *phy) struct tegra_utmip_config *config =3D phy->config; void __iomem *base =3D phy->regs; u32 val; + int err =3D 0; =20 val =3D tegra_hsic_readl(phy, UHSIC_PADS_CFG1); val &=3D ~(UHSIC_PD_BG | UHSIC_PD_TX | UHSIC_PD_TRK | UHSIC_PD_RX | @@ -984,12 +985,14 @@ static int uhsic_phy_power_on(struct tegra_usb_phy *p= hy) val |=3D UHSIC_TX_RTUNE(phy->soc_config->uhsic_tx_rtune); tegra_hsic_writel(phy, UHSIC_PADS_CFG0, val); =20 - if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, - USB_PHY_CLK_VALID)) + err =3D utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, + USB_PHY_CLK_VALID); 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Mon, 02 Feb 2026 00:05:51 -0800 (PST) From: Svyatoslav Ryhel To: Greg Kroah-Hartman , Mikko Perttunen , Thierry Reding , Jonathan Hunter , Svyatoslav Ryhel Cc: linux-usb@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 3/4] usb: phy: tegra: parametrize HSIC PTS value Date: Mon, 2 Feb 2026 10:05:25 +0200 Message-ID: <20260202080526.23487-4-clamor95@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260202080526.23487-1-clamor95@gmail.com> References: <20260202080526.23487-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The parallel transceiver select used in HSIC mode differs on Tegra20, where it uses the UTMI value (0), whereas Tegra30+ uses a dedicated HSIC value. Reflect this in the SoC config. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen --- drivers/usb/phy/phy-tegra-usb.c | 7 +++---- include/linux/usb/tegra_usb_phy.h | 2 ++ 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/usb/phy/phy-tegra-usb.c b/drivers/usb/phy/phy-tegra-us= b.c index 6173b240c3ea..812d99443180 100644 --- a/drivers/usb/phy/phy-tegra-usb.c +++ b/drivers/usb/phy/phy-tegra-usb.c @@ -957,10 +957,7 @@ static int uhsic_phy_power_on(struct tegra_usb_phy *ph= y) writel_relaxed(val, base + USB_USBMODE); } =20 - if (phy->soc_config->has_hostpc) - set_pts(phy, TEGRA_USB_HOSTPC1_DEVLC_PTS_HSIC); - else - set_pts(phy, 0); + set_pts(phy, phy->soc_config->uhsic_pts_value); =20 val =3D readl_relaxed(base + USB_TXFILLTUNING); if ((val & USB_FIFO_TXFILL_MASK) !=3D USB_FIFO_TXFILL_THRES(0x10)) { @@ -1474,6 +1471,7 @@ static const struct tegra_phy_soc_config tegra20_soc_= config =3D { .requires_pmc_ao_power_up =3D false, .uhsic_registers_offset =3D 0, .uhsic_tx_rtune =3D 0, /* 40 ohm */ + .uhsic_pts_value =3D 0, /* UTMI */ }; =20 static const struct tegra_phy_soc_config tegra30_soc_config =3D { @@ -1484,6 +1482,7 @@ static const struct tegra_phy_soc_config tegra30_soc_= config =3D { .requires_pmc_ao_power_up =3D true, .uhsic_registers_offset =3D 0x400, .uhsic_tx_rtune =3D 8, /* 50 ohm */ + .uhsic_pts_value =3D TEGRA_USB_HOSTPC1_DEVLC_PTS_HSIC, }; =20 static const struct of_device_id tegra_usb_phy_id_table[] =3D { diff --git a/include/linux/usb/tegra_usb_phy.h b/include/linux/usb/tegra_us= b_phy.h index fbdd2dcb3a2b..81d9f22e58b5 100644 --- a/include/linux/usb/tegra_usb_phy.h +++ b/include/linux/usb/tegra_usb_phy.h @@ -27,6 +27,7 @@ struct gpio_desc; * uhsic_registers_offset: for Tegra30+ where HSIC registers were offset * comparing to Tegra20 by 0x400, since Tegra20 has no UTMIP on PHY2 * uhsic_tx_rtune: fine tuned 50 Ohm termination resistor for NMOS/PMOS dr= iver + * uhsic_pts_value: parallel transceiver select enumeration value */ =20 struct tegra_phy_soc_config { @@ -37,6 +38,7 @@ struct tegra_phy_soc_config { bool requires_pmc_ao_power_up; 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Mon, 02 Feb 2026 00:05:52 -0800 (PST) From: Svyatoslav Ryhel To: Greg Kroah-Hartman , Mikko Perttunen , Thierry Reding , Jonathan Hunter , Svyatoslav Ryhel Cc: linux-usb@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 4/4] usb: phy: tegra: parametrize PORTSC1 register offset Date: Mon, 2 Feb 2026 10:05:26 +0200 Message-ID: <20260202080526.23487-5-clamor95@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260202080526.23487-1-clamor95@gmail.com> References: <20260202080526.23487-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The PORTSC1 register has a different offset in Tegra20 compared to Tegra30+, yet they share a crucial set of registers required for HSIC functionality. Reflect this register offset change in the SoC config. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen --- drivers/usb/phy/phy-tegra-usb.c | 17 ++++++----------- include/linux/usb/tegra_usb_phy.h | 2 ++ 2 files changed, 8 insertions(+), 11 deletions(-) diff --git a/drivers/usb/phy/phy-tegra-usb.c b/drivers/usb/phy/phy-tegra-us= b.c index 812d99443180..00443a7beaeb 100644 --- a/drivers/usb/phy/phy-tegra-usb.c +++ b/drivers/usb/phy/phy-tegra-usb.c @@ -965,17 +965,10 @@ static int uhsic_phy_power_on(struct tegra_usb_phy *p= hy) writel_relaxed(val, base + USB_TXFILLTUNING); } =20 - if (phy->soc_config->has_hostpc) { - val =3D readl_relaxed(base + TEGRA30_USB_PORTSC1); - val &=3D ~(TEGRA_USB_PORTSC1_WKOC | TEGRA_USB_PORTSC1_WKDS | - TEGRA_USB_PORTSC1_WKCN); - writel_relaxed(val, base + TEGRA30_USB_PORTSC1); - } else { - val =3D readl_relaxed(base + TEGRA_USB_PORTSC1); - val &=3D ~(TEGRA_USB_PORTSC1_WKOC | TEGRA_USB_PORTSC1_WKDS | - TEGRA_USB_PORTSC1_WKCN); - writel_relaxed(val, base + TEGRA_USB_PORTSC1); - } + val =3D readl_relaxed(base + phy->soc_config->portsc1_offset); + val &=3D ~(TEGRA_USB_PORTSC1_WKOC | TEGRA_USB_PORTSC1_WKDS | + TEGRA_USB_PORTSC1_WKCN); + writel_relaxed(val, base + phy->soc_config->portsc1_offset); =20 val =3D tegra_hsic_readl(phy, UHSIC_PADS_CFG0); val &=3D ~UHSIC_TX_RTUNEN; @@ -1472,6 +1465,7 @@ static const struct tegra_phy_soc_config tegra20_soc_= config =3D { .uhsic_registers_offset =3D 0, .uhsic_tx_rtune =3D 0, /* 40 ohm */ .uhsic_pts_value =3D 0, /* UTMI */ + .portsc1_offset =3D TEGRA_USB_PORTSC1, }; =20 static const struct tegra_phy_soc_config tegra30_soc_config =3D { @@ -1483,6 +1477,7 @@ static const struct tegra_phy_soc_config tegra30_soc_= config =3D { .uhsic_registers_offset =3D 0x400, .uhsic_tx_rtune =3D 8, /* 50 ohm */ .uhsic_pts_value =3D TEGRA_USB_HOSTPC1_DEVLC_PTS_HSIC, + .portsc1_offset =3D TEGRA30_USB_PORTSC1, }; =20 static const struct of_device_id tegra_usb_phy_id_table[] =3D { diff --git a/include/linux/usb/tegra_usb_phy.h b/include/linux/usb/tegra_us= b_phy.h index 81d9f22e58b5..57e22aae6247 100644 --- a/include/linux/usb/tegra_usb_phy.h +++ b/include/linux/usb/tegra_usb_phy.h @@ -28,6 +28,7 @@ struct gpio_desc; * comparing to Tegra20 by 0x400, since Tegra20 has no UTMIP on PHY2 * uhsic_tx_rtune: fine tuned 50 Ohm termination resistor for NMOS/PMOS dr= iver * uhsic_pts_value: parallel transceiver select enumeration value + * portsc1_offset: register offset of PORTSC1 */ =20 struct tegra_phy_soc_config { @@ -39,6 +40,7 @@ struct tegra_phy_soc_config { u32 uhsic_registers_offset; u32 uhsic_tx_rtune; u32 uhsic_pts_value; + u32 portsc1_offset; }; =20 struct tegra_utmip_config { --=20 2.51.0