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Mon, 2 Feb 2026 01:28:10 -0600 From: Aksh Garg To: , , , , , , , , , , , CC: , , , Aksh Garg Subject: [PATCH 2/2] PCI: dwc: ep: Mirror the max link width and speed fields to all functions Date: Mon, 2 Feb 2026 12:57:58 +0530 Message-ID: <20260202072758.101845-3-a-garg7@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260202072758.101845-1-a-garg7@ti.com> References: <20260202072758.101845-1-a-garg7@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C37F:EE_|DS0PR10MB7203:EE_ X-MS-Office365-Filtering-Correlation-Id: 248cdec6-005a-4d3a-f096-08de622ca0fc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|7416014|376014|36860700013|921020; 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charset="utf-8" PCIe r6.0, section 7.5.3.6 states that for multi-function devices, the Max Link Width and Max Link Speed fields in the Link Capabilities Register must report the same values for all functions. Currently, dw_pcie_setup() programs these fields only for physical function 0 (PF0) via dw_pcie_link_set_max_speed() and dw_pcie_link_set_max_link_width(). For multi-function endpoint configurations, PF1 and beyond retain their default values, violating the PCIe specification. Fix this by reading the Max Link Width and Max Link Speed fields from PF0's Link Capabilities Register after dw_pcie_setup() completes, then mirroring these values to all other physical functions. Fixes: 24ede430fa49 ("PCI: designware-ep: Add multiple PFs support for DWC") Fixes: 89db0793c9f2 ("PCI: dwc: Add missing PCI_EXP_LNKCAP_MLW handling") Signed-off-by: Aksh Garg --- The link speed and width would be negotiated through PF0 during initialization that controls the link behaviour, hence it didn't broke the driver. However, the change is proposed just to make the driver compatible with the PCIe base specifications. The fix is implemented in pcie-designware-ep.c rather than modifying dw_pcie_setup() directly to keep pcie-designware.c independent of RC/EP specifics and maintain it as common code. .../pci/controller/dwc/pcie-designware-ep.c | 24 ++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/= controller/dwc/pcie-designware-ep.c index 771241e1a2c9..4ac25da2b117 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -1094,7 +1094,8 @@ static void dw_pcie_ep_init_non_sticky_registers(stru= ct dw_pcie *pci) { struct dw_pcie_ep *ep =3D &pci->ep; u8 funcs =3D ep->epc->max_functions; - u8 func_no; + u32 ref_lnkcap, lnkcap; + u8 func_no, offset; =20 dw_pcie_dbi_ro_wr_en(pci); =20 @@ -1102,6 +1103,27 @@ static void dw_pcie_ep_init_non_sticky_registers(str= uct dw_pcie *pci) dw_pcie_ep_init_rebar_registers(ep, func_no); =20 dw_pcie_setup(pci); + + /* + * PCIe r6.0, section 7.5.3.6 states that for multi-function endpoints, + * max link width and speed fields must report same values for all functi= ons. + * However, dw_pcie_setup() programs these fields only for physical funct= ion 0. + * Hence, mirror these fields to all other physical functions as well. + */ + if (funcs > 1) { + offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + ref_lnkcap =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); + ref_lnkcap &=3D PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS; + + for (func_no =3D 1; func_no < funcs; func_no++) { + offset =3D dw_pcie_ep_find_capability(ep, func_no, PCI_CAP_ID_EXP); + lnkcap =3D dw_pcie_ep_readl_dbi(ep, func_no, offset + PCI_EXP_LNKCAP); + lnkcap &=3D ~(PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS); + lnkcap |=3D ref_lnkcap; + dw_pcie_ep_writel_dbi(ep, func_no, offset + PCI_EXP_LNKCAP, lnkcap); + } + } + dw_pcie_dbi_ro_wr_dis(pci); } =20 --=20 2.34.1