From nobody Mon Feb 9 15:26:04 2026 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A0C242F9D85; Mon, 2 Feb 2026 06:28:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770013734; cv=none; b=FkqSVM3eYlMIdLiereqNcE+5GeQ9XPtISq3BkvmtveDUXOn5WsXd6l3snSAfBCW+fnU6y4w/1S38lnOhrxuDV/DCCuf41o/D7IwI4D13MLimXq4K1e6wo2PBXCKM4iZGYiqMCV+ivIWtnDO74uuM3oTMbSYi9VGc8KL+HKrfADg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770013734; c=relaxed/simple; bh=akClU+dxQ869+SKcEWLXtsyxin7K6PI4gTCwZBYdwXM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=a8REzFr4Bax0mNAj3E/s3HGmDUtP33uAAjv4bJd9Dr7U1XexDy2RUxVDo2r8zxZmVdAux1r87IxmY5dm7qYjunIthobg7zXEeIMUR+5Ur0CEdSKSVtLEr7xKTldX6f6el1WRgd4sTNd4c88avqrEhc5Vh5JTQ64E6ai/usZ8M80= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=XuZgRwUM; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="XuZgRwUM" X-UUID: 6d37840c000011f185319dbc3099e8fb-20260202 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=2MO5pAeKaDnZlEBZfBK1faXM6L5WkJmGw9Ae7P9JBmk=; b=XuZgRwUMEU/H14it7uBIoDtbLvqRV3IC39YdRJkfhQhKWg93z0wZkXrvbqRKcYcZEsmIO6zpw8wM1t1yQb3y2e4vijYmSFbMS3HxEKKHQ4w6Br4Vv0p79zO1y2FfrdCyidbpw9gs4omvLjGcK8+wPxGxZI/1MMAZ76uuqs8Q7T4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.11,REQID:63d98649-dbfa-43b1-b116-1062f5134a90,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:89c9d04,CLOUDID:b5347b7a-8c8a-4fc4-88c0-3556e7711556,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:-3,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:-1,COL:0,OSI :0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 6d37840c000011f185319dbc3099e8fb-20260202 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1286572311; Mon, 02 Feb 2026 14:28:45 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Mon, 2 Feb 2026 14:28:44 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Mon, 2 Feb 2026 14:28:44 +0800 From: irving.ch.lin To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Richard Cochran , Bartosz Golaszewski , Chen-Yu Tsai , Miles Chen CC: , , , , , , , Qiqi Wang , , , , Subject: [PATCH v5 08/18] clk: mediatek: Add MT8189 cam clock support Date: Mon, 2 Feb 2026 14:28:15 +0800 Message-ID: <20260202062840.342707-9-irving-ch.lin@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20260202062840.342707-1-irving-ch.lin@mediatek.com> References: <20260202062840.342707-1-irving-ch.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Irving-CH Lin Add support for the MT8189 cam clock controller, which provides clock gate control for camera. Signed-off-by: Irving-CH Lin --- drivers/clk/mediatek/Kconfig | 11 +++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8189-cam.c | 108 ++++++++++++++++++++++++++ 3 files changed, 120 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8189-cam.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 47172623f29f..0665255a29fd 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -839,6 +839,17 @@ config COMMON_CLK_MT8189_BUS MT8189 chipset, ensuring that all bus-related components receive the correct clock signals for optimal performance. =20 +config COMMON_CLK_MT8189_CAM + tristate "Clock driver for MediaTek MT8189 cam" + depends on COMMON_CLK_MT8189 + default COMMON_CLK_MT8189 + help + Enable this to support the clock management for the camera interface + on MediaTek MT8189 SoCs. This includes enabling, disabling, and + setting the rate for camera-related clocks. If you have a camera + that relies on this SoC and you want to control its clocks, say Y or M + to include this driver in your kernel build. + config COMMON_CLK_MT8192 tristate "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index aabfb42cb1b2..95a8f4ae05ee 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -126,6 +126,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188_WPESYS) +=3D clk-mt8188-= wpe.o obj-$(CONFIG_COMMON_CLK_MT8189) +=3D clk-mt8189-apmixedsys.o clk-mt8189-to= pckgen.o \ clk-mt8189-vlpckgen.o clk-mt8189-vlpcfg.o obj-$(CONFIG_COMMON_CLK_MT8189_BUS) +=3D clk-mt8189-bus.o +obj-$(CONFIG_COMMON_CLK_MT8189_CAM) +=3D clk-mt8189-cam.o obj-$(CONFIG_COMMON_CLK_MT8192) +=3D clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) +=3D clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) +=3D clk-mt8192-cam.o diff --git a/drivers/clk/mediatek/clk-mt8189-cam.c b/drivers/clk/mediatek/c= lk-mt8189-cam.c new file mode 100644 index 000000000000..d65ac08cedd6 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189-cam.c @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Qiqi Wang + */ + +#include +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +static const struct mtk_gate_regs cam_m_cg_regs =3D { + .set_ofs =3D 0x4, + .clr_ofs =3D 0x8, + .sta_ofs =3D 0x0, +}; + +#define GATE_CAM_M(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &cam_m_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, CLK_IGNORE_UNUSED) + +static const struct mtk_gate cam_m_clks[] =3D { + GATE_CAM_M(CLK_CAM_M_LARB13, "cam_m_larb13", "cam_sel", 0), + GATE_CAM_M(CLK_CAM_M_LARB14, "cam_m_larb14", "cam_sel", 2), + GATE_CAM_M(CLK_CAM_M_CAMSYS_MAIN_CAM, "cam_m_camsys_main_cam", "cam_sel",= 6), + GATE_CAM_M(CLK_CAM_M_CAMSYS_MAIN_CAMTG, "cam_m_camsys_main_camtg", "cam_s= el", 7), + GATE_CAM_M(CLK_CAM_M_SENINF, "cam_m_seninf", "cam_sel", 8), + GATE_CAM_M(CLK_CAM_M_CAMSV1, "cam_m_camsv1", "cam_sel", 10), + GATE_CAM_M(CLK_CAM_M_CAMSV2, "cam_m_camsv2", "cam_sel", 11), + GATE_CAM_M(CLK_CAM_M_CAMSV3, "cam_m_camsv3", "cam_sel", 12), + GATE_CAM_M(CLK_CAM_M_FAKE_ENG, "cam_m_fake_eng", "cam_sel", 17), + GATE_CAM_M(CLK_CAM_M_CAM2MM_GALS, "cam_m_cam2mm_gals", "cam_sel", 19), + GATE_CAM_M(CLK_CAM_M_CAMSV4, "cam_m_camsv4", "cam_sel", 20), + GATE_CAM_M(CLK_CAM_M_PDA, "cam_m_pda", "cam_sel", 21), +}; + +static const struct mtk_clk_desc cam_m_mcd =3D { + .clks =3D cam_m_clks, + .num_clks =3D ARRAY_SIZE(cam_m_clks), +}; + +static const struct mtk_gate_regs cam_ra_cg_regs =3D { + .set_ofs =3D 0x4, + .clr_ofs =3D 0x8, + .sta_ofs =3D 0x0, +}; + +#define GATE_CAM_RA(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &cam_ra_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, CLK_IGNORE_UNUSED) + +static const struct mtk_gate cam_ra_clks[] =3D { + GATE_CAM_RA(CLK_CAM_RA_CAMSYS_RAWA_LARBX, "cam_ra_camsys_rawa_larbx", "ca= m_sel", 0), + GATE_CAM_RA(CLK_CAM_RA_CAMSYS_RAWA_CAM, "cam_ra_camsys_rawa_cam", "cam_se= l", 1), + GATE_CAM_RA(CLK_CAM_RA_CAMSYS_RAWA_CAMTG, "cam_ra_camsys_rawa_camtg", "ca= m_sel", 2), +}; + +static const struct mtk_clk_desc cam_ra_mcd =3D { + .clks =3D cam_ra_clks, + .num_clks =3D ARRAY_SIZE(cam_ra_clks), +}; + +static const struct mtk_gate_regs cam_rb_cg_regs =3D { + .set_ofs =3D 0x4, + .clr_ofs =3D 0x8, + .sta_ofs =3D 0x0, +}; + +#define GATE_CAM_RB(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &cam_rb_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, CLK_IGNORE_UNUSED) + +static const struct mtk_gate cam_rb_clks[] =3D { + GATE_CAM_RB(CLK_CAM_RB_CAMSYS_RAWB_LARBX, "cam_rb_camsys_rawb_larbx", "ca= m_sel", 0), + GATE_CAM_RB(CLK_CAM_RB_CAMSYS_RAWB_CAM, "cam_rb_camsys_rawb_cam", "cam_se= l", 1), + GATE_CAM_RB(CLK_CAM_RB_CAMSYS_RAWB_CAMTG, "cam_rb_camsys_rawb_camtg", "ca= m_sel", 2), +}; + +static const struct mtk_clk_desc cam_rb_mcd =3D { + .clks =3D cam_rb_clks, + .num_clks =3D ARRAY_SIZE(cam_rb_clks), +}; + +static const struct of_device_id of_match_clk_mt8189_cam[] =3D { + { .compatible =3D "mediatek,mt8189-camsys-main", .data =3D &cam_m_mcd }, + { .compatible =3D "mediatek,mt8189-camsys-rawa", .data =3D &cam_ra_mcd }, + { .compatible =3D "mediatek,mt8189-camsys-rawb", .data =3D &cam_rb_mcd }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_cam); + +static struct platform_driver clk_mt8189_cam_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8189-cam", + .of_match_table =3D of_match_clk_mt8189_cam, + }, +}; + +module_platform_driver(clk_mt8189_cam_drv); +MODULE_DESCRIPTION("MediaTek MT8189 cam clocks driver"); +MODULE_LICENSE("GPL"); --=20 2.45.2