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Signed-off-by: Irving-CH Lin --- drivers/clk/mediatek/Kconfig | 11 ++++++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8189-mfg.c | 53 +++++++++++++++++++++++++++ 3 files changed, 65 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8189-mfg.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index bd50e18e48f4..e2eb74d79cfd 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -906,6 +906,17 @@ config COMMON_CLK_MT8189_MDPSYS chipset, ensuring that the display system operates efficiently and effectively. =20 +config COMMON_CLK_MT8189_MFG + tristate "Clock driver for MediaTek MT8189 mfg" + depends on COMMON_CLK_MT8189 + default COMMON_CLK_MT8189 + help + Enable this option to support the manufacturing clocks for the MediaTek + MT8189 chipset. This driver provides the necessary clock framework + integration for manufacturing tests and operations that are specific to + the MT8189 chipset. Enabling this will allow the manufacturing mode of + the chipset to function correctly with the appropriate clock settings. + config COMMON_CLK_MT8192 tristate "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 9b23e4c5e019..07f11760cf68 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -132,6 +132,7 @@ obj-$(CONFIG_COMMON_CLK_MT8189_DVFSRC) +=3D clk-mt8189-= dvfsrc.o obj-$(CONFIG_COMMON_CLK_MT8189_IIC) +=3D clk-mt8189-iic.o obj-$(CONFIG_COMMON_CLK_MT8189_IMG) +=3D clk-mt8189-img.o obj-$(CONFIG_COMMON_CLK_MT8189_MDPSYS) +=3D clk-mt8189-mdpsys.o +obj-$(CONFIG_COMMON_CLK_MT8189_MFG) +=3D clk-mt8189-mfg.o obj-$(CONFIG_COMMON_CLK_MT8192) +=3D clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) +=3D clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) +=3D clk-mt8192-cam.o diff --git a/drivers/clk/mediatek/clk-mt8189-mfg.c b/drivers/clk/mediatek/c= lk-mt8189-mfg.c new file mode 100644 index 000000000000..a09bf8f2e017 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189-mfg.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Qiqi Wang + */ + +#include +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +static const struct mtk_gate_regs mfg_cg_regs =3D { + .set_ofs =3D 0x4, + .clr_ofs =3D 0x8, + .sta_ofs =3D 0x0, +}; + +#define GATE_MFG(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, CLK_IGNORE_UNUSED) + +static const struct mtk_gate mfg_clks[] =3D { + GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel_mfgpll", 0), +}; + +static const struct mtk_clk_desc mfg_mcd =3D { + .clks =3D mfg_clks, + .num_clks =3D ARRAY_SIZE(mfg_clks), +}; + +static const struct of_device_id of_match_clk_mt8189_mfg[] =3D { + { .compatible =3D "mediatek,mt8189-mfgcfg", .data =3D &mfg_mcd }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_mfg); + +static struct platform_driver clk_mt8189_mfg_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8189-mfg", + .of_match_table =3D of_match_clk_mt8189_mfg, + }, +}; + +module_platform_driver(clk_mt8189_mfg_drv); +MODULE_DESCRIPTION("MediaTek MT8189 mfg clocks driver"); +MODULE_LICENSE("GPL"); --=20 2.45.2