From nobody Mon Feb 9 23:16:13 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A868378803; Mon, 2 Feb 2026 14:58:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770044300; cv=none; b=BCwiaxvU+hLlcnoPTAhCsINxg5Om1udsXp9Nz441YCIuKYihthH/KQvfTd+IaX/JbelAd0oG67N0AiiG5TFpEiytLNeRpZK1tGOQsj9QbdyA9Xa5+EOdOXEsRpdjrplGGcJASkvFQOwb0gaqV6nUBtSiNgjTjjttmE+NTffNRRo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770044300; c=relaxed/simple; bh=w8CT5nF4xuNQYgtEB/14jQDFCsAZe2Yvi9iEBlAn/4o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rTCrSuQnEE8aehwMQRFh047JDT8DQ7YD0aMtqBjsRU0gBV8BsghpmYWm5hZmXQ2tjaul0Rsstx5UptU0WgSSqTt+WDoy2Hb5xKsmK7tCdLqsd2bkXSRYnp2va+n4MfrUF2HD8q4+8hrbchowZCq7GTpAAPYNsK/tDFkJCu7BV2Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SHzk4wbs; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SHzk4wbs" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0C637C116C6; Mon, 2 Feb 2026 14:58:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1770044300; bh=w8CT5nF4xuNQYgtEB/14jQDFCsAZe2Yvi9iEBlAn/4o=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=SHzk4wbscWkXQoaAwuSpZM6lT4H+y1BpHYlL8H2srXYCqJk05iz3knoiTqOYuPv7V 7edbIBPdPQrJgU9YTmSVQVjaBZ/CbSA76QXDq0zmetLaFDxa4urwRHNWnxNaod61+Z jDiAtMUA5rwAOY6dLIuuj82EjNZgLVE/GwzTWVD0ljKXgAoV/WrMJZ3PZMOAkI3RUs PN7XQ4Ew7bicr266l8bevB3vAlEadzou1A3SP4aOSbGfo0yjpvKqUuRtTNDrJrM+1H TsJ9uBJhKlcLKK4UvfTmj0XoCd1fKJF+DN9gq+RNNye3Z67xgUFZw/uAJ9SL6+vqBm Fy07BOHpqxR5g== From: Konrad Dybcio Date: Mon, 02 Feb 2026 15:57:37 +0100 Subject: [PATCH RFC 5/8] arm64: dts: qcom: Remove inexistent TCSR_CC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260202-topic-8750_tcsr-v1-5-cd7e6648c64f@oss.qualcomm.com> References: <20260202-topic-8750_tcsr-v1-0-cd7e6648c64f@oss.qualcomm.com> In-Reply-To: <20260202-topic-8750_tcsr-v1-0-cd7e6648c64f@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Taniya Das , Linus Walleij , Melody Olvera , Konrad Dybcio , Taniya Das , Raviteja Laggyshetty , Jishnu Prakash Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Mukesh Ojha , Konrad Dybcio , stable+noautosel@kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770044267; l=3098; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=wqBz3XZ7otCfDneRsMc+hVuBgRcuU5xR3d2hpgBDzfo=; b=+Goy1gGvRaC61VyZMpeKlsXAhXDhatyIKZtR1iz6TzVnSlKIRQlp7mE581WHyIBUgOE40REbo LUPXCL9gGbrAAvb1CoJAWV3R7JG1pEUASFwkc7tmIjU0UgEqBSwDumH X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio On SM8750 specifically, the block which provides various reference clocks does *NOT* live inside TCSR, but rather TLMM. With the former now being able to properly expose them, switch over to the proper source. Now, the TCSR still exists as a block for various tunables and switches, however the prior misuse resulted in its 8750-specifc compatible being already in use. With it freed up, it is now free again to be described properly. Fixes: 068c3d3c83be ("arm64: dts: qcom: Add base SM8750 dtsi") Cc: # complex dependencies, no immediate gain Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 22 ++++++++-------------- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qco= m/sm8750.dtsi index f56b1f889b85..0c034ba0517f 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -2727,7 +2727,7 @@ usb_hsphy: phy@88e3000 { compatible =3D "qcom,sm8750-m31-eusb2-phy"; reg =3D <0x0 0x88e3000 0x0 0x29c>; =20 - clocks =3D <&tcsrcc TCSR_USB2_CLKREF_EN>; + clocks =3D <&tlmm TCSR_USB2_CLKREF_EN>; clock-names =3D "ref"; =20 resets =3D <&gcc GCC_QUSB2PHY_PRIM_BCR>; @@ -2742,7 +2742,7 @@ usb_dp_qmpphy: phy@88e8000 { reg =3D <0x0 0x088e8000 0x0 0x4000>; =20 clocks =3D <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&tcsrcc TCSR_USB3_CLKREF_EN>, + <&tlmm TCSR_USB3_CLKREF_EN>, <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; clock-names =3D "aux", @@ -3063,6 +3063,8 @@ tlmm: pinctrl@f100000 { compatible =3D "qcom,sm8750-tlmm"; reg =3D <0x0 0x0f100000 0x0 0x102000>; =20 + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + interrupts =3D ; =20 gpio-controller; @@ -3074,6 +3076,8 @@ tlmm: pinctrl@f100000 { gpio-ranges =3D <&tlmm 0 0 216>; wakeup-parent =3D <&pdc>; =20 + #clock-cells =3D <1>; + hub_i2c0_data_clk: hub-i2c0-data-clk-state { /* SDA, SCL */ pins =3D "gpio64", "gpio65"; @@ -3564,16 +3568,6 @@ data-pins { }; }; =20 - tcsrcc: clock-controller@f204008 { - compatible =3D "qcom,sm8750-tcsr", "syscon"; - reg =3D <0x0 0x0f204008 0x0 0x3004>; - - clocks =3D <&rpmhcc RPMH_CXO_CLK>; - - #clock-cells =3D <1>; - #reset-cells =3D <1>; - }; - stm@10002000 { compatible =3D "arm,coresight-stm", "arm,primecell"; reg =3D <0x0 0x10002000 0x0 0x1000>, @@ -4818,7 +4812,7 @@ pcie0_phy: phy@1c06000 { =20 clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&tcsrcc TCSR_PCIE_0_CLKREF_EN>, + <&tlmm TCSR_PCIE_0_CLKREF_EN>, <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK>; clock-names =3D "aux", @@ -4849,7 +4843,7 @@ ufs_mem_phy: phy@1d80000 { =20 clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, - <&tcsrcc TCSR_UFS_CLKREF_EN>; + <&tlmm TCSR_UFS_CLKREF_EN>; =20 clock-names =3D "ref", "ref_aux", --=20 2.52.0