From nobody Mon Feb 9 19:52:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B472237757B; Mon, 2 Feb 2026 14:58:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770044289; cv=none; b=hi1GYyUBm8A2UW7KfVWd64ORx25b0+WLiqntO3wTDVBav9Q6sUErBz03rrkHsZVxYFvXacV2AlxBa4884yr2SIZrW/Zwf6yUlnAZAM4k4VOlZ1TvKRCPx6Dad6H+UF9crfC/HD8YHBkJTGBLYCMNcEwkrcsp9uPI9Nqf3xSYVvs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770044289; c=relaxed/simple; bh=hSUDMemRVUoY0npdFDPpId4d3LZDbW1Q30SA0hltVEI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RyJtl7krODUi4hkXuEZCn9TxN+r5wA8fKnW/37K13TgYd/r6VDOK1HqnkT+yhxlHvcxXwlmtmOLL87Vmzm2AkHdJHMNemJq4IE56zlJxd75zmNQX4S9f2qbNPfpAk1p6Av3V9NJ7bNBcWnHI0TIyOtcXB2OY27LWhj15at6lzxM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tlDKB6vW; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tlDKB6vW" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 87CE0C116C6; Mon, 2 Feb 2026 14:58:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1770044289; bh=hSUDMemRVUoY0npdFDPpId4d3LZDbW1Q30SA0hltVEI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=tlDKB6vWFEX2IqsSPC6Z+1HN2mjscqjc8033NUTLg20tqdJ1YEXlth+tFXTvVtV86 h7Wqmn6gcWLn2xdERzxUjIqRjLACaUemPcXzq76vBvALGKKjcYH6cor6cmY5hWvMl4 3sJZEGqR1tWSrgEgzC6mIaBrw8zlEqwR3dhjDRUmiN1uHqEApADPpv+MK7fGYlD+RL aqm1i+V5UtXpsU+CsiixFBB3NE0g7SUdeuYoXn/+/hFg5Z+OGjN2rMgtJYSUIWGTaK iCddsG68JjWYLmfUyOENEwzqVhYZH6ZDkfWM+q/s2Rn+mzSy/n6R1yuT1nfmWmhb4I HS6qN4Cc5qKfA== From: Konrad Dybcio Date: Mon, 02 Feb 2026 15:57:35 +0100 Subject: [PATCH RFC 3/8] pinctrl: qcom: Allow exposing reference clocks living in TLMM reg space Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260202-topic-8750_tcsr-v1-3-cd7e6648c64f@oss.qualcomm.com> References: <20260202-topic-8750_tcsr-v1-0-cd7e6648c64f@oss.qualcomm.com> In-Reply-To: <20260202-topic-8750_tcsr-v1-0-cd7e6648c64f@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Taniya Das , Linus Walleij , Melody Olvera , Konrad Dybcio , Taniya Das , Raviteja Laggyshetty , Jishnu Prakash Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Mukesh Ojha , Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770044267; l=5326; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=OhZ2KA92dJ70lXXP48TBPU9L16SvJF50a/3w3QOui6Y=; b=fVkRsrz+nGOZjQaZvb483P6TQrKhcx9av3824ehABeteCt/6FVYFMsDLaZBnF840GD5cKB8BN IJpasMwOkRzAErlLaBLhmIad4tt5ySAZTu3SFpj3/CeoMIU8IYr8gcT X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Certain platforms (at least SM8750) had a number of registers (responsible for gating refclk output to various consumers) moved to TLMM. They're simple on/off toggles. Expose them from the msm-pinctrl driver to allow for a reasonable DT representation. Signed-off-by: Konrad Dybcio --- drivers/pinctrl/qcom/pinctrl-msm.c | 92 ++++++++++++++++++++++++++++++++++= ++++ drivers/pinctrl/qcom/pinctrl-msm.h | 14 ++++++ 2 files changed, 106 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinc= trl-msm.c index e99871b90ab9..1a52431a8605 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -4,6 +4,7 @@ * Copyright (c) 2013, The Linux Foundation. All rights reserved. */ =20 +#include #include #include #include @@ -16,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -80,6 +82,7 @@ struct msm_pinctrl { const struct msm_pinctrl_soc_data *soc; void __iomem *regs[MAX_NR_TILES]; u32 phys_base[MAX_NR_TILES]; + struct ref_clk ref_clks[]; }; =20 #define MSM_ACCESSOR(name) \ @@ -1525,9 +1528,69 @@ SIMPLE_DEV_PM_OPS(msm_pinctrl_dev_pm_ops, msm_pinctr= l_suspend, =20 EXPORT_SYMBOL(msm_pinctrl_dev_pm_ops); =20 +static int clkref_enable(struct clk_hw *hw) +{ + struct ref_clk *rclk =3D container_of(hw, struct ref_clk, hw); + u32 val; + + regmap_write(rclk->regmap, rclk->init.offset, BIT(0)); + udelay(10); + + regmap_read(rclk->regmap, rclk->init.offset, &val); + + return (val & BIT(0)) ? 0 : -EINVAL; +} + +static void clkref_disable(struct clk_hw *hw) +{ + struct ref_clk *rclk =3D container_of(hw, struct ref_clk, hw); + + regmap_write(rclk->regmap, rclk->init.offset, 0); + + udelay(10); +} + +static int clkref_is_enabled(struct clk_hw *hw) +{ + struct ref_clk *rclk =3D container_of(hw, struct ref_clk, hw); + u32 val; + + regmap_read(rclk->regmap, rclk->init.offset, &val); + + return !!val; +} + +static const struct clk_ops clkref_ops =3D { + .enable =3D clkref_enable, + .disable =3D clkref_disable, + .is_enabled =3D clkref_is_enabled, +}; + +static struct clk_hw *msm_pinctrl_clk_get(struct of_phandle_args *clkspec,= void *data) +{ + struct msm_pinctrl *pctrl =3D data; + u32 idx =3D clkspec->args[0]; + + if (idx >=3D pctrl->soc->num_ref_clks) + return ERR_PTR(-EINVAL); + + return &pctrl->ref_clks[idx].hw; +} + +static const struct clk_parent_data clkref_parent_data =3D { + .index =3D 0, /* RPM(h) XO clock */ +}; + +static const struct regmap_config clkref_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, +}; + int msm_pinctrl_probe(struct platform_device *pdev, const struct msm_pinctrl_soc_data *soc_data) { + struct device *dev =3D &pdev->dev; const struct pinfunction *func; struct msm_pinctrl *pctrl; struct resource *res; @@ -1595,6 +1658,35 @@ int msm_pinctrl_probe(struct platform_device *pdev, if (ret) return ret; =20 + if (soc_data->num_ref_clks) { + struct regmap *regmap =3D devm_regmap_init_mmio(dev, pctrl->regs[0], + &clkref_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + for (int i =3D 0; i < soc_data->num_ref_clks; i++) { + struct clk_hw *hw =3D &pctrl->ref_clks[i].hw; + struct clk_init_data init =3D { }; + + init.name =3D pctrl->soc->ref_clks[i]->name; + init.parent_data =3D &clkref_parent_data; + init.num_parents =3D 1; + init.ops =3D &clkref_ops; + hw->init =3D &init; + + ret =3D devm_clk_hw_register(dev, hw); + if (ret) + return dev_err_probe(dev, ret, "Couldn't register clock %s\n", + init.name); + + pctrl->ref_clks[i].regmap =3D regmap; + } + + ret =3D devm_of_clk_add_hw_provider(dev, msm_pinctrl_clk_get, pctrl); + if (ret) + return dev_err_probe(dev, ret, "Couldn't register clk provider\n"); + } + platform_set_drvdata(pdev, pctrl); =20 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinc= trl-msm.h index 4625fa5320a9..213cc789711d 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.h +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -5,6 +5,7 @@ #ifndef __PINCTRL_MSM_H__ #define __PINCTRL_MSM_H__ =20 +#include #include #include =20 @@ -129,6 +130,17 @@ struct msm_gpio_wakeirq_map { unsigned int wakeirq; }; =20 +struct ref_clk_init_data { + const char * const name; + u32 offset; +}; + +struct ref_clk { + struct clk_hw hw; + struct regmap *regmap; + struct ref_clk_init_data init; +}; + /** * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configurat= ion * @pins: An array describing all pins the pin controller affects. @@ -170,6 +182,8 @@ struct msm_pinctrl_soc_data { bool wakeirq_dual_edge_errata; unsigned int gpio_func; unsigned int egpio_func; + const struct ref_clk_init_data **ref_clks; + unsigned int num_ref_clks; }; =20 extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops; --=20 2.52.0