From nobody Mon Feb 9 16:02:45 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D33C364E85; Mon, 2 Feb 2026 14:58:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770044284; cv=none; b=WTdVpd6YwP7LdO3kyJJlx50IftxncU2dsZAwOV0XXkzTLtyCgjxb2K5hNKg1+Pkd3WILsaVq/faK3NAkpMCxRCcRnGcswn1rVZ3EHqxj1naR6PyapBspIzHeAVpN8HDq0W+ZIaO/LIjVbbA3vVp2f3rsdrEWy9i4utvaTvmA5CE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770044284; c=relaxed/simple; bh=WrkE3KnR40Jr7WeldZUrKrhOpgORxGxgXjF8DyMvuYU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lIAM9YKp/v8h2keohxv1d+6sdlrTnEp0n/2OZIXeau5JeyuISoBW4xE+FClAsm0NQ1Q2CYOipGDvqfZvZUOkeINM0ZYoZEDSrnkFoI0OUhTbZN592g1ucHNk0Eh/FqzE8fShJRrBM4wN6rQ8Fk/AMZvw/CJlJtrROiMSkn8vcxc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Fy4ONN/f; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Fy4ONN/f" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 335E9C2BC86; Mon, 2 Feb 2026 14:57:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1770044284; bh=WrkE3KnR40Jr7WeldZUrKrhOpgORxGxgXjF8DyMvuYU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Fy4ONN/fpGvBWY25CjSYLBcttWtqDCnUeA+Fdzbt044Q6kfOKyw6u0CDgY08IhMgk bGfmlNHQAuramvFL7O17d1EqI+gLr2BwvKz1AbPkuO84E6DAMbPim2O0HkL4CEosKH uuuEZS12ay+1wxHjxY3+GyAPxodmvnsai9Tf4XVLZYscjtj5nyZ2YR0IQJkk9nt5js gbg0vS4iU2j4v3F2Yn89MmwPUvVlm83IvWQVGfAPc7UnMnhedZOGQY7hnwihq3DcY+ hECbYFGi0S3c9UB6scdEVt65Fu18NywBPMhb+wA0PDxEsrGU8GSCxooB5fq+eIpKUq zoTnRegw+EPzg== From: Konrad Dybcio Date: Mon, 02 Feb 2026 15:57:34 +0100 Subject: [PATCH RFC 2/8] dt-bindings: pinctrl: qcom,sm8750-tlmm: Allow clocks/clock-cells Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260202-topic-8750_tcsr-v1-2-cd7e6648c64f@oss.qualcomm.com> References: <20260202-topic-8750_tcsr-v1-0-cd7e6648c64f@oss.qualcomm.com> In-Reply-To: <20260202-topic-8750_tcsr-v1-0-cd7e6648c64f@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Taniya Das , Linus Walleij , Melody Olvera , Konrad Dybcio , Taniya Das , Raviteja Laggyshetty , Jishnu Prakash Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Mukesh Ojha , Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770044267; l=1823; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=B4OvKogN/7PqKBfyCbBZSMrA7mnCwm2FZc2lYzaJU7o=; b=7WYFQhCF9wMdpqhNa1cTXR1jPgwxcQmMteNRj0rPhPzZRvw5150gNl4VvK/gtVr8O4+RUi9fX 8vvRfvxRLS7BLxsZX2aSrNE/b5VLag8UwHllajufFiHjNhiZHWYW1ln X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio On SM8750 specifically, the TLMM block register space contains a number of gates that forward the system XO (reference) clock to various IP blocks. Allow '#clock-cells' (since it provides clocks) and 'clocks' (so that the parent clock may be consumed and linked with the clocks provided). Signed-off-by: Konrad Dybcio --- .../devicetree/bindings/pinctrl/qcom,sm8750-tlmm.yaml | 12 ++++++++= ++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8750-tlmm.yam= l b/Documentation/devicetree/bindings/pinctrl/qcom,sm8750-tlmm.yaml index 7aecc97745a8..136366d89290 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8750-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8750-tlmm.yaml @@ -19,6 +19,10 @@ properties: compatible: const: qcom,sm8750-tlmm =20 + clocks: + items: + - description: RPMh XO clock + reg: maxItems: 1 =20 @@ -32,6 +36,9 @@ properties: gpio-line-names: maxItems: 215 =20 + '#clock-cells': + const: 1 + patternProperties: "-state$": oneOf: @@ -100,6 +107,8 @@ $defs: required: - compatible - reg + - clocks + - '#clock-cells' =20 unevaluatedProperties: false =20 @@ -109,6 +118,7 @@ examples: tlmm: pinctrl@f100000 { compatible =3D "qcom,sm8750-tlmm"; reg =3D <0x0f100000 0x300000>; + clocks =3D <&rpmhcc_xo>; gpio-controller; #gpio-cells =3D <2>; gpio-ranges =3D <&tlmm 0 0 216>; @@ -116,6 +126,8 @@ examples: #interrupt-cells =3D <2>; interrupts =3D ; =20 + #clock-cells =3D <1>; + gpio-wo-state { pins =3D "gpio1"; function =3D "gpio"; --=20 2.52.0