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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b8283def01sm417499eec.34.2026.02.02.22.06.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Feb 2026 22:06:40 -0800 (PST) From: Jingyi Wang Date: Mon, 02 Feb 2026 22:06:26 -0800 Subject: [PATCH v5 09/10] arm64: dts: qcom: kaanapali: Add support for MM clock controllers for Kaanapali Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260202-knp-dts-misc-v5-9-02de82bf9901@oss.qualcomm.com> References: <20260202-knp-dts-misc-v5-0-02de82bf9901@oss.qualcomm.com> In-Reply-To: <20260202-knp-dts-misc-v5-0-02de82bf9901@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jingyi Wang , 20260114-knp-remoteproc-v4-0-fcf0b04d01af@oss.qualcomm.com, Taniya Das , Konrad Dybcio , Abel Vesa X-Mailer: b4 0.15-dev-3d134 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770098787; l=4559; i=jingyi.wang@oss.qualcomm.com; s=20250911; h=from:subject:message-id; bh=V8klYJcTlCA0XXPc7b6wczy0KpOL9nFdZCIXVz7dVR8=; b=FKKu39p50DwCp0ka35XVW2kfs65wOudb7bNZhS2NB7BqFTW6s/K6lfOyY99F3hXL0WS/P29g4 62OObZZ1szPBD9mU1qwtgKuRd2Mb/N14tkPvHflXQp43OGSdY01sSPY X-Developer-Key: i=jingyi.wang@oss.qualcomm.com; a=ed25519; pk=PSoHZ6KbUss3IW8FPRVMHMK0Jkkr/jV347mBYJO3iLo= X-Proofpoint-ORIG-GUID: ZeCkoPnudGzl1OBMIpgHaIV2eELYM2aW X-Authority-Analysis: v=2.4 cv=dcmNHHXe c=1 sm=1 tr=0 ts=69819072 cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=Y3HLYP14RHR0fgYgac8A:9 a=QEXdDO2ut3YA:10 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-GUID: ZeCkoPnudGzl1OBMIpgHaIV2eELYM2aW X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjAzMDA0NyBTYWx0ZWRfXxMJDOKG0kwot xkgqaKxzTYaxG4VLACOvfbJTVBVgVHKwmAgJ6baHAx97AfWSbSE9yL3k5jETD//Z4ONEQQG+mOB AsHsNqCz5zxVe2Rf+sXyNj7xwMmeliMbsCXAHoHxdoWtKbtp2EOsi/LPqC8Ip60qe5boGl0YPpD YQ/+zOBJpRqNKQjB1cNK9ZwbdfDYy1DenyuQ1uz8+ZewKXsDcfkOcYyrgjk/bFwRZAKGhUFN3/G 8mN82mkt1jsXI6rK140sGIrlpqwPeizSWG2MZtJG+SpHXr/SdJEEDxx6jZe1KidxduDXJz6sGwM e0QXye9yDUZP8NVC5NRtaSKv9ATj6DQjL6vw1nOOdeHnXguaSpzkMMTRYq50ru2GnAlzM9l82PU xgXAsBCPSOR8E9uJsO5gNZWuJlyau9dhZunuz3eIoWSk5HWqTRLzkdKrRwktz0aiPmkxUuW9Y36 vn/9lry1nTXf//9HSRg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-03_01,2026-02-02_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602030047 From: Taniya Das Add the device nodes for the multimedia clock controllers (cambistmclkcc, camcc, dispcc, videocc, gpucc and gxclkctl). Signed-off-by: Taniya Das Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 111 ++++++++++++++++++++++++++++= ++++ 1 file changed, 111 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/= qcom/kaanapali.dtsi index 050d47691f5c..08d098c1f5af 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -3,7 +3,13 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ =20 +#include +#include +#include #include +#include +#include +#include #include #include #include @@ -1557,6 +1563,24 @@ aggre_noc: interconnect@16e0000 { <&rpmhcc RPMH_IPA_CLK>; }; =20 + cambistmclkcc: clock-controller@1760000 { + compatible =3D "qcom,kaanapali-cambistmclkcc"; + reg =3D <0x0 0x01760000 0x0 0x8000>; + + clocks =3D <&gcc GCC_CAM_BIST_MCLK_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MX>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + mmss_noc: interconnect@1780000 { compatible =3D "qcom,kaanapali-mmss-noc"; reg =3D <0x0 0x01780000 0x0 0x5b800>; @@ -2532,6 +2556,46 @@ tcsr: clock-controller@1fc0000 { #reset-cells =3D <1>; }; =20 + videocc: clock-controller@20f0000 { + compatible =3D "qcom,kaanapali-videocc"; + reg =3D <0x0 0x020f0000 0x0 0x10000>; + clocks =3D <&bi_tcxo_div2>, + <&gcc GCC_VIDEO_AHB_CLK>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + gxclkctl: clock-controller@3d64000 { + compatible =3D "qcom,kaanapali-gxclkctl"; + reg =3D <0x0 0x03d64000 0x0 0x6000>; + + power-domains =3D <&rpmhpd RPMHPD_GFX>, + <&rpmhpd RPMHPD_GMXC>, + <&gpucc GPU_CC_CX_GDSC>; + + #power-domain-cells =3D <1>; + }; + + gpucc: clock-controller@3d90000 { + compatible =3D "qcom,kaanapali-gpucc"; + reg =3D <0x0 0x03d90000 0x0 0x9800>; + + clocks =3D <&bi_tcxo_div2>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + remoteproc_adsp: remoteproc@6800000 { compatible =3D "qcom,kaanapali-adsp-pas", "qcom,sm8550-adsp-pas"; reg =3D <0x0 0x06800000 0x0 0x10000>; @@ -3073,6 +3137,53 @@ opp-202000000 { }; }; =20 + camcc: clock-controller@956d000 { + compatible =3D "qcom,kaanapali-camcc"; + reg =3D <0x0 0x0956d000 0x0 0x80000>; + + clocks =3D <&gcc GCC_CAMERA_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + dispcc: clock-controller@9ba2000 { + compatible =3D "qcom,kaanapali-dispcc"; + reg =3D <0x0 0x09ba2000 0x0 0x20000>; + clocks =3D <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&gcc GCC_DISP_AHB_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + + #clock-cells =3D <1>; + #power-domain-cells =3D <1>; + #reset-cells =3D <1>; + }; + pdc: interrupt-controller@b220000 { compatible =3D "qcom,kaanapali-pdc", "qcom,pdc"; reg =3D <0x0 0x0b220000 0x0 0x10000>, --=20 2.25.1