From nobody Mon Feb 9 13:57:18 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4AD836CDEB for ; Tue, 3 Feb 2026 06:06:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770098800; cv=none; b=dEuCYupVH8/m71G7FTHm5VV97U7PmWaKAG0EqxNRthhjW9g+Jgrg6jNrONcVsBJzVLIbesybZqlNiyYpKm2heQGvXYR8HdpQ5S2vYyqbeCCU6hRcR3A826kvrUdvTYzaOtXL7Dz++9AbpiiMj0hYt9/gCp6S0OjUYObvMzzI/UY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770098800; c=relaxed/simple; bh=eH8r2OJtMCYgllI4zHwUIcr1LC1eoaIGEiyIlXtdVqQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NbUfqyFzYCcctmG/GYTIrfjiy1e0dRxerdJLW+0bsCjm+U65TvAnII3MHQBX58GF7EYVdFyxLaDSVy8DWqp4P9I/EOgTMup5umraQ+QJNDSSdO+aFs1y5lm0BhIyTIfgKjSX0+6jGuHDHwFDp2d3Sh/5YZkCoyy+TYuIcMbRDSk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=JiGN8f5w; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=YcInYlB3; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="JiGN8f5w"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="YcInYlB3" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6135apZu2262003 for ; Tue, 3 Feb 2026 06:06:37 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= XMQvaYxNBv7Uq72KbDA4JI6fY2h7Ap5Ef7mb2dwbHdY=; b=JiGN8f5wfiXqxaxc uM9Tab49hH3rw3vaL8xvGtUPceGhYacE/at1w5qW1Rn13cs7e+CiLeLp35cRyUED EUxAULs5TAP9FMNsAWBFNSnW/4gnqIoVl2CMDLugyPpvilfrAa9KFFBmgc3y9fwp NMOCJRdhOk/1CERliNTRUd1fbYtghvzdGy6DaNpkJV+WsVIH2mkuXw5TH93mSxKU L0V9L+mQgpf93jaC2uYCKoYWgV8TcbdUSa9fQEXRDUVwohLT4X1FYmZqWynkLEEJ 1ppT42ZasCxGL5qXavIZbNh1+X9di1TsGZsxEa92LPDoIStLmOB6nQAvFSD+agVp Lc2fQg== Received: from mail-dl1-f70.google.com (mail-dl1-f70.google.com [74.125.82.70]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4c2tmtk3um-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 03 Feb 2026 06:06:36 +0000 (GMT) Received: by mail-dl1-f70.google.com with SMTP id a92af1059eb24-124a95b6f61so14625937c88.0 for ; Mon, 02 Feb 2026 22:06:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1770098796; x=1770703596; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=XMQvaYxNBv7Uq72KbDA4JI6fY2h7Ap5Ef7mb2dwbHdY=; b=YcInYlB3Y4TMePTQN3kq54TWnQ9WTXPapfAEe5fIvy4W8wNr002MxoWZ0BwwCnKsV0 eE7uYx7dXOJh2uRtI+iCJJDuXmEg1bQsFjKJAn8nc3TmDj337IH6WS3D0c/TjimCCuyC yEJCaDx8cfQ9YrHJuaicpibgFsXG1Aq0UuNMPlDlh9upnzc59rzOhfQBcFycVsPOaknT VqdgVB4sFdNjAPkE+/TEyLB/4ZAdags8iZbWPoN0d8L9g3LI5KYzDj4HWIPAgtF69vWT OfjfH+HzIX32vtDQsZik/4x1S8uRivojSWPwwyzfFvESp2RYr+Pp8qC4C5DhnHZMuEbK rm7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770098796; x=1770703596; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=XMQvaYxNBv7Uq72KbDA4JI6fY2h7Ap5Ef7mb2dwbHdY=; b=Atvz0U37nL9Q5MFObl2pAGdNtx27RpIzt9X3hCuSSPh0vYJxU5PS+fo5uA8DwHXVww Mr/7fCioVkrtefegP35BY7fuyUndhSBm8RKt0dO5lLRStA41XWdNks2duTcxdtwoxXsc 9831zfHCcQRV1LiGdawAa9poTm2ox4M/B1UAY0dltJMupN3lbXh0wsXmclssa5VgP6DI jaqCqPwRG///4tlE7OEbPZYpvhUKcjXSRqtMcN3v3bJgusoTqinubFF5vZh6qHDEM4hq S/7hrM72MszpH2rj3dNE30aERvRo44Osjjy7Fw7MGxxGeW4VmbeA7kdK8WNFYl6quPhN rSDA== X-Forwarded-Encrypted: i=1; AJvYcCV/TJ6bRy4icHUD0iWskNSTMJ7kMikw1IadytzXPLZ2y7L5LOjy5vr7upXOj61Ne9tGxzA7na+/xuJTQv8=@vger.kernel.org X-Gm-Message-State: AOJu0Ywmk2wOIH/F7bZfqd9xF5uDa3hiX1vWjWx2LFiQ7IRjoLAtWY+D rFAsWTV0UbIErmVraq5DNny6thZmbTlbnqiz+EuYkNnfzq8vARA529rqzhi1IsBBt7QtQyidnpw iYIHBa8b9YdLNStTvGZzDTN07AjyJH94yo3yqje/b1ujNkYh1RVBpSJSy5pQ7fRyAGWs= X-Gm-Gg: AZuq6aIQRY9TFN/T9JmntzPo4DvkwoZJO7wswU6uSDsnYdsyLkCHbSKHSHEfr3r1IlG eMY1XUPl0Rz7Ls3nlWwquVKBsS2p/d+a3dwIgZ5XpoZAlQoNQv6et+7/hlxmRG35woV971LiKKE DrLwBDJHdbA/CE6QV0pGoNGZ1cWS0KjlCLiW56pPzlE07yrcIWbK20Tp/wuKPidM2KbQKN8g5tc 1BzdAxBID3z+zT9tyKCmjC1g43fM8bdrjHcT4cpG+CFawuX8mvr2J/jEJnaHQPBXr4RzcPd7afs gYYdWNnxZNaJlkF3UBvOLxVtsJcWBt7WpngVcGcIgJ0gUho1MLqMX2HXXjdO+B67zKh7e5SkZHn FqejavFnaQjXZL8RIINY6EdBWyTDloDKPm3ex5vVzBrI1pcjSPJNkPOPzt4EQ X-Received: by 2002:a05:7022:660a:b0:122:153:d161 with SMTP id a92af1059eb24-125c0fa713cmr7051323c88.17.1770098795685; Mon, 02 Feb 2026 22:06:35 -0800 (PST) X-Received: by 2002:a05:7022:660a:b0:122:153:d161 with SMTP id a92af1059eb24-125c0fa713cmr7051302c88.17.1770098795053; Mon, 02 Feb 2026 22:06:35 -0800 (PST) Received: from hu-jingyw-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b8283def01sm417499eec.34.2026.02.02.22.06.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Feb 2026 22:06:34 -0800 (PST) From: Jingyi Wang Date: Mon, 02 Feb 2026 22:06:22 -0800 Subject: [PATCH v5 05/10] arm64: dts: qcom: kaanapali: Add support for audio Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260202-knp-dts-misc-v5-5-02de82bf9901@oss.qualcomm.com> References: <20260202-knp-dts-misc-v5-0-02de82bf9901@oss.qualcomm.com> In-Reply-To: <20260202-knp-dts-misc-v5-0-02de82bf9901@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jingyi Wang , 20260114-knp-remoteproc-v4-0-fcf0b04d01af@oss.qualcomm.com, Prasad Kumpatla , Konrad Dybcio , Abel Vesa X-Mailer: b4 0.15-dev-3d134 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770098787; l=13571; i=jingyi.wang@oss.qualcomm.com; s=20250911; h=from:subject:message-id; bh=FN/C0JgEfkUGxO0ScMaU8W8gbfqsrDP9YrR20hfWJV8=; b=quNaBUhSPaHVTraGSoJUM3poyJAiCqmvT6ueTfDsTPt7C5GEtQ6ERNoohOca555O5KNOvdmIU We0xL6bx3TaCqG9f45KRUCQY0PG8TpYjndAe2jWNDRPTP7FVm6V/oeD X-Developer-Key: i=jingyi.wang@oss.qualcomm.com; a=ed25519; pk=PSoHZ6KbUss3IW8FPRVMHMK0Jkkr/jV347mBYJO3iLo= X-Authority-Analysis: v=2.4 cv=Xb6EDY55 c=1 sm=1 tr=0 ts=6981906c cx=c_pps a=SvEPeNj+VMjHSW//kvnxuw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=fOvlSJoLLuNaJOMVFRMA:9 a=QEXdDO2ut3YA:10 a=Kq8ClHjjuc5pcCNDwlU0:22 X-Proofpoint-ORIG-GUID: Mh4ZT63NybfALOvSy7DAtuuYBFBCbvL1 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjAzMDA0NyBTYWx0ZWRfX99AQnuOGE5uO CLDGugfltWpxFZLEw0bqF2KJPpKbLV0I1fqE7KmysRtphcRAzidm4RmAcY5hOa59i/LsWxgUGpu qPkf4l/b6Vl9/mQXKAVnSLB5IMK2Pg79N7DQ2Y0X8hb3XijnkwyMNZoujSyjVm3ujh3vWJyG4pQ 71tYHhqGGYQcUaA8hwV8VzvnJVNMuM38tkct382kafNvzxmDvv2AZZvHO/xWIuYCWnViuyGzZAb KvjTch7VmOYtAQUgf+h8zDSO4Bo/CJUvT/2zkH9YjYcNPwboXSzHjyEO0pbzXLK6yMFaBtVqz0Q 8AOczSPVe5e1x1YPB3/6F3kHSsz4tNnXEaZAkBF1gJkX3QjvL7tMa96MiUG8VN7bEA6hAXynQpI hq1aQa8egg+HW+Wh0s/ePYZMQLf0yV+qNO5XCxjL/zPRobHSCQOY6uVUYIZRQSoAOrJjIcs/MQW 4rk7GGhHncp3UerbPzw== X-Proofpoint-GUID: Mh4ZT63NybfALOvSy7DAtuuYBFBCbvL1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-03_01,2026-02-02_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 phishscore=0 adultscore=0 suspectscore=0 bulkscore=0 impostorscore=0 malwarescore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602030047 From: Prasad Kumpatla Introduce audio support for Kaanapali SoC by adding LPASS macro codecs, TLMM pin controller and SoundWire controller with similar hardware implementation to SM8750 platform. Also add GPR (Generic Pack Router) node along with support for APM (Audio Process Manager) and PRM (Proxy Resource Manager) audio services. Signed-off-by: Prasad Kumpatla Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 367 ++++++++++++++++++++++++++++= ++++ 1 file changed, 367 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/= qcom/kaanapali.dtsi index c8f61200f261..050d47691f5c 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -16,7 +16,9 @@ #include #include #include +#include #include +#include =20 #include "kaanapali-ipcc.h" =20 @@ -2632,6 +2634,371 @@ compute-cb@7 { dma-coherent; }; }; + + gpr { + compatible =3D "qcom,gpr"; + qcom,glink-channels =3D "adsp_apps"; + qcom,domain =3D ; + qcom,intents =3D <512 20>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + q6apm: service@1 { + compatible =3D "qcom,q6apm"; + reg =3D ; + #sound-dai-cells =3D <0>; + qcom,protection-domain =3D "avs/audio", + "msm/adsp/audio_pd"; + + q6apmbedai: bedais { + compatible =3D "qcom,q6apm-lpass-dais"; + #sound-dai-cells =3D <1>; + }; + + q6apmdai: dais { + compatible =3D "qcom,q6apm-dais"; + iommus =3D <&apps_smmu 0x1001 0x80>, + <&apps_smmu 0x1041 0x20>; + }; + }; + + q6prm: service@2 { + compatible =3D "qcom,q6prm"; + reg =3D ; + qcom,protection-domain =3D "avs/audio", + "msm/adsp/audio_pd"; + + q6prmcc: clock-controller { + compatible =3D "qcom,q6prm-lpass-clocks"; + #clock-cells =3D <2>; + }; + }; + }; + }; + }; + + lpass_wsa2macro: codec@6aa0000 { + compatible =3D "qcom,kaanapali-lpass-wsa-macro", + "qcom,sm8550-lpass-wsa-macro"; + reg =3D <0x0 0x06aa0000 0x0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names =3D "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells =3D <0>; + clock-output-names =3D "wsa2-mclk"; + #sound-dai-cells =3D <1>; + }; + + swr3: soundwire@6ab0000 { + compatible =3D "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0"; + reg =3D <0 0x06ab0000 0 0x10000>; + interrupts =3D ; + clocks =3D <&lpass_wsa2macro>; + clock-names =3D "iface"; + label =3D "WSA2"; + + pinctrl-0 =3D <&wsa2_swr_active>; + pinctrl-names =3D "default"; + + qcom,din-ports =3D <4>; + qcom,dout-ports =3D <9>; + + qcom,ports-sinterval =3D /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18= f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; + qcom,ports-offset1 =3D /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0x= ff 0xff 0x06 0x0d 0xff 0x00>; + qcom,ports-offset2 =3D /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0x= ff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xf= f 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff= 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-word-length =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08= 0xff 0xff 0xff 0xff 0xff 0x18>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 = 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff 0xff 0xff 0xff 0xff>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + #sound-dai-cells =3D <1>; + status =3D "disabled"; + }; + + lpass_rxmacro: codec@6ac0000 { + compatible =3D "qcom,kaanapali-lpass-rx-macro", "qcom,sm8550-lpass-rx-m= acro"; + reg =3D <0x0 0x06ac0000 0x0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names =3D "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells =3D <0>; + clock-output-names =3D "mclk"; + #sound-dai-cells =3D <1>; + }; + + swr1: soundwire@6ad0000 { + compatible =3D "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0"; + reg =3D <0 0x06ad0000 0 0x10000>; + interrupts =3D ; + clocks =3D <&lpass_rxmacro>; + clock-names =3D "iface"; + label =3D "RX"; + + pinctrl-0 =3D <&rx_swr_active>; + pinctrl-names =3D "default"; + + qcom,din-ports =3D <1>; + qcom,dout-ports =3D <11>; + + qcom,ports-sinterval =3D /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xf= f 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-offset1 =3D /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0x= ff 0xff 0xff 0xff 0xff>; + qcom,ports-offset2 =3D /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0x= ff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xf= f 0xff 0xff 0xff 0xff>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff= 0xff 0xff 0xff 0xff>; + qcom,ports-word-length =3D /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff= 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 = 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x0= 0 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xf= f 0xff 0xff 0xff 0xff 0xff>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + #sound-dai-cells =3D <1>; + status =3D "disabled"; + }; + + lpass_txmacro: codec@6ae0000 { + compatible =3D "qcom,kaanapali-lpass-tx-macro", "qcom,sm8550-lpass-tx-m= acro"; + reg =3D <0x0 0x06ae0000 0x0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUP= LE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names =3D "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells =3D <0>; + clock-output-names =3D "mclk"; + #sound-dai-cells =3D <1>; + }; + + lpass_wsamacro: codec@6b00000 { + compatible =3D "qcom,kaanapali-lpass-wsa-macro", + "qcom,sm8550-lpass-wsa-macro"; + reg =3D <0x0 0x06b00000 0x0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names =3D "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells =3D <0>; + clock-output-names =3D "mclk"; + #sound-dai-cells =3D <1>; + }; + + swr0: soundwire@6b10000 { + compatible =3D "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0"; + reg =3D <0 0x06b10000 0 0x10000>; + interrupts =3D ; + clocks =3D <&lpass_wsamacro>; + clock-names =3D "iface"; + label =3D "WSA"; + + pinctrl-0 =3D <&wsa_swr_active>; + pinctrl-names =3D "default"; + + qcom,din-ports =3D <4>; + qcom,dout-ports =3D <9>; + + qcom,ports-sinterval =3D /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18= f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; + qcom,ports-offset1 =3D /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0x= ff 0xff 0x06 0x0d 0xff 0x00>; + qcom,ports-offset2 =3D /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0x= ff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xf= f 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff= 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-word-length =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08= 0xff 0xff 0xff 0xff 0xff 0x18>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 = 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff 0xff 0xff 0xff 0xff>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + #sound-dai-cells =3D <1>; + status =3D "disabled"; + }; + + swr2: soundwire@7630000 { + compatible =3D "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0"; + reg =3D <0 0x07630000 0 0x10000>; + interrupts-extended =3D <&intc GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 40 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "core", "wakeup"; + clocks =3D <&lpass_txmacro>; + clock-names =3D "iface"; + label =3D "TX"; + + pinctrl-0 =3D <&tx_swr_active>; + pinctrl-names =3D "default"; + + qcom,din-ports =3D <4>; + qcom,dout-ports =3D <0>; + qcom,ports-sinterval-low =3D /bits/ 8 <0x01 0x01 0x03 0x03>; + qcom,ports-offset1 =3D /bits/ 8 <0x00 0x00 0x01 0x01>; + qcom,ports-offset2 =3D /bits/ 8 <0x00 0x00 0x00 0x00>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-word-length =3D /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0x01 0x02 0x00 0x00>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + #sound-dai-cells =3D <1>; + status =3D "disabled"; + }; + + lpass_vamacro: codec@7660000 { + compatible =3D "qcom,kaanapali-lpass-va-macro", "qcom,sm8550-lpass-va-m= acro"; + reg =3D <0 0x07660000 0 0x2000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUP= LE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names =3D "mclk", "macro", "dcodec"; + + #clock-cells =3D <0>; + clock-output-names =3D "fsgen"; + #sound-dai-cells =3D <1>; + }; + + lpass_tlmm: pinctrl@7760000 { + compatible =3D "qcom,sm8750-lpass-lpi-pinctrl", + "qcom,sm8650-lpass-lpi-pinctrl"; + reg =3D <0 0x07760000 0 0x20000>; + + clocks =3D <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names =3D "core", "audio"; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&lpass_tlmm 0 0 23>; + + tx_swr_active: tx-swr-active-state { + clk-pins { + pins =3D "gpio0"; + function =3D "swr_tx_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio1", "gpio2", "gpio14"; + function =3D "swr_tx_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + rx_swr_active: rx-swr-active-state { + clk-pins { + pins =3D "gpio3"; + function =3D "swr_rx_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio4", "gpio5"; + function =3D "swr_rx_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + dmic01_default: dmic01-default-state { + clk-pins { + pins =3D "gpio6"; + function =3D "dmic1_clk"; + drive-strength =3D <8>; + output-high; + }; + + data-pins { + pins =3D "gpio7"; + function =3D "dmic1_data"; + drive-strength =3D <8>; + input-enable; + }; + }; + + dmic23_default: dmic23-default-state { + clk-pins { + pins =3D "gpio8"; + function =3D "dmic2_clk"; + drive-strength =3D <8>; + output-high; + }; + + data-pins { + pins =3D "gpio9"; + function =3D "dmic2_data"; + drive-strength =3D <8>; + input-enable; + }; + }; + + wsa_swr_active: wsa-swr-active-state { + clk-pins { + pins =3D "gpio10"; + function =3D "wsa_swr_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio11"; + function =3D "wsa_swr_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + wsa2_swr_active: wsa2-swr-active-state { + clk-pins { + pins =3D "gpio15"; + function =3D "wsa2_swr_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio16"; + function =3D "wsa2_swr_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; }; }; =20 --=20 2.25.1