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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b8283def01sm417499eec.34.2026.02.02.22.06.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Feb 2026 22:06:29 -0800 (PST) From: Jingyi Wang Date: Mon, 02 Feb 2026 22:06:18 -0800 Subject: [PATCH v5 01/10] arm64: dts: qcom: kaanapali: add coresight nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260202-knp-dts-misc-v5-1-02de82bf9901@oss.qualcomm.com> References: <20260202-knp-dts-misc-v5-0-02de82bf9901@oss.qualcomm.com> In-Reply-To: <20260202-knp-dts-misc-v5-0-02de82bf9901@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jingyi Wang , 20260114-knp-remoteproc-v4-0-fcf0b04d01af@oss.qualcomm.com, Jie Gan , Konrad Dybcio , Abel Vesa X-Mailer: b4 0.15-dev-3d134 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770098787; l=23499; i=jingyi.wang@oss.qualcomm.com; s=20250911; h=from:subject:message-id; bh=prYMCbFhtJWKvpHLod3UOeIGs03j5Ip2+BricOoj6iE=; b=s50pW7iREJ6VqGB5TR5znmjzCG6T6bbLMlFi/JIdAVEJil19+sZDPaUTTqEkqk00J2sQS/mlY xm9OqeI4+jABSELjztPYJRtnmSONYwsETCdIyJua+HGeVMlwRyaBLgt X-Developer-Key: i=jingyi.wang@oss.qualcomm.com; a=ed25519; pk=PSoHZ6KbUss3IW8FPRVMHMK0Jkkr/jV347mBYJO3iLo= X-Authority-Analysis: v=2.4 cv=TaebdBQh c=1 sm=1 tr=0 ts=69819067 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=7UlbJtpOWuNyX1kucuYA:9 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-GUID: U9nC6DmNP9onXUVsdZoTyL2ANEcK3nSt X-Proofpoint-ORIG-GUID: U9nC6DmNP9onXUVsdZoTyL2ANEcK3nSt X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjAzMDA0NyBTYWx0ZWRfX4X4pPX8xL76p wyB+JmgF4Hr75CCmHhatSmV1Ph77wD0t8gwL2wfOulh2hXT1vHCbwM0L7IinYDgYbWJoxitm+ni 3pBLCimYVoyOwkldS2edO2tX3gH+xNaul+RGODXvg/XkOzPd1O8A8GNYV7t7txu58xxoX/oll2/ fz3qtcoPrdvpLs3u+DxMUsrt+5XILOG9kvvIczl2t907kVcg9ALeFf+E6igxKO+tduCw8bgaSPW ZGH8XCPOBmZBFcWEYM/GkD0p+ZHtFTYFKyDyrR4viotdJwOWalQcom7yFjivfYdnK2YfpwAzTOj sL+2LdYmq2aYFKKrk1UAvaDcyITYof08UtpVkEBf3B0/RX8J4JNIcDOueTNIcOYv9fnmUHRsXHI lfJ6Xp/nW4l+zEmGsJr/GpKIyQrTel6NdX1ER+68epAm0fvNSmHv/DaH4gm2Cb8HMzrroginh2W 4zCiBwz2hoFnia7wHcw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-03_01,2026-02-02_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602030047 From: Jie Gan Add CoreSight nodes to enable trace paths such as TPDM->ETF and STM->ETF. These devices are part of the AOSS, CDSP, QDSS, modem and some small subsystems, such as DCC, GCC, ipcc and so on. Signed-off-by: Jie Gan Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 1160 +++++++++++++++++++++++++++= ++++ 1 file changed, 1160 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/= qcom/kaanapali.dtsi index 9ef57ad0ca71..6e231850d5d6 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -1080,6 +1080,1114 @@ card-detect-pins { }; }; =20 + stm@10002000 { + compatible =3D "arm,coresight-stm", "arm,primecell"; + reg =3D <0x0 0x10002000 0x0 0x1000>, + <0x0 0x16280000 0x0 0x180000>; + reg-names =3D "stm-base", + "stm-stimulus-base"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint =3D <&funnel_in0_in7>; + }; + }; + }; + }; + + tpdm@10003000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x10003000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <32>; + + out-ports { + port { + tpdm_dcc_out: endpoint { + remote-endpoint =3D <&tpda_qdss_in0>; + }; + }; + }; + }; + + tpda@10004000 { + compatible =3D "qcom,coresight-tpda", "arm,primecell"; + reg =3D <0x0 0x10004000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + tpda_qdss_in0: endpoint { + remote-endpoint =3D <&tpdm_dcc_out>; + }; + }; + + port@1 { + reg =3D <1>; + + tpda_qdss_in1: endpoint { + remote-endpoint =3D <&tpdm_spdm_out>; + }; + }; + }; + + out-ports { + port { + tpda_qdss_out: endpoint { + remote-endpoint =3D <&funnel_in0_in6>; + }; + }; + }; + }; + + tpdm@1000f000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x1000f000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <32>; + + out-ports { + port { + tpdm_spdm_out: endpoint { + remote-endpoint =3D <&tpda_qdss_in1>; + }; + }; + }; + }; + + funnel@10041000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + reg =3D <0x0 0x10041000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + funnel_in0_in0: endpoint { + remote-endpoint =3D <&tn_ag_out>; + }; + }; + + port@6 { + reg =3D <6>; + + funnel_in0_in6: endpoint { + remote-endpoint =3D <&tpda_qdss_out>; + }; + }; + + port@7 { + reg =3D <7>; + + funnel_in0_in7: endpoint { + remote-endpoint =3D <&stm_out>; + }; + }; + }; + + out-ports { + port { + funnel_in0_out: endpoint { + remote-endpoint =3D <&funnel_aoss_in6>; + }; + }; + }; + }; + + tpdm@11000000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11000000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-element-bits =3D <32>; + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + tpdm_modem0_out: endpoint { + remote-endpoint =3D <&tpda_modem_in0>; + }; + }; + }; + }; + + tpda@11004000 { + compatible =3D "qcom,coresight-tpda", "arm,primecell"; + reg =3D <0x0 0x11004000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + tpda_modem_in0: endpoint { + remote-endpoint =3D <&tpdm_modem0_out>; + }; + }; + + port@1 { + reg =3D <1>; + + tpda_modem_in1: endpoint { + remote-endpoint =3D <&tpdm_modem1_out>; + }; + }; + + port@2 { + reg =3D <2>; + + tpda_modem_in2: endpoint { + remote-endpoint =3D <&tpdm_modem2_out>; + }; + }; + }; + + out-ports { + port { + tpda_modem_out: endpoint { + remote-endpoint =3D <&funnel_modem_dl_in0>; + }; + }; + }; + }; + + funnel@11005000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + reg =3D <0x0 0x11005000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + port { + funnel_modem_dl_in0: endpoint { + remote-endpoint =3D <&tpda_modem_out>; + }; + }; + }; + + out-ports { + port { + funnel_modem_dl_out: endpoint { + remote-endpoint =3D <&tn_ag_in13>; + }; + }; + }; + }; + + tpdm@1102c000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x1102c000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + tpdm_gcc_out: endpoint { + remote-endpoint =3D <&tn_ag_in17>; + }; + }; + }; + }; + + tpdm@11180000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11180000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-element-bits =3D <32>; + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + tpdm_cdsp_out: endpoint { + remote-endpoint =3D <&tpda_cdsp_in0>; + }; + }; + }; + }; + + tpdm@11183000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11183000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-element-bits =3D <32>; + qcom,cmb-element-bits =3D <32>; + + out-ports { + port { + tpdm_cdsp_cmsr1_out: endpoint { + remote-endpoint =3D <&tpda_cdsp_in3>; + }; + }; + }; + }; + + tpdm@11184000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11184000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-element-bits =3D <32>; + qcom,cmb-element-bits =3D <32>; + + out-ports { + port { + tpdm_cdsp_cmsr2_out: endpoint { + remote-endpoint =3D <&tpda_cdsp_in4>; + }; + }; + }; + }; + + tpdm@11185000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11185000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <64>; + + out-ports { + port { + tpdm_cdsp_dpm1_out: endpoint { + remote-endpoint =3D <&tpda_cdsp_in5>; + }; + }; + }; + }; + + tpdm@11186000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11186000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <64>; + + out-ports { + port { + tpdm_cdsp_dpm2_out: endpoint { + remote-endpoint =3D <&tpda_cdsp_in6>; + }; + }; + }; + }; + + tpda@11188000 { + compatible =3D "qcom,coresight-tpda", "arm,primecell"; + reg =3D <0x0 0x11188000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + tpda_cdsp_in0: endpoint { + remote-endpoint =3D <&tpdm_cdsp_out>; + }; + }; + + port@1 { + reg =3D <1>; + + tpda_cdsp_in1: endpoint { + remote-endpoint =3D <&tpdm_cdsp_llm_out>; + }; + }; + + port@2 { + reg =3D <2>; + + tpda_cdsp_in2: endpoint { + remote-endpoint =3D <&tpdm_cdsp_llm2_out>; + }; + }; + + port@3 { + reg =3D <3>; + + tpda_cdsp_in3: endpoint { + remote-endpoint =3D <&tpdm_cdsp_cmsr1_out>; + }; + }; + + port@4 { + reg =3D <4>; + + tpda_cdsp_in4: endpoint { + remote-endpoint =3D <&tpdm_cdsp_cmsr2_out>; + }; + }; + + port@5 { + reg =3D <5>; + + tpda_cdsp_in5: endpoint { + remote-endpoint =3D <&tpdm_cdsp_dpm1_out>; + }; + }; + + port@6 { + reg =3D <6>; + + tpda_cdsp_in6: endpoint { + remote-endpoint =3D <&tpdm_cdsp_dpm2_out>; + }; + }; + }; + + out-ports { + port { + tpda_cdsp_out: endpoint { + remote-endpoint =3D <&funnel_cdsp_in0>; + }; + }; + }; + }; + + funnel@11189000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + reg =3D <0x0 0x11189000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + port { + funnel_cdsp_in0: endpoint { + remote-endpoint =3D <&tpda_cdsp_out>; + }; + }; + }; + + out-ports { + port { + funnel_cdsp_out: endpoint { + remote-endpoint =3D <&tn_ag_in16>; + }; + }; + }; + }; + + tpdm@111a3000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x111a3000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + tpdm_pmu_out: endpoint { + remote-endpoint =3D <&tn_ag_in29>; + }; + }; + }; + }; + + tpdm@111a4000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x111a4000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + tpdm_qrng_out: endpoint { + remote-endpoint =3D <&tn_ag_in18>; + }; + }; + }; + }; + + tpdm@111a5000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x111a5000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + tpdm_dlmm_out: endpoint { + remote-endpoint =3D <&tn_ag_in25>; + }; + }; + }; + }; + + tpdm@111a6000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x111a6000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + tpdm_north_dsb_out: endpoint { + remote-endpoint =3D <&tn_ag_in26>; + }; + }; + }; + }; + + tpdm@111a7000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x111a7000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + tpdm_south_dsb_out: endpoint { + remote-endpoint =3D <&tn_ag_in27>; + }; + }; + }; + }; + + tpdm@111a8000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x111a8000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + tpdm_rdpm_cmb0_out: endpoint { + remote-endpoint =3D <&tn_ag_in30>; + }; + }; + }; + }; + + tpdm@111a9000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x111a9000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + tpdm_rdpm_cmb1_out: endpoint { + remote-endpoint =3D <&tn_ag_in31>; + }; + }; + }; + }; + + tpdm@111aa000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x111aa000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + tpdm_rdpm_cmb2_out: endpoint { + remote-endpoint =3D <&tn_ag_in32>; + }; + }; + }; + }; + + tpdm@111ab000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x111ab000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + tpdm_ipcc_cmb0_out: endpoint { + remote-endpoint =3D <&tn_ag_in36>; + }; + }; + }; + }; + + tpdm@111ac000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x111ac000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + tpdm_ipcc_cmb1_out: endpoint { + remote-endpoint =3D <&tn_ag_in28>; + }; + }; + }; + }; + + tpdm@111ad000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x111ad000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + tpdm_ipcc_cmb2_out: endpoint { + remote-endpoint =3D <&tn_ag_in34>; + }; + }; + }; + }; + + tpdm@111ae000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x111ae000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + tpdm_ipcc_cmb3_out: endpoint { + remote-endpoint =3D <&tn_ag_in37>; + }; + }; + }; + }; + + tpdm@111af000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x111af000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + tpdm_ipcc_cmb4_out: endpoint { + remote-endpoint =3D <&tn_ag_in35>; + }; + }; + }; + }; + + tpdm@111b3000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x111b3000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + tpdm_pcie_rscc_out: endpoint { + remote-endpoint =3D <&tn_ag_in8>; + }; + }; + }; + }; + + tn@111b8000 { + compatible =3D "qcom,coresight-tnoc", "arm,primecell"; + reg =3D <0x0 0x111b8000 0x0 0x4200>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@8 { + reg =3D <8>; + + tn_ag_in8: endpoint { + remote-endpoint =3D <&tpdm_pcie_rscc_out>; + }; + }; + + port@d { + reg =3D <0xd>; + + tn_ag_in13: endpoint { + remote-endpoint =3D <&funnel_modem_dl_out>; + }; + }; + + port@10 { + reg =3D <0x10>; + + tn_ag_in16: endpoint { + remote-endpoint =3D <&funnel_cdsp_out>; + }; + }; + + port@11 { + reg =3D <0x11>; + + tn_ag_in17: endpoint { + remote-endpoint =3D <&tpdm_gcc_out>; + }; + }; + + port@12 { + reg =3D <0x12>; + + tn_ag_in18: endpoint { + remote-endpoint =3D <&tpdm_qrng_out>; + }; + }; + + port@13 { + reg =3D <0x13>; + + tn_ag_in19: endpoint { + remote-endpoint =3D <&tpdm_qm_out>; + }; + }; + + port@15 { + reg =3D <0x15>; + + tn_ag_in21: endpoint { + remote-endpoint =3D <&tpdm_ipa_out>; + }; + }; + + port@19 { + reg =3D <0x19>; + + tn_ag_in25: endpoint { + remote-endpoint =3D <&tpdm_dlmm_out>; + }; + }; + + port@1a { + reg =3D <0x1a>; + + tn_ag_in26: endpoint { + remote-endpoint =3D <&tpdm_north_dsb_out>; + }; + }; + + port@1b { + reg =3D <0x1b>; + + tn_ag_in27: endpoint { + remote-endpoint =3D <&tpdm_south_dsb_out>; + }; + }; + + port@1c { + reg =3D <0x1c>; + + tn_ag_in28: endpoint { + remote-endpoint =3D <&tpdm_ipcc_cmb1_out>; + }; + }; + + port@1d { + reg =3D <0x1d>; + + tn_ag_in29: endpoint { + remote-endpoint =3D <&tpdm_pmu_out>; + }; + }; + + port@1e { + reg =3D <0x1e>; + + tn_ag_in30: endpoint { + remote-endpoint =3D <&tpdm_rdpm_cmb0_out>; + }; + }; + + port@1f { + reg =3D <0x1f>; + + tn_ag_in31: endpoint { + remote-endpoint =3D <&tpdm_rdpm_cmb1_out>; + }; + }; + + port@20 { + reg =3D <0x20>; + + tn_ag_in32: endpoint { + remote-endpoint =3D <&tpdm_rdpm_cmb2_out>; + }; + }; + + port@22 { + reg =3D <0x22>; + + tn_ag_in34: endpoint { + remote-endpoint =3D <&tpdm_ipcc_cmb2_out>; + }; + }; + + port@23 { + reg =3D <0x23>; + + tn_ag_in35: endpoint { + remote-endpoint =3D <&tpdm_ipcc_cmb4_out>; + }; + }; + + port@24 { + reg =3D <0x24>; + + tn_ag_in36: endpoint { + remote-endpoint =3D <&tpdm_ipcc_cmb0_out>; + }; + }; + + port@25 { + reg =3D <37>; + + tn_ag_in37: endpoint { + remote-endpoint =3D <&tpdm_ipcc_cmb3_out>; + }; + }; + }; + + out-ports { + port { + tn_ag_out: endpoint { + remote-endpoint =3D <&funnel_in0_in0>; + }; + }; + }; + }; + + tpdm@111d0000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x111d0000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + tpdm_qm_out: endpoint { + remote-endpoint =3D <&tn_ag_in19>; + }; + }; + }; + }; + + tpdm@11303000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11303000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <64>; + + out-ports { + port { + tpdm_swao_prio4_out: endpoint { + remote-endpoint =3D <&tpda_aoss_in4>; + }; + }; + }; + }; + + funnel@11304000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + reg =3D <0x0 0x11304000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@5 { + reg =3D <5>; + + funnel_aoss_in5: endpoint { + remote-endpoint =3D <&tpda_aoss_out>; + }; + }; + + port@6 { + reg =3D <6>; + + funnel_aoss_in6: endpoint { + remote-endpoint =3D <&funnel_in0_out>; + }; + }; + + }; + + out-ports { + port { + funnel_aoss_out: endpoint { + remote-endpoint =3D <&tmc_etf_in>; + }; + }; + }; + }; + + tmc@11305000 { + compatible =3D "arm,coresight-tmc", "arm,primecell"; + reg =3D <0x0 0x11305000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + port { + tmc_etf_in: endpoint { + remote-endpoint =3D <&funnel_aoss_out>; + }; + }; + }; + }; + + tpda@11308000 { + compatible =3D "qcom,coresight-tpda", "arm,primecell"; + reg =3D <0x0 0x11308000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + tpda_aoss_in0: endpoint { + remote-endpoint =3D <&tpdm_swao_prio0_out>; + }; + }; + + port@1 { + reg =3D <1>; + + tpda_aoss_in1: endpoint { + remote-endpoint =3D <&tpdm_swao_prio1_out>; + }; + }; + + port@2 { + reg =3D <2>; + + tpda_aoss_in2: endpoint { + remote-endpoint =3D <&tpdm_swao_prio2_out>; + }; + }; + + port@3 { + reg =3D <3>; + + tpda_aoss_in3: endpoint { + remote-endpoint =3D <&tpdm_swao_prio3_out>; + }; + }; + + port@4 { + reg =3D <4>; + + tpda_aoss_in4: endpoint { + remote-endpoint =3D <&tpdm_swao_prio4_out>; + }; + }; + + port@5 { + reg =3D <5>; + + tpda_aoss_in5: endpoint { + remote-endpoint =3D <&tpdm_swao_out>; + }; + }; + }; + + out-ports { + port { + tpda_aoss_out: endpoint { + remote-endpoint =3D <&funnel_aoss_in5>; + }; + }; + }; + }; + + tpdm@11309000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11309000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <64>; + + out-ports { + port { + tpdm_swao_prio0_out: endpoint { + remote-endpoint =3D <&tpda_aoss_in0>; + }; + }; + }; + }; + + tpdm@1130a000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x1130a000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <64>; + + out-ports { + port { + tpdm_swao_prio1_out: endpoint { + remote-endpoint =3D <&tpda_aoss_in1>; + }; + }; + }; + }; + + tpdm@1130b000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x1130b000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <64>; + + out-ports { + port { + tpdm_swao_prio2_out: endpoint { + remote-endpoint =3D <&tpda_aoss_in2>; + }; + }; + }; + }; + + tpdm@1130c000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x1130c000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <64>; + + out-ports { + port { + tpdm_swao_prio3_out: endpoint { + remote-endpoint =3D <&tpda_aoss_in3>; + }; + }; + }; + }; + + tpdm@1130d000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x1130d000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-element-bits =3D <32>; + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + tpdm_swao_out: endpoint { + remote-endpoint =3D <&tpda_aoss_in5>; + }; + }; + }; + }; + + tpdm@11422000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11422000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + tpdm_ipa_out: endpoint { + remote-endpoint =3D <&tn_ag_in21>; + }; + }; + }; + }; + sram@14680000 { compatible =3D "qcom,kaanapali-imem", "mmio-sram"; reg =3D <0x0 0x14680000 0x0 0x1000>; @@ -1603,4 +2711,56 @@ timer { , ; }; + + tpdm-cdsp-llm { + compatible =3D "qcom,coresight-static-tpdm"; + qcom,cmb-element-bits =3D <32>; + + out-ports { + port { + tpdm_cdsp_llm_out: endpoint { + remote-endpoint =3D <&tpda_cdsp_in1>; + }; + }; + }; + }; + + tpdm-cdsp-llm2 { + compatible =3D "qcom,coresight-static-tpdm"; + qcom,cmb-element-bits =3D <32>; + + out-ports { + port { + tpdm_cdsp_llm2_out: endpoint { + remote-endpoint =3D <&tpda_cdsp_in2>; + }; + }; + }; + }; + + tpdm-modem1 { + compatible =3D "qcom,coresight-static-tpdm"; + qcom,cmb-element-bits =3D <32>; + + out-ports { + port { + tpdm_modem1_out: endpoint { + remote-endpoint =3D <&tpda_modem_in1>; + }; + }; + }; + }; + + tpdm-modem2 { + compatible =3D "qcom,coresight-static-tpdm"; + qcom,cmb-element-bits =3D <64>; + + out-ports { + port { + tpdm_modem2_out: endpoint { + remote-endpoint =3D <&tpda_modem_in2>; + }; + }; + }; + }; }; --=20 2.25.1 From nobody Sun Feb 8 10:33:44 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF33436B079 for ; Tue, 3 Feb 2026 06:06:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770098798; cv=none; b=uGHxFuUBzfKfoP8lQTq+tHhUU5Jeo+w5JC6+rkdH31xc5HuDiq8R3z6WMkK93MhOCFWiLMAY2Ggx/iJi0dtHAwgA546ZPUCNR3SuxLZBCv3uLq6SYMp3ee7G6DxeV2iLiWPLgDMzfnfIFDNtKt0DPamOhSgigLxoIogNSzNUzWw= ARC-Message-Signature: i=1; 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Kaanapali has 24 QUP serial engines across 4 QUP wrappers, each with support of GPI DMA engines, and it also includes 5 I2C hubs. Signed-off-by: Jyothi Kumar Seerapu Reviewed-by: Dmitry Baryshkov Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 2092 +++++++++++++++++++++++++++= ++++ 1 file changed, 2092 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/= qcom/kaanapali.dtsi index 6e231850d5d6..df05d204ed41 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -468,6 +469,508 @@ gcc: clock-controller@100000 { #power-domain-cells =3D <1>; }; =20 + gpi_dma2: dma-controller@800000 { + compatible =3D "qcom,kaanapali-gpi-dma", "qcom,sm6350-gpi-dma"; + reg =3D <0x0 0x00800000 0x0 0x60000>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels =3D <12>; + dma-channel-mask =3D <0x1f>; + #dma-cells =3D <3>; + + iommus =3D <&apps_smmu 0x436 0x0>; + dma-coherent; + }; + + qupv3_2: geniqup@8c0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x008c0000 0x0 0x2000>; + + clocks =3D <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + clock-names =3D "m-ahb", + "s-ahb"; + + iommus =3D <&apps_smmu 0x423 0x0>; + + dma-coherent; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + i2c8: i2c@880000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00880000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma2 0 0 QCOM_GPI_I2C>, + <&gpi_dma2 1 0 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c8_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi8: spi@880000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00880000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma2 0 0 QCOM_GPI_SPI>, + <&gpi_dma2 1 0 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi8_data_clk>, <&qup_spi8_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c9: i2c@884000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00884000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma2 0 1 QCOM_GPI_I2C>, + <&gpi_dma2 1 1 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c9_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi9: spi@884000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00884000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma2 0 1 QCOM_GPI_SPI>, + <&gpi_dma2 1 1 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi9_data_clk>, <&qup_spi9_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c10: i2c@888000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00888000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma2 0 2 QCOM_GPI_I2C>, + <&gpi_dma2 1 2 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c10_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi10: spi@888000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00888000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma2 0 2 QCOM_GPI_SPI>, + <&gpi_dma2 1 2 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi10_data_clk>, <&qup_spi10_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c11: i2c@88c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x0088c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c11_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi11: spi@88c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x0088c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma2 0 3 QCOM_GPI_SPI>, + <&gpi_dma2 1 3 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi11_data_clk>, <&qup_spi11_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c12: i2c@890000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00890000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c12_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + }; + + i2c_master_hub: geniqup@9c0000 { + compatible =3D "qcom,geni-se-i2c-master-hub"; + reg =3D <0x0 0x009c0000 0x0 0x2000>; + + clocks =3D <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; + clock-names =3D "s-ahb"; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + i2c_hub_0: i2c@980000 { + compatible =3D "qcom,geni-i2c-master-hub"; + reg =3D <0x0 0x00980000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_I2C_S0_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names =3D "se", + "core"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&hub_i2c0_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c_hub_1: i2c@984000 { + compatible =3D "qcom,geni-i2c-master-hub"; + reg =3D <0x0 0x00984000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_I2C_S1_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names =3D "se", + "core"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&hub_i2c1_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c_hub_2: i2c@988000 { + compatible =3D "qcom,geni-i2c-master-hub"; + reg =3D <0x0 0x00988000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_I2C_S2_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names =3D "se", + "core"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&hub_i2c2_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c_hub_3: i2c@98c000 { + compatible =3D "qcom,geni-i2c-master-hub"; + reg =3D <0x0 0x0098c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_I2C_S3_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names =3D "se", + "core"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&hub_i2c3_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c_hub_4: i2c@990000 { + compatible =3D "qcom,geni-i2c-master-hub"; + reg =3D <0x0 0x00990000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_I2C_S4_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names =3D "se", + "core"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&hub_i2c4_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + }; + + gpi_dma1: dma-controller@a00000 { + compatible =3D "qcom,kaanapali-gpi-dma", "qcom,sm6350-gpi-dma"; + reg =3D <0x0 0x00a00000 0x0 0x60000>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels =3D <12>; + dma-channel-mask =3D <0x1f>; + #dma-cells =3D <3>; + + iommus =3D <&apps_smmu 0xb6 0x0>; + dma-coherent; + }; + qupv3_1: geniqup@ac0000 { compatible =3D "qcom,geni-se-qup"; reg =3D <0x0 0x00ac0000 0x0 0x2000>; @@ -485,6 +988,447 @@ qupv3_1: geniqup@ac0000 { #size-cells =3D <2>; ranges; =20 + i2c0: i2c@a80000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a80000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c0_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi0: spi@a80000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a80000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi0_data_clk>, <&qup_spi0_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c1: i2c@a84000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a84000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c1_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi1: spi@a84000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a84000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi1_data_clk>, <&qup_spi1_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c2: i2c@a88000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a88000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c2_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi2: spi@a88000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a88000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi2_data_clk>, <&qup_spi2_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c3: i2c@a8c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a8c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c3_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi3: spi@a8c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a8c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi3_data_clk>, <&qup_spi3_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c4: i2c@a90000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a90000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c4_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi4: spi@a90000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a90000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi4_data_clk>, <&qup_spi4_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c5: i2c@a94000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a94000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c5_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi5: spi@a94000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a94000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi5_data_clk>, <&qup_spi5_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c6: i2c@a98000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a98000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c6_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi6: spi@a98000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a98000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma1 0 6 QCOM_GPI_SPI>, + <&gpi_dma1 1 6 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi6_data_clk>, <&qup_spi6_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + uart7: serial@a9c000 { compatible =3D "qcom,geni-debug-uart"; reg =3D <0x0 0x00a9c000 0x0 0x4000>; @@ -566,6 +1510,653 @@ mmss_noc: interconnect@1780000 { #interconnect-cells =3D <2>; }; =20 + gpi_dma3: dma-controller@1900000 { + compatible =3D "qcom,kaanapali-gpi-dma", "qcom,sm6350-gpi-dma"; + reg =3D <0x0 0x01900000 0x0 0x60000>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels =3D <12>; + dma-channel-mask =3D <0x1e>; + #dma-cells =3D <3>; + + iommus =3D <&apps_smmu 0x4d6 0x0>; + dma-coherent; + }; + + qupv3_3: geniqup@19c0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x019c0000 0x0 0x2000>; + + clocks =3D <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; + clock-names =3D "m-ahb", + "s-ahb"; + + iommus =3D <&apps_smmu 0x4c3 0x0>; + + dma-coherent; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + i2c13: i2c@1980000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x01980000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma3 0 0 QCOM_GPI_I2C>, + <&gpi_dma3 1 0 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c13_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c14: i2c@1984000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x01984000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S1_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma3 0 1 QCOM_GPI_I2C>, + <&gpi_dma3 1 1 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c14_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi14: spi@1984000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x01984000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S1_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma3 0 1 QCOM_GPI_SPI>, + <&gpi_dma3 1 1 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi14_data_clk>, <&qup_spi14_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c15: i2c@1988000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x01988000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S2_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma3 0 2 QCOM_GPI_I2C>, + <&gpi_dma3 1 2 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c15_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi15: spi@1988000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x01988000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S2_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma3 0 2 QCOM_GPI_SPI>, + <&gpi_dma3 1 2 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi15_data_clk>, <&qup_spi15_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c16: i2c@198c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x0198c000 0x0 0x4000>; + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S3_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma3 0 3 QCOM_GPI_I2C>, + <&gpi_dma3 1 3 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c16_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi16: spi@198c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x198c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S3_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma3 0 3 QCOM_GPI_SPI>, + <&gpi_dma3 1 3 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi16_data_clk>, <&qup_spi16_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c17: i2c@1990000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x01990000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S4_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma3 0 4 QCOM_GPI_I2C>, + <&gpi_dma3 1 4 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c17_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi17: spi@1990000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x01990000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S4_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma3 0 4 QCOM_GPI_SPI>, + <&gpi_dma3 1 4 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi17_data_clk>, <&qup_spi17_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart18: serial@1994000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x01994000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP3_S5_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart18_default>, <&qup_uart18_cts_rts>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + }; + + gpi_dma4: dma-controller@1a00000 { + compatible =3D "qcom,kaanapali-gpi-dma", "qcom,sm6350-gpi-dma"; + reg =3D <0x0 0x01a00000 0x0 0x60000>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels =3D <12>; + dma-channel-mask =3D <0x1e>; + #dma-cells =3D <3>; + + iommus =3D <&apps_smmu 0x536 0x0>; + dma-coherent; + }; + + qupv3_4: geniqup@1ac0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x01ac0000 0x0 0x2000>; + + clocks =3D <&gcc GCC_QUPV3_WRAP_4_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_4_S_AHB_CLK>; + clock-names =3D "m-ahb", + "s-ahb"; + + iommus =3D <&apps_smmu 0x523 0x0>; + + dma-coherent; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + i2c19: i2c@1a80000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x01a80000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP4_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma4 0 0 QCOM_GPI_I2C>, + <&gpi_dma4 1 0 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c19_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi19: spi@1a80000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x01a80000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP4_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma4 0 0 QCOM_GPI_SPI>, + <&gpi_dma4 1 0 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi19_data_clk>, <&qup_spi19_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c20: i2c@1a84000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x01a84000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP4_S1_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma4 0 1 QCOM_GPI_I2C>, + <&gpi_dma4 1 1 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c20_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi20: spi@1a84000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x01a84000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP4_S1_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma4 0 1 QCOM_GPI_SPI>, + <&gpi_dma4 1 1 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi20_data_clk>, <&qup_spi20_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c21: i2c@1a88000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x01a88000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP4_S2_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma4 0 2 QCOM_GPI_I2C>, + <&gpi_dma4 1 2 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c21_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi21: spi@1a88000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x01a88000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP4_S2_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma4 0 2 QCOM_GPI_SPI>, + <&gpi_dma4 1 2 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi21_data_clk>, <&qup_spi21_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c22: i2c@1a8c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x01a8c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP4_S3_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma4 0 3 QCOM_GPI_I2C>, + <&gpi_dma4 1 3 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c22_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c23: i2c@1a90000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x01a90000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP4_S4_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma4 0 4 QCOM_GPI_I2C>, + <&gpi_dma4 1 4 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c23_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + }; + pcie0: pcie@1c00000 { device_type =3D "pci"; compatible =3D "qcom,kaanapali-pcie", "qcom,pcie-sm8550"; @@ -1017,6 +2608,491 @@ tlmm: pinctrl@f100000 { #interrupt-cells =3D <2>; wakeup-parent =3D <&pdc>; =20 + hub_i2c0_data_clk: hub-i2c0-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio66", "gpio67"; + function =3D "i2chub0_se0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + hub_i2c1_data_clk: hub-i2c1-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio78", "gpio79"; + function =3D "i2chub0_se1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + hub_i2c2_data_clk: hub-i2c2-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio68", "gpio69"; + function =3D "i2chub0_se2"; + drive-strength =3D <2>; + bias-pull-up; + }; + + hub_i2c3_data_clk: hub-i2c3-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio70", "gpio71"; + function =3D "i2chub0_se3"; + drive-strength =3D <2>; + bias-pull-up; + }; + + hub_i2c4_data_clk: hub-i2c4-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio72", "gpio73"; + function =3D "i2chub0_se4"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c0_data_clk: qup-i2c0-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio80", "gpio83"; + function =3D "qup1_se0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c1_data_clk: qup-i2c1-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio74", "gpio75"; + function =3D "qup1_se1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio40", "gpio41"; + function =3D "qup1_se2"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio44", "gpio45"; + function =3D "qup1_se3"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c4_data_clk: qup-i2c4-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio36", "gpio37"; + function =3D "qup1_se4"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c5_data_clk: qup-i2c5-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio52", "gpio53"; + function =3D "qup1_se5"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c6_data_clk: qup-i2c6-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio56", "gpio57"; + function =3D "qup1_se6"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c8_data_clk: qup-i2c8-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio0", "gpio1"; + function =3D "qup2_se0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c9_data_clk: qup-i2c9-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio4", "gpio5"; + function =3D "qup2_se1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c10_data_clk: qup-i2c10-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio117", "gpio118"; + function =3D "qup2_se2"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c11_data_clk: qup-i2c11-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio122", "gpio123"; + function =3D "qup2_se3"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c12_data_clk: qup-i2c12-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio208", "gpio209"; + function =3D "qup2_se4"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c13_data_clk: qup-i2c13-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio64", "gpio65"; + function =3D "qup3_se0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c14_data_clk: qup-i2c14-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio8", "gpio9"; + function =3D "qup3_se1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c15_data_clk: qup-i2c15-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio12", "gpio13"; + function =3D "qup3_se2"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c16_data_clk: qup-i2c16-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio16", "gpio17"; + function =3D "qup3_se3"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c17_data_clk: qup-i2c17-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio20", "gpio21"; + function =3D "qup3_se4"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c19_data_clk: qup-i2c19-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio48", "gpio49"; + function =3D "qup4_se0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c20_data_clk: qup-i2c20-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio28", "gpio29"; + function =3D "qup4_se1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c21_data_clk: qup-i2c21-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio32", "gpio33"; + function =3D "qup4_se2"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c22_data_clk: qup-i2c22-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio121", "gpio84"; + function =3D "qup4_se3"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c23_data_clk: qup-i2c23-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio161", "gpio162"; + function =3D "qup4_se4"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi0_cs: qup-spi0-cs-state { + pins =3D "gpio81"; + function =3D "qup1_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi0_data_clk: qup-spi0-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio80", "gpio83", "gpio82"; + function =3D "qup1_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi1_cs: qup-spi1-cs-state { + pins =3D "gpio77"; + function =3D "qup1_se1"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi1_data_clk: qup-spi1-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio74", "gpio75", "gpio76"; + function =3D "qup1_se1"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi2_cs: qup-spi2-cs-state { + pins =3D "gpio43"; + function =3D "qup1_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi2_data_clk: qup-spi2-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio40", "gpio41", "gpio42"; + function =3D "qup1_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi3_cs: qup-spi3-cs-state { + pins =3D "gpio47"; + function =3D "qup1_se3"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi3_data_clk: qup-spi3-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio44", "gpio45", "gpio46"; + function =3D "qup1_se3"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi4_cs: qup-spi4-cs-state { + pins =3D "gpio39"; + function =3D "qup1_se4"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi4_data_clk: qup-spi4-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio36", "gpio37", "gpio38"; + function =3D "qup1_se4"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi5_cs: qup-spi5-cs-state { + pins =3D "gpio55"; + function =3D "qup1_se5"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi5_data_clk: qup-spi5-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio52", "gpio53", "gpio54"; + function =3D "qup1_se5"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi6_cs: qup-spi6-cs-state { + pins =3D "gpio59"; + function =3D "qup1_se6"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi6_data_clk: qup-spi6-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio56", "gpio57", "gpio58"; + function =3D "qup1_se6"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi8_cs: qup-spi8-cs-state { + pins =3D "gpio3"; + function =3D "qup2_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi8_data_clk: qup-spi8-data-clk-state { + /* MISO, MOSI, CLK */pins =3D "gpio0", "gpio1", "gpio2"; + function =3D "qup2_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi9_cs: qup-spi9-cs-state { + pins =3D "gpio7"; + function =3D "qup2_se1"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi9_data_clk: qup-spi9-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio4", "gpio5", "gpio6"; + function =3D "qup2_se1"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi10_cs: qup-spi10-cs-state { + pins =3D "gpio120"; + function =3D "qup2_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi10_data_clk: qup-spi10-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio117", "gpio118", "gpio119"; + function =3D "qup2_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi11_cs: qup-spi11-cs-state { + pins =3D "gpio125"; + function =3D "qup2_se3"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi11_data_clk: qup-spi11-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio122", "gpio123", "gpio124"; + function =3D "qup2_se3"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi14_cs: qup-spi14-cs-state { + pins =3D "gpio11"; + function =3D "qup3_se1"; + drive-strength =3D <6>; + bias-pull-up; + }; + + qup_spi14_data_clk: qup-spi14-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio8", "gpio9", "gpio10"; + function =3D "qup3_se1"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi15_cs: qup-spi15-cs-state { + pins =3D "gpio15"; + function =3D "qup3_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi15_data_clk: qup-spi15-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio12", "gpio13", "gpio14"; + function =3D "qup3_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi16_cs: qup-spi16-cs-state { + pins =3D "gpio19"; + function =3D "qup3_se3"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi16_data_clk: qup-spi16-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio16", "gpio17", "gpio18"; + function =3D "qup3_se3"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi17_cs: qup-spi17-cs-state { + pins =3D "gpio23"; + function =3D "qup3_se4"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi17_data_clk: qup-spi17-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio20", "gpio21", "gpio22"; + function =3D "qup3_se4"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi19_cs: qup-spi19-cs-state { + pins =3D "gpio51"; + function =3D "qup4_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi19_data_clk: qup-spi19-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio48", "gpio49", "gpio50"; + function =3D "qup4_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi20_cs: qup-spi20-cs-state { + pins =3D "gpio31"; + function =3D "qup4_se1"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi20_data_clk: qup-spi20-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio28", "gpio29", "gpio30"; + function =3D "qup4_se1"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi21_cs: qup-spi21-cs-state { + pins =3D "gpio35"; + function =3D "qup4_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi21_data_clk: qup-spi21-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio32", "gpio33", "gpio34"; + function =3D "qup4_se2"; + drive-strength =3D <6>; + bias-disable; + }; + qup_uart7_default: qup-uart7-state { /* TX, RX */ pins =3D "gpio62", "gpio63"; @@ -1025,6 +3101,22 @@ qup_uart7_default: qup-uart7-state { bias-disable; }; =20 + qup_uart18_default: qup-uart18-default-state { + /* TX, RX */ + pins =3D "gpio26", "gpio27"; + function =3D "qup3_se5"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_uart18_cts_rts: qup-uart18-cts-rts-state { + /* CTS, RTS */ + pins =3D "gpio24", "gpio25"; + function =3D "qup3_se5"; + drive-strength =3D <2>; + bias-pull-down; + }; + sdc2_default: sdc2-default-state { clk-pins { pins =3D "sdc2_clk"; --=20 2.25.1 From nobody Sun Feb 8 10:33:44 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 876F336BCE4 for ; Tue, 3 Feb 2026 06:06:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b8283def01sm417499eec.34.2026.02.02.22.06.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Feb 2026 22:06:31 -0800 (PST) From: Jingyi Wang Date: Mon, 02 Feb 2026 22:06:20 -0800 Subject: [PATCH v5 03/10] arm64: dts: qcom: kaanapali: Add TSENS and thermal zones Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260202-knp-dts-misc-v5-3-02de82bf9901@oss.qualcomm.com> References: <20260202-knp-dts-misc-v5-0-02de82bf9901@oss.qualcomm.com> In-Reply-To: <20260202-knp-dts-misc-v5-0-02de82bf9901@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jingyi Wang , 20260114-knp-remoteproc-v4-0-fcf0b04d01af@oss.qualcomm.com, Manaf Meethalavalappu Pallikunhi , Konrad Dybcio X-Mailer: b4 0.15-dev-3d134 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770098787; l=21820; i=jingyi.wang@oss.qualcomm.com; s=20250911; h=from:subject:message-id; bh=57BK10vrSKxDmNIb15WOBEDGWrb50WLKstLYTMBM8Qg=; b=oTOWvzEU1WpqF0iCfN7EFKXMOAdGWqOILAKnCKAoU/8VgNOGu7GyPU7xVZk7NdNTkdLS7zca0 Hzbxg57w3pWCzMp1J4+j9095OXur5gNQwnyWvIJg4G7t/FeLsU930UE X-Developer-Key: i=jingyi.wang@oss.qualcomm.com; a=ed25519; pk=PSoHZ6KbUss3IW8FPRVMHMK0Jkkr/jV347mBYJO3iLo= X-Proofpoint-GUID: hvUJX8Xuog-jyZJx6oJFyJ4OtK-Jxhur X-Proofpoint-ORIG-GUID: hvUJX8Xuog-jyZJx6oJFyJ4OtK-Jxhur X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjAzMDA0NyBTYWx0ZWRfX7sBjKN/Xynvb r1AIumlrPGcKjeocWhj+RKakF4vS/XlOAG0jgR+zy37jtuzQrCPWPFgeLYsvADDs5Px53oFpT9j 3oF1jr30LHrJkPlEf7zhofS4AvZLuyVEY+i/lngxCWuOAbcXY/7XFCw2G0Y03/IbjUomNtNOd0z z+PW59nsCvHzI+iAX7Gcwic6t5+EEf+1nV32L9lwvGdtr7B/oAGMwsRT5w4UX8DVqEXV6jJ1b4N T83biK+hMzHejc6m6luJof6HtUKoLiy6NJwS9QTdWFLpdjkl5Rfevw20l/+xverk+pxqrdoTujv cs4uS+9b6H9JEdvHDxGJSQG72chGELbWLffNilbQj86TbTyUThZ25zdriCrcCKjgrsoaTtfMNL2 G2UxAzRSuN6PSGCuZ5lN2uOANssga0ztkUvLorczLxzzfMMy2auLRM154GYIybqsbUrrK7Q/FYU pC7D7Rq50u1O9dI0dWA== X-Authority-Analysis: v=2.4 cv=AurjHe9P c=1 sm=1 tr=0 ts=69819069 cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=gpPq06xVYaF9EkK19g8A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-03_01,2026-02-02_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 suspectscore=0 phishscore=0 adultscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602030047 From: Manaf Meethalavalappu Pallikunhi The Kaanapali includes seven TSENS instances, with a total of 55 thermal sensors distributed across various locations on the SoC. The TSENS max/reset threshold is configured to 130=C2=B0C in the hardware. Enable all TSENS instances, and define the thermal zones with a hot trip at 120=C2=B0C and critical trip at 125=C2=B0C. Signed-off-by: Manaf Meethalavalappu Pallikunhi Reviewed-by: Konrad Dybcio Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 1075 +++++++++++++++++++++++++++= ++++ 1 file changed, 1075 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/= qcom/kaanapali.dtsi index df05d204ed41..251e36cf7477 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -2583,6 +2583,90 @@ pdc: interrupt-controller@b220000 { interrupt-controller; }; =20 + tsens0: thermal-sensor@c229000 { + compatible =3D "qcom,kaanapali-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c229000 0x0 0x1000>, + <0x0 0x0c222000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <5>; + #thermal-sensor-cells =3D <1>; + }; + + tsens1: thermal-sensor@c22a000 { + compatible =3D "qcom,kaanapali-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c22a000 0x0 0x1000>, + <0x0 0x0c223000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <12>; + #thermal-sensor-cells =3D <1>; + }; + + tsens2: thermal-sensor@c22b000 { + compatible =3D "qcom,kaanapali-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c22b000 0x0 0x1000>, + <0x0 0x0c224000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <7>; + #thermal-sensor-cells =3D <1>; + }; + + tsens3: thermal-sensor@c22c000 { + compatible =3D "qcom,kaanapali-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c22c000 0x0 0x1000>, + <0x0 0x0c225000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <4>; + #thermal-sensor-cells =3D <1>; + }; + + tsens4: thermal-sensor@c22d000 { + compatible =3D "qcom,kaanapali-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c22d000 0x0 0x1000>, + <0x0 0x0c226000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <8>; + #thermal-sensor-cells =3D <1>; + }; + + tsens5: thermal-sensor@c22e000 { + compatible =3D "qcom,kaanapali-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c22e000 0x0 0x1000>, + <0x0 0x0c227000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <12>; + #thermal-sensor-cells =3D <1>; + }; + + tsens6: thermal-sensor@c22f000 { + compatible =3D "qcom,kaanapali-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c22f000 0x0 0x1000>, + <0x0 0x0c228000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <7>; + #thermal-sensor-cells =3D <1>; + }; + aoss_qmp: power-management@c300000 { compatible =3D "qcom,kaanapali-aoss-qmp", "qcom,aoss-qmp"; reg =3D <0x0 0x0c300000 0x0 0x400>; @@ -4795,6 +4879,997 @@ pdp_tx: scp-sram-section@100 { }; }; =20 + thermal-zones { + cpullc-0-0-thermal { + thermal-sensors =3D <&tsens0 0>; + + trips { + cpullc-0-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpullc-0-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpullc-0-1-thermal { + thermal-sensors =3D <&tsens0 1>; + + trips { + cpullc-0-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpullc-0-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + qmx-0-0-thermal { + thermal-sensors =3D <&tsens0 2>; + + trips { + qmx-0-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + qmx-0-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + qmx-0-1-thermal { + thermal-sensors =3D <&tsens0 3>; + + trips { + qmx-0-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + qmx-0-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + qmx-0-2-thermal { + thermal-sensors =3D <&tsens0 4>; + + trips { + qmx-0-2-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + qmx-0-2-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-0-0-0-thermal { + thermal-sensors =3D <&tsens1 0>; + + trips { + cpu-0-0-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-0-0-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-0-0-1-thermal { + thermal-sensors =3D <&tsens1 1>; + + trips { + cpu-0-0-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-0-0-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-0-1-0-thermal { + thermal-sensors =3D <&tsens1 2>; + + trips { + cpu-0-1-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-0-1-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-0-1-1-thermal { + thermal-sensors =3D <&tsens1 3>; + + trips { + cpu-0-1-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-0-1-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-0-2-0-thermal { + thermal-sensors =3D <&tsens1 4>; + + trips { + cpu-0-2-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-0-2-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-0-2-1-thermal { + thermal-sensors =3D <&tsens1 5>; + + trips { + cpu-0-2-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-0-2-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-0-3-0-thermal { + thermal-sensors =3D <&tsens1 6>; + + trips { + cpu-0-3-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-0-3-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-0-3-1-thermal { + thermal-sensors =3D <&tsens1 7>; + + trips { + cpu-0-3-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-0-3-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-0-4-0-thermal { + thermal-sensors =3D <&tsens1 8>; + + trips { + cpu-0-4-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-0-4-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-0-4-1-thermal { + thermal-sensors =3D <&tsens1 9>; + + trips { + cpu-0-4-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-0-4-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-0-5-0-thermal { + thermal-sensors =3D <&tsens1 10>; + + trips { + cpu-0-5-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-0-5-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-0-5-1-thermal { + thermal-sensors =3D <&tsens1 11>; + + trips { + cpu-0-5-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-0-5-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpullc-1-0-thermal { + thermal-sensors =3D <&tsens2 0>; + + trips { + cpullc-1-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpullc-1-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpullc-1-1-thermal { + thermal-sensors =3D <&tsens2 1>; + + trips { + cpullc-1-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpullc-1-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + qmx-1-0-thermal { + thermal-sensors =3D <&tsens2 2>; + + trips { + qmx-1-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + qmx-1-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + qmx-1-1-thermal { + thermal-sensors =3D <&tsens2 3>; + + trips { + qmx-1-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + qmx-1-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + qmx-1-2-thermal { + thermal-sensors =3D <&tsens2 4>; + + trips { + qmx-1-2-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + qmx-1-2-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + qmx-1-3-thermal { + thermal-sensors =3D <&tsens2 5>; + + trips { + qmx-1-3-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + qmx-1-3-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + qmx-1-4-thermal { + thermal-sensors =3D <&tsens2 6>; + + trips { + qmx-1-4-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + qmx-1-4-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-1-0-0-thermal { + thermal-sensors =3D <&tsens3 0>; + + trips { + cpu-1-0-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-1-0-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-1-0-1-thermal { + thermal-sensors =3D <&tsens3 1>; + + trips { + cpu-1-0-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-1-0-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-1-1-0-thermal { + thermal-sensors =3D <&tsens3 2>; + + trips { + cpu-1-1-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-1-1-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-1-1-1-thermal { + thermal-sensors =3D <&tsens3 3>; + + trips { + cpu-1-1-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu-1-1-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nsphvx-0-thermal { + thermal-sensors =3D <&tsens4 0>; + + trips { + nsphvx-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + nsphvx-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nsphvx-1-thermal { + thermal-sensors =3D <&tsens4 1>; + + trips { + nsphvx-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + nsphvx-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nsphvx-2-thermal { + thermal-sensors =3D <&tsens4 2>; + + trips { + nsphvx-2-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + nsphvx-2-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nsphvx-3-thermal { + thermal-sensors =3D <&tsens4 3>; + + trips { + nsphvx-3-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + nsphvx-3-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nsphmx-0-thermal { + thermal-sensors =3D <&tsens4 4>; + + trips { + nsphmx-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + nsphmx-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nsphmx-1-thermal { + thermal-sensors =3D <&tsens4 5>; + + trips { + nsphmx-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + nsphmx-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nsphmx-2-thermal { + thermal-sensors =3D <&tsens4 6>; + + trips { + nsphmx-2-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + nsphmx-2-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nsphmx-3-thermal { + thermal-sensors =3D <&tsens4 7>; + + trips { + nsphmx-3-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + nsphmx-3-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpuss-0-thermal { + thermal-sensors =3D <&tsens5 0>; + + trips { + gpuss-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpuss-1-thermal { + thermal-sensors =3D <&tsens5 1>; + + trips { + gpuss-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpuss-2-thermal { + thermal-sensors =3D <&tsens5 2>; + + trips { + gpuss-2-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-2-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpuss-3-thermal { + thermal-sensors =3D <&tsens5 3>; + + trips { + gpuss-3-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-3-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpuss-4-thermal { + thermal-sensors =3D <&tsens5 4>; + + trips { + gpuss-4-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-4-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpuss-5-thermal { + thermal-sensors =3D <&tsens5 5>; + + trips { + gpuss-5-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-5-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpuss-6-thermal { + thermal-sensors =3D <&tsens5 6>; + + trips { + gpuss-6-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-6-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpuss-7-thermal { + thermal-sensors =3D <&tsens5 7>; + + trips { + gpuss-7-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-7-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpuss-8-thermal { + thermal-sensors =3D <&tsens5 8>; + + trips { + gpuss-8-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-8-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpuss-9-thermal { + thermal-sensors =3D <&tsens5 9>; + + trips { + gpuss-9-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-9-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpuss-10-thermal { + thermal-sensors =3D <&tsens5 10>; + + trips { + gpuss-10-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-10-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + ddr-thermal { + thermal-sensors =3D <&tsens5 11>; + + trips { + ddr-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + ddr-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + mdmss-0-thermal { + thermal-sensors =3D <&tsens6 0>; + + trips { + mdmss-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + mdmss-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + mdmss-1-thermal { + thermal-sensors =3D <&tsens6 1>; + trips { + mdmss-1-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + mdmss-1-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + mdmss-2-thermal { + thermal-sensors =3D <&tsens6 2>; + + trips { + mdmss-2-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + mdmss-2-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + mdmss-3-thermal { + thermal-sensors =3D <&tsens6 3>; + + trips { + mdmss-3-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + mdmss-3-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + camera-0-thermal { + thermal-sensors =3D <&tsens6 4>; + + trips { + camera-0-hot { + temperature =3D <120000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + camera-0-critical { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b8283def01sm417499eec.34.2026.02.02.22.06.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Feb 2026 22:06:32 -0800 (PST) From: Jingyi Wang Date: Mon, 02 Feb 2026 22:06:21 -0800 Subject: [PATCH v5 04/10] arm64: dts: qcom: kaanapali: Add ADSP and CDSP for Kaanapali SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260202-knp-dts-misc-v5-4-02de82bf9901@oss.qualcomm.com> References: <20260202-knp-dts-misc-v5-0-02de82bf9901@oss.qualcomm.com> In-Reply-To: <20260202-knp-dts-misc-v5-0-02de82bf9901@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jingyi Wang , 20260114-knp-remoteproc-v4-0-fcf0b04d01af@oss.qualcomm.com, Kumari Pallavi , Dmitry Baryshkov X-Mailer: b4 0.15-dev-3d134 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770098787; l=9654; i=jingyi.wang@oss.qualcomm.com; s=20250911; h=from:subject:message-id; bh=uUBE3lTqLTzvbb91gqNdaKq9CEjQg0KFuOf7KF+AA3A=; b=d4xtQn28BLwFs+tn5R47cPQECuqTUZy/pFl/6M6VW+y9V2BXVrXDgLgUUHzDAWkpewmb3cRlh ar1FnsWAGSLDQ6no1sunMBWI/881YXOXcHVzSx/rcrMbCtlx/tq1Hvd X-Developer-Key: i=jingyi.wang@oss.qualcomm.com; a=ed25519; pk=PSoHZ6KbUss3IW8FPRVMHMK0Jkkr/jV347mBYJO3iLo= X-Proofpoint-GUID: 3uZuxbadUlDUiHZsAfbnSZ6zF1U_uTX1 X-Proofpoint-ORIG-GUID: 3uZuxbadUlDUiHZsAfbnSZ6zF1U_uTX1 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjAzMDA0NyBTYWx0ZWRfXzffSR2H4iSiN iGaTVdFr6OT55GPkINj3LBw58zzSCrx1zEO0GqBuaJRNWvoQWBvhJ2aO7lmTn7aBKXeUbgxebqi WOnV78iNHLVYP5bw2QAPxef6WJgxgowPPoN+KA70UgTqHVfInc3D9aJnBxcFBG8/V5ixAKRPhdW bF/UAvT2yRPNFmLzTmHSOYHt+E69MmP7ACdJlOT96NdNyvrSeiyn1XqN32yL+nhQfabqcoOWwIH 6oBKADr65oSSCUgfqwIJIc0h5Y68ga37XmdcuiCNcbxOQLjkUpRFw3wfLZ2B4MEhhaVYIPOrBkP LC/xQpPcaynl+C2y3kttpV+Yev+EIzpwDuPqixKVmPiQa65NDIoAYK6r66pq4QxbygkHpfj9PVv 578gkwy8PX09IV7GajZ+0ugUO8USigdphmqTsMjShjtisvAOrTGpy16/ejcngU91/4xmGT415Qj DXS72pE8wy7T0GB7gyg== X-Authority-Analysis: v=2.4 cv=AurjHe9P c=1 sm=1 tr=0 ts=6981906b cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=vejemSqAVpqrvhYTndAA:9 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-03_01,2026-02-02_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 suspectscore=0 phishscore=0 adultscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602030047 Add remoteproc PAS loader for ADSP and CDSP with its SMP2P and fastrpc nodes. Co-developed-by: Kumari Pallavi Signed-off-by: Kumari Pallavi Reviewed-by: Dmitry Baryshkov Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 314 ++++++++++++++++++++++++++++= ++++ 1 file changed, 314 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/= qcom/kaanapali.dtsi index 251e36cf7477..c8f61200f261 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -443,6 +443,58 @@ rmtfs_mem: rmtfs@d7c00000 { }; }; =20 + smp2p-adsp { + compatible =3D "qcom,smp2p"; + + interrupts-extended =3D <&ipcc IPCC_MPROC_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes =3D <&ipcc IPCC_MPROC_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem =3D <443>, <429>; + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-cdsp { + compatible =3D "qcom,smp2p"; + + interrupts-extended =3D <&ipcc IPCC_MPROC_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes =3D <&ipcc IPCC_MPROC_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem =3D <94>, <432>; + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <5>; + + smp2p_cdsp_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_cdsp_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + soc: soc@0 { compatible =3D "simple-bus"; =20 @@ -2478,6 +2530,111 @@ tcsr: clock-controller@1fc0000 { #reset-cells =3D <1>; }; =20 + remoteproc_adsp: remoteproc@6800000 { + compatible =3D "qcom,kaanapali-adsp-pas", "qcom,sm8550-adsp-pas"; + reg =3D <0x0 0x06800000 0x0 0x10000>; + + interrupts-extended =3D <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + interconnects =3D <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWA= YS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + power-domains =3D <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; + power-domain-names =3D "lcx", + "lmx"; + + memory-region =3D <&adspslpi_mem>, <&q6_adsp_dtb_mem>; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&smp2p_adsp_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + remoteproc_adsp_glink: glink-edge { + interrupts-extended =3D <&ipcc IPCC_MPROC_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes =3D <&ipcc IPCC_MPROC_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + qcom,remote-pid =3D <2>; + + label =3D "lpass"; + + fastrpc { + compatible =3D "qcom,kaanapali-fastrpc"; + qcom,glink-channels =3D "fastrpcglink-apps-dsp"; + label =3D "adsp"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + compute-cb@3 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <3>; + + iommus =3D <&apps_smmu 0x1003 0x80>, + <&apps_smmu 0x1043 0x20>; + dma-coherent; + }; + + compute-cb@4 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <4>; + + iommus =3D <&apps_smmu 0x1004 0x80>, + <&apps_smmu 0x1044 0x20>; + dma-coherent; + }; + + compute-cb@5 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <5>; + + iommus =3D <&apps_smmu 0x1005 0x80>, + <&apps_smmu 0x1045 0x20>; + dma-coherent; + }; + + compute-cb@6 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <6>; + + iommus =3D <&apps_smmu 0x1006 0x80>, + <&apps_smmu 0x1046 0x20>; + dma-coherent; + }; + + compute-cb@7 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <7>; + + iommus =3D <&apps_smmu 0x1007 0x40>, + <&apps_smmu 0x1067 0x0>, + <&apps_smmu 0x1087 0x0>; + dma-coherent; + }; + }; + }; + }; + lpass_lpiaon_noc: interconnect@7400000 { compatible =3D "qcom,kaanapali-lpass-lpiaon-noc"; reg =3D <0x0 0x07400000 0x0 0x19080>; @@ -4760,6 +4917,163 @@ nsp_noc: interconnect@260c0000 { #interconnect-cells =3D <2>; }; =20 + remoteproc_cdsp: remoteproc@26300000 { + compatible =3D "qcom,kaanapali-cdsp-pas", "qcom,sm8550-cdsp-pas"; + reg =3D <0x0 0x26300000 0x0 0x10000>; + + interrupts-extended =3D <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + interconnects =3D <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + power-domains =3D <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_NSP>; + power-domain-names =3D "cx", + "mxc", + "nsp"; + + memory-region =3D <&cdsp_mem>, <&q6_cdsp_dtb_mem>; + qcom,qmp =3D <&aoss_qmp>; + qcom,smem-states =3D <&smp2p_cdsp_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + glink-edge { + interrupts-extended =3D <&ipcc IPCC_MPROC_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_MPROC_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + qcom,remote-pid =3D <5>; + label =3D "cdsp"; + + fastrpc { + compatible =3D "qcom,kaanapali-fastrpc"; + qcom,glink-channels =3D "fastrpcglink-apps-dsp"; + label =3D "cdsp"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + compute-cb@1 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <1>; + iommus =3D <&apps_smmu 0x19c1 0x0>, + <&apps_smmu 0x1961 0x0>, + <&apps_smmu 0x0c21 0x0>, + <&apps_smmu 0x0c01 0x40>; + dma-coherent; + }; + + compute-cb@2 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <2>; + iommus =3D <&apps_smmu 0x1962 0x0>, + <&apps_smmu 0x0c02 0x20>, + <&apps_smmu 0x0c42 0x0>, + <&apps_smmu 0x19c2 0x0>; + dma-coherent; + }; + + compute-cb@3 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <3>; + iommus =3D <&apps_smmu 0x1963 0x0>, + <&apps_smmu 0x0c23 0x0>, + <&apps_smmu 0x0c03 0x40>, + <&apps_smmu 0x19c3 0x0>; + dma-coherent; + }; + + compute-cb@4 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <4>; + iommus =3D <&apps_smmu 0x1964 0x0>, + <&apps_smmu 0x0c44 0x0>, + <&apps_smmu 0x0c04 0x20>, + <&apps_smmu 0x19c4 0x0>; + dma-coherent; + }; + + compute-cb@5 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <5>; + iommus =3D <&apps_smmu 0x1965 0x0>, + <&apps_smmu 0x0c45 0x0>, + <&apps_smmu 0x0c05 0x20>, + <&apps_smmu 0x19c5 0x0>; + dma-coherent; + }; + + compute-cb@6 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <6>; + iommus =3D <&apps_smmu 0x1966 0x0>, + <&apps_smmu 0x0c06 0x20>, + <&apps_smmu 0x0c46 0x0>, + <&apps_smmu 0x19c6 0x0>; + dma-coherent; + }; + + compute-cb@7 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <7>; + iommus =3D <&apps_smmu 0x1967 0x0>, + <&apps_smmu 0x0c27 0x0>, + <&apps_smmu 0x0c07 0x40>, + <&apps_smmu 0x19c7 0x0>; + dma-coherent; + }; + + compute-cb@8 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <8>; + iommus =3D <&apps_smmu 0x1968 0x0>, + <&apps_smmu 0x0c08 0x20>, + <&apps_smmu 0x0c48 0x0>, + <&apps_smmu 0x19c8 0x0>; + dma-coherent; + }; + + compute-cb@12 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <12>; + iommus =3D <&apps_smmu 0x196c 0x0>, + <&apps_smmu 0x0c2c 0x00>, + <&apps_smmu 0x0c0c 0x40>, + <&apps_smmu 0x19cc 0x0>; + dma-coherent; + }; + + compute-cb@13 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <13>; + iommus =3D <&apps_smmu 0x196d 0x0>, + <&apps_smmu 0x0c0d 0x40>, + <&apps_smmu 0x0c2e 0x0>, + <&apps_smmu 0x0c2d 0x0>, + <&apps_smmu 0x19cd 0x0>; + dma-coherent; + }; + }; + }; + }; + /* Cluster 0 */ pmu@310b3400 { compatible =3D "qcom,kaanapali-cpu-bwmon", "qcom,sdm845-bwmon"; --=20 2.25.1 From nobody Sun Feb 8 10:33:44 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4AD836CDEB for ; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b8283def01sm417499eec.34.2026.02.02.22.06.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Feb 2026 22:06:34 -0800 (PST) From: Jingyi Wang Date: Mon, 02 Feb 2026 22:06:22 -0800 Subject: [PATCH v5 05/10] arm64: dts: qcom: kaanapali: Add support for audio Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260202-knp-dts-misc-v5-5-02de82bf9901@oss.qualcomm.com> References: <20260202-knp-dts-misc-v5-0-02de82bf9901@oss.qualcomm.com> In-Reply-To: <20260202-knp-dts-misc-v5-0-02de82bf9901@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jingyi Wang , 20260114-knp-remoteproc-v4-0-fcf0b04d01af@oss.qualcomm.com, Prasad Kumpatla , Konrad Dybcio , Abel Vesa X-Mailer: b4 0.15-dev-3d134 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770098787; l=13571; i=jingyi.wang@oss.qualcomm.com; s=20250911; h=from:subject:message-id; bh=FN/C0JgEfkUGxO0ScMaU8W8gbfqsrDP9YrR20hfWJV8=; b=quNaBUhSPaHVTraGSoJUM3poyJAiCqmvT6ueTfDsTPt7C5GEtQ6ERNoohOca555O5KNOvdmIU We0xL6bx3TaCqG9f45KRUCQY0PG8TpYjndAe2jWNDRPTP7FVm6V/oeD X-Developer-Key: i=jingyi.wang@oss.qualcomm.com; a=ed25519; pk=PSoHZ6KbUss3IW8FPRVMHMK0Jkkr/jV347mBYJO3iLo= X-Authority-Analysis: v=2.4 cv=Xb6EDY55 c=1 sm=1 tr=0 ts=6981906c cx=c_pps a=SvEPeNj+VMjHSW//kvnxuw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=fOvlSJoLLuNaJOMVFRMA:9 a=QEXdDO2ut3YA:10 a=Kq8ClHjjuc5pcCNDwlU0:22 X-Proofpoint-ORIG-GUID: Mh4ZT63NybfALOvSy7DAtuuYBFBCbvL1 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjAzMDA0NyBTYWx0ZWRfX99AQnuOGE5uO CLDGugfltWpxFZLEw0bqF2KJPpKbLV0I1fqE7KmysRtphcRAzidm4RmAcY5hOa59i/LsWxgUGpu qPkf4l/b6Vl9/mQXKAVnSLB5IMK2Pg79N7DQ2Y0X8hb3XijnkwyMNZoujSyjVm3ujh3vWJyG4pQ 71tYHhqGGYQcUaA8hwV8VzvnJVNMuM38tkct382kafNvzxmDvv2AZZvHO/xWIuYCWnViuyGzZAb KvjTch7VmOYtAQUgf+h8zDSO4Bo/CJUvT/2zkH9YjYcNPwboXSzHjyEO0pbzXLK6yMFaBtVqz0Q 8AOczSPVe5e1x1YPB3/6F3kHSsz4tNnXEaZAkBF1gJkX3QjvL7tMa96MiUG8VN7bEA6hAXynQpI hq1aQa8egg+HW+Wh0s/ePYZMQLf0yV+qNO5XCxjL/zPRobHSCQOY6uVUYIZRQSoAOrJjIcs/MQW 4rk7GGhHncp3UerbPzw== X-Proofpoint-GUID: Mh4ZT63NybfALOvSy7DAtuuYBFBCbvL1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-03_01,2026-02-02_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 phishscore=0 adultscore=0 suspectscore=0 bulkscore=0 impostorscore=0 malwarescore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602030047 From: Prasad Kumpatla Introduce audio support for Kaanapali SoC by adding LPASS macro codecs, TLMM pin controller and SoundWire controller with similar hardware implementation to SM8750 platform. Also add GPR (Generic Pack Router) node along with support for APM (Audio Process Manager) and PRM (Proxy Resource Manager) audio services. Signed-off-by: Prasad Kumpatla Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 367 ++++++++++++++++++++++++++++= ++++ 1 file changed, 367 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/= qcom/kaanapali.dtsi index c8f61200f261..050d47691f5c 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -16,7 +16,9 @@ #include #include #include +#include #include +#include =20 #include "kaanapali-ipcc.h" =20 @@ -2632,6 +2634,371 @@ compute-cb@7 { dma-coherent; }; }; + + gpr { + compatible =3D "qcom,gpr"; + qcom,glink-channels =3D "adsp_apps"; + qcom,domain =3D ; + qcom,intents =3D <512 20>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + q6apm: service@1 { + compatible =3D "qcom,q6apm"; + reg =3D ; + #sound-dai-cells =3D <0>; + qcom,protection-domain =3D "avs/audio", + "msm/adsp/audio_pd"; + + q6apmbedai: bedais { + compatible =3D "qcom,q6apm-lpass-dais"; + #sound-dai-cells =3D <1>; + }; + + q6apmdai: dais { + compatible =3D "qcom,q6apm-dais"; + iommus =3D <&apps_smmu 0x1001 0x80>, + <&apps_smmu 0x1041 0x20>; + }; + }; + + q6prm: service@2 { + compatible =3D "qcom,q6prm"; + reg =3D ; + qcom,protection-domain =3D "avs/audio", + "msm/adsp/audio_pd"; + + q6prmcc: clock-controller { + compatible =3D "qcom,q6prm-lpass-clocks"; + #clock-cells =3D <2>; + }; + }; + }; + }; + }; + + lpass_wsa2macro: codec@6aa0000 { + compatible =3D "qcom,kaanapali-lpass-wsa-macro", + "qcom,sm8550-lpass-wsa-macro"; + reg =3D <0x0 0x06aa0000 0x0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names =3D "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells =3D <0>; + clock-output-names =3D "wsa2-mclk"; + #sound-dai-cells =3D <1>; + }; + + swr3: soundwire@6ab0000 { + compatible =3D "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0"; + reg =3D <0 0x06ab0000 0 0x10000>; + interrupts =3D ; + clocks =3D <&lpass_wsa2macro>; + clock-names =3D "iface"; + label =3D "WSA2"; + + pinctrl-0 =3D <&wsa2_swr_active>; + pinctrl-names =3D "default"; + + qcom,din-ports =3D <4>; + qcom,dout-ports =3D <9>; + + qcom,ports-sinterval =3D /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18= f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; + qcom,ports-offset1 =3D /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0x= ff 0xff 0x06 0x0d 0xff 0x00>; + qcom,ports-offset2 =3D /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0x= ff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xf= f 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff= 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-word-length =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08= 0xff 0xff 0xff 0xff 0xff 0x18>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 = 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff 0xff 0xff 0xff 0xff>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + #sound-dai-cells =3D <1>; + status =3D "disabled"; + }; + + lpass_rxmacro: codec@6ac0000 { + compatible =3D "qcom,kaanapali-lpass-rx-macro", "qcom,sm8550-lpass-rx-m= acro"; + reg =3D <0x0 0x06ac0000 0x0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names =3D "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells =3D <0>; + clock-output-names =3D "mclk"; + #sound-dai-cells =3D <1>; + }; + + swr1: soundwire@6ad0000 { + compatible =3D "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0"; + reg =3D <0 0x06ad0000 0 0x10000>; + interrupts =3D ; + clocks =3D <&lpass_rxmacro>; + clock-names =3D "iface"; + label =3D "RX"; + + pinctrl-0 =3D <&rx_swr_active>; + pinctrl-names =3D "default"; + + qcom,din-ports =3D <1>; + qcom,dout-ports =3D <11>; + + qcom,ports-sinterval =3D /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xf= f 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-offset1 =3D /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0x= ff 0xff 0xff 0xff 0xff>; + qcom,ports-offset2 =3D /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0x= ff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xf= f 0xff 0xff 0xff 0xff>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff= 0xff 0xff 0xff 0xff>; + qcom,ports-word-length =3D /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff= 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 = 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x0= 0 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xf= f 0xff 0xff 0xff 0xff 0xff>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + #sound-dai-cells =3D <1>; + status =3D "disabled"; + }; + + lpass_txmacro: codec@6ae0000 { + compatible =3D "qcom,kaanapali-lpass-tx-macro", "qcom,sm8550-lpass-tx-m= acro"; + reg =3D <0x0 0x06ae0000 0x0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUP= LE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names =3D "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells =3D <0>; + clock-output-names =3D "mclk"; + #sound-dai-cells =3D <1>; + }; + + lpass_wsamacro: codec@6b00000 { + compatible =3D "qcom,kaanapali-lpass-wsa-macro", + "qcom,sm8550-lpass-wsa-macro"; + reg =3D <0x0 0x06b00000 0x0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names =3D "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells =3D <0>; + clock-output-names =3D "mclk"; + #sound-dai-cells =3D <1>; + }; + + swr0: soundwire@6b10000 { + compatible =3D "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0"; + reg =3D <0 0x06b10000 0 0x10000>; + interrupts =3D ; + clocks =3D <&lpass_wsamacro>; + clock-names =3D "iface"; + label =3D "WSA"; + + pinctrl-0 =3D <&wsa_swr_active>; + pinctrl-names =3D "default"; + + qcom,din-ports =3D <4>; + qcom,dout-ports =3D <9>; + + qcom,ports-sinterval =3D /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18= f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; + qcom,ports-offset1 =3D /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0x= ff 0xff 0x06 0x0d 0xff 0x00>; + qcom,ports-offset2 =3D /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0x= ff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xf= f 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff= 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-word-length =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08= 0xff 0xff 0xff 0xff 0xff 0x18>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 = 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff 0xff 0xff 0xff 0xff>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + #sound-dai-cells =3D <1>; + status =3D "disabled"; + }; + + swr2: soundwire@7630000 { + compatible =3D "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0"; + reg =3D <0 0x07630000 0 0x10000>; + interrupts-extended =3D <&intc GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 40 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "core", "wakeup"; + clocks =3D <&lpass_txmacro>; + clock-names =3D "iface"; + label =3D "TX"; + + pinctrl-0 =3D <&tx_swr_active>; + pinctrl-names =3D "default"; + + qcom,din-ports =3D <4>; + qcom,dout-ports =3D <0>; + qcom,ports-sinterval-low =3D /bits/ 8 <0x01 0x01 0x03 0x03>; + qcom,ports-offset1 =3D /bits/ 8 <0x00 0x00 0x01 0x01>; + qcom,ports-offset2 =3D /bits/ 8 <0x00 0x00 0x00 0x00>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-word-length =3D /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0x01 0x02 0x00 0x00>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + #sound-dai-cells =3D <1>; + status =3D "disabled"; + }; + + lpass_vamacro: codec@7660000 { + compatible =3D "qcom,kaanapali-lpass-va-macro", "qcom,sm8550-lpass-va-m= acro"; + reg =3D <0 0x07660000 0 0x2000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUP= LE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names =3D "mclk", "macro", "dcodec"; + + #clock-cells =3D <0>; + clock-output-names =3D "fsgen"; + #sound-dai-cells =3D <1>; + }; + + lpass_tlmm: pinctrl@7760000 { + compatible =3D "qcom,sm8750-lpass-lpi-pinctrl", + "qcom,sm8650-lpass-lpi-pinctrl"; + reg =3D <0 0x07760000 0 0x20000>; + + clocks =3D <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names =3D "core", "audio"; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&lpass_tlmm 0 0 23>; + + tx_swr_active: tx-swr-active-state { + clk-pins { + pins =3D "gpio0"; + function =3D "swr_tx_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio1", "gpio2", "gpio14"; + function =3D "swr_tx_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + rx_swr_active: rx-swr-active-state { + clk-pins { + pins =3D "gpio3"; + function =3D "swr_rx_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio4", "gpio5"; + function =3D "swr_rx_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + dmic01_default: dmic01-default-state { + clk-pins { + pins =3D "gpio6"; + function =3D "dmic1_clk"; + drive-strength =3D <8>; + output-high; + }; + + data-pins { + pins =3D "gpio7"; + function =3D "dmic1_data"; + drive-strength =3D <8>; + input-enable; + }; + }; + + dmic23_default: dmic23-default-state { + clk-pins { + pins =3D "gpio8"; + function =3D "dmic2_clk"; + drive-strength =3D <8>; + output-high; + }; + + data-pins { + pins =3D "gpio9"; + function =3D "dmic2_data"; + drive-strength =3D <8>; + input-enable; + }; + }; + + wsa_swr_active: wsa-swr-active-state { + clk-pins { + pins =3D "gpio10"; + function =3D "wsa_swr_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio11"; + function =3D "wsa_swr_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; 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Reviewed-by: Dmitry Baryshkov Reviewed-by: Abel Vesa Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/d= ts/qcom/kaanapali-mtp.dts index 32a082598434..3544f744fd1d 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts @@ -684,6 +684,20 @@ &pcie_port0 { reset-gpios =3D <&tlmm 102 GPIO_ACTIVE_LOW>; }; =20 +&remoteproc_adsp { + firmware-name =3D "qcom/kaanapali/adsp.mbn", + "qcom/kaanapali/adsp_dtb.mbn"; + + status =3D "okay"; +}; + +&remoteproc_cdsp { + firmware-name =3D "qcom/kaanapali/cdsp.mbn", + "qcom/kaanapali/cdsp_dtb.mbn"; + + status =3D "okay"; +}; + &sdhc_2 { cd-gpios =3D <&tlmm 55 GPIO_ACTIVE_LOW>; =20 --=20 2.25.1 From nobody Sun Feb 8 10:33:44 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6AF036AB53 for ; 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Reviewed-by: Dmitry Baryshkov Reviewed-by: Abel Vesa Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/kaanapali-qrd.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts b/arch/arm64/boot/d= ts/qcom/kaanapali-qrd.dts index 66b423a497b3..32034eed03eb 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts @@ -682,6 +682,20 @@ &sdhc_2 { status =3D "okay"; }; =20 +&remoteproc_adsp { + firmware-name =3D "qcom/kaanapali/adsp.mbn", + "qcom/kaanapali/adsp_dtb.mbn"; + + status =3D "okay"; +}; + +&remoteproc_cdsp { + firmware-name =3D "qcom/kaanapali/cdsp.mbn", + "qcom/kaanapali/cdsp_dtb.mbn"; + + status =3D "okay"; +}; + &tlmm { gpio-reserved-ranges =3D <36 4>, /* NFC eSE SPI */ <74 1>, /* eSE */ --=20 2.25.1 From nobody Sun Feb 8 10:33:44 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E8C2B36D50D for ; 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The WCD9395 codec is add to supply MIC-BIAS, for enabling onboard microphone capture. Signed-off-by: Prasad Kumpatla Reviewed-by: Konrad Dybcio Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 226 +++++++++++++++++++++++++= ++++ 1 file changed, 226 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/d= ts/qcom/kaanapali-mtp.dts index 3544f744fd1d..bc57935c042c 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts @@ -52,6 +52,115 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { clock-div =3D <2>; }; }; + + sound { + compatible =3D "qcom,kaanapali-sndcard", "qcom,sm8450-sndcard"; + model =3D "Kaanapali-MTP"; + + audio-routing =3D "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS1", + "VA DMIC1", "MIC BIAS1", + "VA DMIC2", "MIC BIAS3", + "VA DMIC3", "MIC BIAS3", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + va-dai-link { + link-name =3D "VA Capture"; + + codec { + sound-dai =3D <&lpass_vamacro 0>; + }; + + cpu { + sound-dai =3D <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name =3D "WCD Capture"; + + codec { + sound-dai =3D <&wcd939x 1>, <&swr2 0>, <&lpass_txmacro 0>; + }; + + cpu { + sound-dai =3D <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + + wcd-playback-dai-link { + link-name =3D "WCD Playback"; + + codec { + sound-dai =3D <&wcd939x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + cpu { + sound-dai =3D <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + + wsa-dai-link { + link-name =3D "WSA Playback"; + + codec { + sound-dai =3D <&north_spkr>, <&south_spkr>, <&swr0 0>, + <&lpass_wsamacro 0>; + }; + + cpu { + sound-dai =3D <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + }; + + wcd939x: audio-codec { + compatible =3D "qcom,wcd9395-codec", "qcom,wcd9390-codec"; + + pinctrl-0 =3D <&wcd_default>; + pinctrl-names =3D "default"; + + qcom,micbias1-microvolt =3D <1800000>; + qcom,micbias2-microvolt =3D <1800000>; + qcom,micbias3-microvolt =3D <1800000>; + qcom,micbias4-microvolt =3D <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt =3D <75000 150000 237000 500000 + 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt =3D <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt =3D <50000>; + qcom,rx-device =3D <&wcd_rx>; + qcom,tx-device =3D <&wcd_tx>; + + reset-gpios =3D <&tlmm 161 GPIO_ACTIVE_LOW>; + + vdd-buck-supply =3D <&vreg_l15b_1p8>; + vdd-rxtx-supply =3D <&vreg_l15b_1p8>; + vdd-io-supply =3D <&vreg_l15b_1p8>; + vdd-mic-bias-supply =3D <&vreg_bob1>; + vdd-px-supply =3D <&vreg_l1g_1p2>; + + #sound-dai-cells =3D <1>; + }; }; =20 &apps_rsc { @@ -665,6 +774,14 @@ vreg_l7n_3p3: ldo7 { }; }; =20 +&lpass_vamacro { + pinctrl-0 =3D <&dmic01_default>, <&dmic23_default>; + pinctrl-names =3D "default"; + + vdd-micb-supply =3D <&vreg_l10b_1p8>; + qcom,dmic-sample-rate =3D <4800000>; +}; + &pcie0 { pinctrl-0 =3D <&pcie0_default_state>; pinctrl-names =3D "default"; @@ -715,12 +832,114 @@ &sdhc_2 { status =3D "okay"; }; =20 +&swr0 { + status =3D "okay"; + + /* WSA8845, Speaker North */ + north_spkr: speaker@0,0 { + compatible =3D "sdw20217020400"; + reg =3D <0 0>; + pinctrl-0 =3D <&spkr_0_sd_n_active>; + pinctrl-names =3D "default"; + powerdown-gpios =3D <&tlmm 76 GPIO_ACTIVE_LOW>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "SpkrLeft"; + vdd-1p8-supply =3D <&vreg_l15b_1p8>; + vdd-io-supply =3D <&vreg_l2i_1p2>; + + /* + * WSA8845 Port 1 (DAC) <=3D> SWR0 Port 1 (SPKR_L) + * WSA8845 Port 2 (COMP) <=3D> SWR0 Port 2 (SPKR_L_COMP) + * WSA8845 Port 3 (BOOST) <=3D> SWR0 Port 3 (SPKR_L_BOOST) + * WSA8845 Port 4 (PBR) <=3D> SWR0 Port 7 (PBR) + * WSA8845 Port 5 (VISENSE) <=3D> SWR0 Port 10 (SPKR_L_VI) + * WSA8845 Port 6 (CPS) <=3D> SWR0 Port 13 (CPS) + */ + qcom,port-mapping =3D <1 2 3 7 10 13>; + }; + + /* WSA8845, Speaker South */ + south_spkr: speaker@0,1 { + compatible =3D "sdw20217020400"; + reg =3D <0 1>; + pinctrl-0 =3D <&spkr_1_sd_n_active>; + pinctrl-names =3D "default"; + powerdown-gpios =3D <&tlmm 77 GPIO_ACTIVE_LOW>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "SpkrRight"; + vdd-1p8-supply =3D <&vreg_l15b_1p8>; + vdd-io-supply =3D <&vreg_l2i_1p2>; + + /* + * WSA8845 Port 1 (DAC) <=3D> SWR0 Port 4 (SPKR_R) + * WSA8845 Port 2 (COMP) <=3D> SWR0 Port 5 (SPKR_R_COMP) + * WSA8845 Port 3 (BOOST) <=3D> SWR0 Port 6 (SPKR_R_BOOST) + * WSA8845 Port 4 (PBR) <=3D> SWR0 Port 7 (PBR) + * WSA8845 Port 5 (VISENSE) <=3D> SWR0 Port 11 (SPKR_R_VI) + * WSA8845 Port 6 (CPS) <=3D> SWR0 Port 13 (CPS) + */ + qcom,port-mapping =3D <4 5 6 7 11 13>; + }; +}; + +&swr1 { + status =3D "okay"; + + /* WCD9395 RX */ + wcd_rx: codec@0,4 { + compatible =3D "sdw20217010e00"; + reg =3D <0 4>; + + /* + * WCD9395 RX Port 1 (HPH_L/R) <=3D> SWR1 Port 1 (HPH_L/R) + * WCD9395 RX Port 2 (CLSH) <=3D> SWR1 Port 2 (CLSH) + * WCD9395 RX Port 3 (COMP_L/R) <=3D> SWR1 Port 3 (COMP_L/R) + * WCD9395 RX Port 4 (LO) <=3D> SWR1 Port 4 (LO) + * WCD9395 RX Port 5 (DSD_L/R) <=3D> SWR1 Port 5 (DSD_L/R) + * WCD9395 RX Port 6 (HIFI_PCM_L/R) <=3D> SWR1 Port 9 (HIFI_PCM_L/R) + */ + qcom,rx-port-mapping =3D <1 2 3 4 5 9>; + }; +}; + +&swr2 { + status =3D "okay"; + + /* WCD9395 TX */ + wcd_tx: codec@0,3 { + compatible =3D "sdw20217010e00"; + reg =3D <0 3>; + + /* + * WCD9395 TX Port 1 (ADC1,2,3,4) <=3D> SWR2 Port 2 (TX SWR_INPU= T 0,1,2,3) + * WCD9395 TX Port 2 (ADC3,4 & DMIC0,1) <=3D> SWR2 Port 2 (TX SWR_INPU= T 0,1,2,3) + * WCD9395 TX Port 3 (DMIC0,1,2,3 & MBHC) <=3D> SWR2 Port 3 (TX SWR_INPU= T 4,5,6,7) + * WCD9395 TX Port 4 (DMIC4,5,6,7) <=3D> SWR2 Port 4 (TX SWR_INPU= T 8,9,10,11) + */ + qcom,tx-port-mapping =3D <2 2 3 4>; + }; +}; + &tlmm { gpio-reserved-ranges =3D <36 4>, /* NFC eSE SPI */ <74 1>, /* eSE */ <119 2>, /* SoCCP */ <144 4>; /* CXM UART */ =20 + spkr_0_sd_n_active: spkr-0-sd-n-active-state { + pins =3D "gpio76"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + }; + + spkr_1_sd_n_active: spkr-1-sd-n-active-state { + pins =3D "gpio77"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + }; + pcie0_default_state: pcie0-default-state { perst-n-pins { pins =3D "gpio102"; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b8283def01sm417499eec.34.2026.02.02.22.06.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Feb 2026 22:06:40 -0800 (PST) From: Jingyi Wang Date: Mon, 02 Feb 2026 22:06:26 -0800 Subject: [PATCH v5 09/10] arm64: dts: qcom: kaanapali: Add support for MM clock controllers for Kaanapali Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260202-knp-dts-misc-v5-9-02de82bf9901@oss.qualcomm.com> References: <20260202-knp-dts-misc-v5-0-02de82bf9901@oss.qualcomm.com> In-Reply-To: <20260202-knp-dts-misc-v5-0-02de82bf9901@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jingyi Wang , 20260114-knp-remoteproc-v4-0-fcf0b04d01af@oss.qualcomm.com, Taniya Das , Konrad Dybcio , Abel Vesa X-Mailer: b4 0.15-dev-3d134 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770098787; l=4559; i=jingyi.wang@oss.qualcomm.com; s=20250911; h=from:subject:message-id; bh=V8klYJcTlCA0XXPc7b6wczy0KpOL9nFdZCIXVz7dVR8=; b=FKKu39p50DwCp0ka35XVW2kfs65wOudb7bNZhS2NB7BqFTW6s/K6lfOyY99F3hXL0WS/P29g4 62OObZZ1szPBD9mU1qwtgKuRd2Mb/N14tkPvHflXQp43OGSdY01sSPY X-Developer-Key: i=jingyi.wang@oss.qualcomm.com; a=ed25519; pk=PSoHZ6KbUss3IW8FPRVMHMK0Jkkr/jV347mBYJO3iLo= X-Proofpoint-ORIG-GUID: ZeCkoPnudGzl1OBMIpgHaIV2eELYM2aW X-Authority-Analysis: v=2.4 cv=dcmNHHXe c=1 sm=1 tr=0 ts=69819072 cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=Y3HLYP14RHR0fgYgac8A:9 a=QEXdDO2ut3YA:10 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-GUID: ZeCkoPnudGzl1OBMIpgHaIV2eELYM2aW X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjAzMDA0NyBTYWx0ZWRfXxMJDOKG0kwot xkgqaKxzTYaxG4VLACOvfbJTVBVgVHKwmAgJ6baHAx97AfWSbSE9yL3k5jETD//Z4ONEQQG+mOB AsHsNqCz5zxVe2Rf+sXyNj7xwMmeliMbsCXAHoHxdoWtKbtp2EOsi/LPqC8Ip60qe5boGl0YPpD YQ/+zOBJpRqNKQjB1cNK9ZwbdfDYy1DenyuQ1uz8+ZewKXsDcfkOcYyrgjk/bFwRZAKGhUFN3/G 8mN82mkt1jsXI6rK140sGIrlpqwPeizSWG2MZtJG+SpHXr/SdJEEDxx6jZe1KidxduDXJz6sGwM e0QXye9yDUZP8NVC5NRtaSKv9ATj6DQjL6vw1nOOdeHnXguaSpzkMMTRYq50ru2GnAlzM9l82PU xgXAsBCPSOR8E9uJsO5gNZWuJlyau9dhZunuz3eIoWSk5HWqTRLzkdKrRwktz0aiPmkxUuW9Y36 vn/9lry1nTXf//9HSRg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-03_01,2026-02-02_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602030047 From: Taniya Das Add the device nodes for the multimedia clock controllers (cambistmclkcc, camcc, dispcc, videocc, gpucc and gxclkctl). Signed-off-by: Taniya Das Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Signed-off-by: Jingyi Wang --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 111 ++++++++++++++++++++++++++++= ++++ 1 file changed, 111 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/= qcom/kaanapali.dtsi index 050d47691f5c..08d098c1f5af 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -3,7 +3,13 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ =20 +#include +#include +#include #include +#include +#include +#include #include #include #include @@ -1557,6 +1563,24 @@ aggre_noc: interconnect@16e0000 { <&rpmhcc RPMH_IPA_CLK>; }; =20 + cambistmclkcc: clock-controller@1760000 { + compatible =3D "qcom,kaanapali-cambistmclkcc"; + reg =3D <0x0 0x01760000 0x0 0x8000>; + + clocks =3D <&gcc GCC_CAM_BIST_MCLK_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MX>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + mmss_noc: interconnect@1780000 { compatible =3D "qcom,kaanapali-mmss-noc"; reg =3D <0x0 0x01780000 0x0 0x5b800>; @@ -2532,6 +2556,46 @@ tcsr: clock-controller@1fc0000 { #reset-cells =3D <1>; }; =20 + videocc: clock-controller@20f0000 { + compatible =3D "qcom,kaanapali-videocc"; + reg =3D <0x0 0x020f0000 0x0 0x10000>; + clocks =3D <&bi_tcxo_div2>, + <&gcc GCC_VIDEO_AHB_CLK>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + gxclkctl: clock-controller@3d64000 { + compatible =3D "qcom,kaanapali-gxclkctl"; + reg =3D <0x0 0x03d64000 0x0 0x6000>; + + power-domains =3D <&rpmhpd RPMHPD_GFX>, + <&rpmhpd RPMHPD_GMXC>, + <&gpucc GPU_CC_CX_GDSC>; + + #power-domain-cells =3D <1>; + }; + + gpucc: clock-controller@3d90000 { + compatible =3D "qcom,kaanapali-gpucc"; + reg =3D <0x0 0x03d90000 0x0 0x9800>; + + clocks =3D <&bi_tcxo_div2>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + remoteproc_adsp: remoteproc@6800000 { compatible =3D "qcom,kaanapali-adsp-pas", "qcom,sm8550-adsp-pas"; reg =3D <0x0 0x06800000 0x0 0x10000>; @@ -3073,6 +3137,53 @@ opp-202000000 { }; }; =20 + camcc: clock-controller@956d000 { + compatible =3D "qcom,kaanapali-camcc"; + reg =3D <0x0 0x0956d000 0x0 0x80000>; + + clocks =3D <&gcc GCC_CAMERA_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + dispcc: clock-controller@9ba2000 { + compatible =3D "qcom,kaanapali-dispcc"; + reg =3D <0x0 0x09ba2000 0x0 0x20000>; + clocks =3D <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&gcc GCC_DISP_AHB_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; 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Signed-off-by: Taniya Das Reviewed-by: Abel Vesa Signed-off-by: Jingyi Wang --- arch/arm64/configs/defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 7a6d7e70d383..66ba440d0123 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1454,8 +1454,12 @@ CONFIG_COMMON_CLK_MT8192_SCP_ADSP=3Dy CONFIG_COMMON_CLK_MT8192_VDECSYS=3Dy CONFIG_COMMON_CLK_MT8192_VENCSYS=3Dy CONFIG_COMMON_CLK_QCOM=3Dy +CONFIG_CLK_KAANAPALI_CAMCC=3Dm +CONFIG_CLK_KAANAPALI_DISPCC=3Dm CONFIG_CLK_KAANAPALI_GCC=3Dy +CONFIG_CLK_KAANAPALI_GPUCC=3Dm CONFIG_CLK_KAANAPALI_TCSRCC=3Dm +CONFIG_CLK_KAANAPALI_VIDEOCC=3Dm CONFIG_CLK_X1E80100_CAMCC=3Dm CONFIG_CLK_X1E80100_DISPCC=3Dm CONFIG_CLK_X1E80100_GCC=3Dy --=20 2.25.1