From nobody Sat Feb 7 09:42:38 2026 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 357D62BE639 for ; Sun, 1 Feb 2026 19:18:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769973498; cv=none; b=r93dY/36cQyC/vvtSvv9nWxVb3hzgwk0dD0DkS1sHH0uzOs7MNdPaNyUagJSgHeAK5GhhVh4A+eFmWvg9QpEJNpwvSqQ1VN/bPmrZrfLd3XWWVKwbwTE7aqfAl74B/1+EyQt59UqaQ/C4LOZswvvzaGvKv45JltppdDnXWfrkg8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769973498; c=relaxed/simple; bh=HdKjCKYkTUBYWymGVGhnDiISEbQfe6n6+Fjw7/9Oc7s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=AeQpPL3iapTqTqq24KTWLQAmpjHSEJbW1YfB0rX4n4N2TdR4xBQ68YAhR89Cf4Y5bIEV2UhF0cJgIdAQSkWAVF8FpGYAh1CGV9AXlBC+lviPI5ha81kqGp51vU4IsBuMnUIFu9nEQtxT7Qw9AH9R7mDGtLEYaDiILA7WKb+wjXo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=WMeS+fpL; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="WMeS+fpL" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type; bh=zcDBvht1tN7pQSi0T0aBge/reb5eHegqZJLItDNrtYc=; b=WMeS+fpL0Uel8Z4zAfqaUoRggc 2N/TjQ554k0NgIQUhtBzcBt2mYbrS6uQPfJLnkHDq4LlffQk9H6tL89mf0Wwd4wCGQOHYTLp792La AY4sNdeIt51iEkl4t4ek4HgecZmKV+OrCZdgVwlGf3dOARwbOlfVRoVB+HMlvFif9QwaD+NmBaz+y VzMOcsv5HJUQnrvkkoLcj1zqEhWfllBo6QI7e9GxO246SJBnC+V7VnWaqjw3wwzvu5Fks2OSwqL01 MyHPqYxzzDvUaM8vENCt/sN9OnsfgvmHPPBNe0JODISrpPFSG3jOiv/+/fXdNe8b7DnclUkYH1uOr zpIRTm0g==; Received: from [88.128.88.21] (helo=phil.t-mobile.de) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1vmcxT-005wWz-AR; Sun, 01 Feb 2026 20:18:07 +0100 From: Heiko Stuebner To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/4] arm64: dts: rockchip: add overlay for qnap-ts433 device revision Date: Sun, 1 Feb 2026 20:18:02 +0100 Message-ID: <20260201191804.41421-3-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20260201191804.41421-1-heiko@sntech.de> References: <20260201191804.41421-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" TS433 devices received a board revision adding gpios for per hard-disk presence-detection and power-control. These board have a PCB-id of at least 12 (mainboard) and 10 (backplane), which can be read from an EEPROM. The presence detection is not really necessary and there are also no existing bindings for doing something with it. So add them as gpio hogs to at least document them and allow their state to be read from debugfs. The power-control is modelled as regulators, with the hdd1+hdd2 variants connected to the RK3568's SATA controllers as target-supplies. The JMicron AHCI controller on PCIe didn't have bindings for that, I could find, so they get an always-on state for now. Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 5 + .../rockchip/rk3568-qnap-ts433-pcb-12-10.dtso | 151 ++++++++++++++++++ 2 files changed, 156 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433-pcb-12-1= 0.dtso diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index d0f22d3a3bb4..aafffecfb2ef 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -145,6 +145,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-odroid-m1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-photonicat.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-qnap-ts233.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-qnap-ts433.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-qnap-ts433-pcb-12-10.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-radxa-e25.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-rock-3a.dtb @@ -245,6 +246,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3399-rockpro64-v2-s= creen.dtb rk3399-rockpro64-v2-screen-dtbs :=3D rk3399-rockpro64-v2.dtb \ rk3399-rockpro64-screen.dtbo =20 +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-qnap-ts433-pcb-12-10.dtb +rk3568-qnap-ts433-pcb-12-10-dtbs :=3D rk3568-qnap-ts433.dtb \ + rk3568-qnap-ts433-pcb-12-10.dtbo + dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-wolfvision-pf5-vz-2-uhd.dtb rk3568-wolfvision-pf5-vz-2-uhd-dtbs :=3D rk3568-wolfvision-pf5.dtb \ rk3568-wolfvision-pf5-display-vz.dtbo \ diff --git a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433-pcb-12-10.dtso = b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433-pcb-12-10.dtso new file mode 100644 index 000000000000..ce0fdc9f2989 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433-pcb-12-10.dtso @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Device tree overlay for TS433 board PCBs-12-10 revision. + * + * Copyright (C) 2025 Heiko Stuebner + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + /* + * The default hardware-state of this gpio causes the drive + * to be already running when entering the kernel. + * regulator-boot-on is needed to prevent one additional + * power-cycle on the drive. + * + * With regulator-boot-on we get the expected 1 cycle + * per boot, without it we end up with 2 cycles as seen + * via smartctl. + */ + hdd1_pwr: regulator-hdd1-power { + compatible =3D "regulator-fixed"; + gpio =3D <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hdd1_power_pin>; + regulator-name =3D "hdd1-power"; + regulator-boot-on; + vin-supply =3D <&dc_12v>; + }; + + hdd2_pwr: regulator-hdd2-power { + compatible =3D "regulator-fixed"; + gpio =3D <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hdd2_power_pin>; + regulator-name =3D "hdd2-power"; + regulator-boot-on; + vin-supply =3D <&dc_12v>; + }; + + /* + * HDD3+4 are connected to ports of the PCIe SATA controller. + * Currently there is no way to attach those, so keep them + * always on. + */ + hdd3_pwr: regulator-hdd3-power { + compatible =3D "regulator-fixed"; + gpio =3D <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hdd3_power_pin>; + regulator-name =3D "hdd3-power"; + regulator-always-on; + regulator-boot-on; + vin-supply =3D <&dc_12v>; + }; + + hdd4_pwr: regulator-hdd4-power { + compatible =3D "regulator-fixed"; + gpio =3D <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hdd4_power_pin>; + regulator-name =3D "hdd4-power"; + regulator-always-on; + regulator-boot-on; + vin-supply =3D <&dc_12v>; + }; +}; + +&gpio2 { + hdd1-present-hog { + gpios =3D ; + gpio-hog; + input; + line-name =3D "hdd1-present"; + }; + + hdd2-present-hog { + gpios =3D ; + gpio-hog; + input; + line-name =3D "hdd2-present"; + }; + + hdd3-present-hog { + gpios =3D ; + gpio-hog; + input; + line-name =3D "hdd3-present"; + }; + + hdd4-present-hog { + gpios =3D ; + gpio-hog; + input; + line-name =3D "hdd4-present"; + }; +}; + +&pinctrl { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hdd1_present_pin &hdd2_present_pin &hdd3_present_pin + &hdd4_present_pin>; + + hdd-power { + hdd1_power_pin: hdd1-power-pin { + rockchip,pins =3D <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + hdd2_power_pin: hdd2-power-pin { + rockchip,pins =3D <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + hdd3_power_pin: hdd3-power-pin { + rockchip,pins =3D <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + hdd4_power_pin: hdd4-power-pin { + rockchip,pins =3D <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdd-present { + hdd1_present_pin: hdd1-present-pin { + rockchip,pins =3D <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + hdd2_present_pin: hdd2-present-pin { + rockchip,pins =3D <2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + hdd3_present_pin: hdd3-present-pin { + rockchip,pins =3D <2 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + hdd4_present_pin: hdd4-present-pin { + rockchip,pins =3D <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&sata1_port0 { + target-supply =3D <&hdd2_pwr>; +}; + +&sata2_port0 { + target-supply =3D <&hdd1_pwr>; +}; --=20 2.47.2