From nobody Sat Feb 7 08:23:42 2026 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3566A28B4F0 for ; Sun, 1 Feb 2026 19:18:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769973498; cv=none; b=fmFY8dfwtt6o8Q9GzbXVGDBxl4aGvtA+zDxdPc+81pV6jR5hUUTECvc8d/9F6mrzTmwN3OL7DaGihILppjLxOyDJA23I6GYpQCKFPSP2UQ1+PWiJaVsBRk/B7X4TNRlLOulxIcAza2QaQuS6nhoI1VOvMMtB292MoILKt3MJycc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769973498; c=relaxed/simple; bh=6dldJBM/2Cp1xjI3NY7IFNEv9i0x3pyXd5ED55N2rN0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=pfS6kN91rbitqfeK1ijjfpwmdEHUZnIcauo9gyUIJuAxq0+QriV3EaQdvYOcF03NDxmdmz+EzDCezMTVIUwZEYxMSr93ov+wdEL6K4FcRFxrlgk1ZtrzFnv3rEr0clrcKk+ZGwLyJaKg+pk0PAu9rSso6Pb68EYu6yRjsv6LaDY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=jdU90e/I; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="jdU90e/I" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type; bh=oY9lKxk5AO/OIHyzqKioV0eS8+fpzb5n8emykS9njJM=; b=jdU90e/IR1JOqav8FIufAT2jmH bWn2KNSIY565PRN8uJXaTZAMrcoFb6QUy12CWtz1I4Bn+6U+/vTWjzN4uL0JlwXEU7dE2e0IJtBZY sqbRErmwenVCxxcH92V52Nf2nYTJaJIQriB+/3Nsi90v0MdJ35fW2yISrk4VPmVlCbW3JC0kBF41J lyk3PjBWT+T+DamODQlHDG0kQmonfWBvF82SOeBNcsXGo3RpAqK6NEMZBDfchhQI49zPSWpZmUx19 DOTQpSKKBTI5OIG5wFJTfEOtIB6NMUsv25qonhYhjXQz/fJMyI0Q3+r6n1N7/rUa8/w8pVA7QGJLn v26vCXDw==; Received: from [88.128.88.21] (helo=phil.t-mobile.de) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1vmcxT-005wWz-3W; Sun, 01 Feb 2026 20:18:07 +0100 From: Heiko Stuebner To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] arm64: dts: rockchip: Add port subnodes to RK356x SATA controllers Date: Sun, 1 Feb 2026 20:18:01 +0100 Message-ID: <20260201191804.41421-2-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20260201191804.41421-1-heiko@sntech.de> References: <20260201191804.41421-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SATA controllers on RK356x are identical to the ones found on RK3588, but don't yet provide a port sub-node. Per the datasheet the RK356x also supports the fbscp capability and has the same queue maximums. So add port sub-nodes to both sata controllers on RK356x, and move the phy properties to it. Also add phandles to the ports, so that boards can add their target-supply when available. Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 27 ++++++++++++++++--- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk356x-base.dtsi index b84055a77ac5..c6bd051b6a25 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. */ =20 +#include #include #include #include @@ -234,11 +235,20 @@ sata1: sata@fc400000 { <&cru CLK_SATA1_RXOOB>; clock-names =3D "sata", "pmalive", "rxoob"; interrupts =3D ; - phys =3D <&combphy1 PHY_TYPE_SATA>; - phy-names =3D "sata-phy"; ports-implemented =3D <0x1>; power-domains =3D <&power RK3568_PD_PIPE>; + #address-cells =3D <1>; + #size-cells =3D <0>; status =3D "disabled"; + + sata1_port0: sata-port@0 { + reg =3D <0>; + hba-port-cap =3D ; + phys =3D <&combphy1 PHY_TYPE_SATA>; + phy-names =3D "sata-phy"; + snps,rx-ts-max =3D <32>; + snps,tx-ts-max =3D <32>; + }; }; =20 sata2: sata@fc800000 { @@ -248,11 +258,20 @@ sata2: sata@fc800000 { <&cru CLK_SATA2_RXOOB>; clock-names =3D "sata", "pmalive", "rxoob"; interrupts =3D ; - phys =3D <&combphy2 PHY_TYPE_SATA>; - phy-names =3D "sata-phy"; ports-implemented =3D <0x1>; power-domains =3D <&power RK3568_PD_PIPE>; + #address-cells =3D <1>; + #size-cells =3D <0>; status =3D "disabled"; + + sata2_port0: sata-port@0 { + reg =3D <0>; + hba-port-cap =3D ; + phys =3D <&combphy2 PHY_TYPE_SATA>; + phy-names =3D "sata-phy"; + snps,rx-ts-max =3D <32>; + snps,tx-ts-max =3D <32>; + }; }; =20 usb_host0_xhci: usb@fcc00000 { --=20 2.47.2 From nobody Sat Feb 7 08:23:42 2026 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 357D62BE639 for ; Sun, 1 Feb 2026 19:18:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769973498; cv=none; b=r93dY/36cQyC/vvtSvv9nWxVb3hzgwk0dD0DkS1sHH0uzOs7MNdPaNyUagJSgHeAK5GhhVh4A+eFmWvg9QpEJNpwvSqQ1VN/bPmrZrfLd3XWWVKwbwTE7aqfAl74B/1+EyQt59UqaQ/C4LOZswvvzaGvKv45JltppdDnXWfrkg8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769973498; c=relaxed/simple; bh=HdKjCKYkTUBYWymGVGhnDiISEbQfe6n6+Fjw7/9Oc7s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=AeQpPL3iapTqTqq24KTWLQAmpjHSEJbW1YfB0rX4n4N2TdR4xBQ68YAhR89Cf4Y5bIEV2UhF0cJgIdAQSkWAVF8FpGYAh1CGV9AXlBC+lviPI5ha81kqGp51vU4IsBuMnUIFu9nEQtxT7Qw9AH9R7mDGtLEYaDiILA7WKb+wjXo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=WMeS+fpL; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="WMeS+fpL" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type; bh=zcDBvht1tN7pQSi0T0aBge/reb5eHegqZJLItDNrtYc=; b=WMeS+fpL0Uel8Z4zAfqaUoRggc 2N/TjQ554k0NgIQUhtBzcBt2mYbrS6uQPfJLnkHDq4LlffQk9H6tL89mf0Wwd4wCGQOHYTLp792La AY4sNdeIt51iEkl4t4ek4HgecZmKV+OrCZdgVwlGf3dOARwbOlfVRoVB+HMlvFif9QwaD+NmBaz+y VzMOcsv5HJUQnrvkkoLcj1zqEhWfllBo6QI7e9GxO246SJBnC+V7VnWaqjw3wwzvu5Fks2OSwqL01 MyHPqYxzzDvUaM8vENCt/sN9OnsfgvmHPPBNe0JODISrpPFSG3jOiv/+/fXdNe8b7DnclUkYH1uOr zpIRTm0g==; Received: from [88.128.88.21] (helo=phil.t-mobile.de) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1vmcxT-005wWz-AR; Sun, 01 Feb 2026 20:18:07 +0100 From: Heiko Stuebner To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/4] arm64: dts: rockchip: add overlay for qnap-ts433 device revision Date: Sun, 1 Feb 2026 20:18:02 +0100 Message-ID: <20260201191804.41421-3-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20260201191804.41421-1-heiko@sntech.de> References: <20260201191804.41421-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" TS433 devices received a board revision adding gpios for per hard-disk presence-detection and power-control. These board have a PCB-id of at least 12 (mainboard) and 10 (backplane), which can be read from an EEPROM. The presence detection is not really necessary and there are also no existing bindings for doing something with it. So add them as gpio hogs to at least document them and allow their state to be read from debugfs. The power-control is modelled as regulators, with the hdd1+hdd2 variants connected to the RK3568's SATA controllers as target-supplies. The JMicron AHCI controller on PCIe didn't have bindings for that, I could find, so they get an always-on state for now. Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 5 + .../rockchip/rk3568-qnap-ts433-pcb-12-10.dtso | 151 ++++++++++++++++++ 2 files changed, 156 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433-pcb-12-1= 0.dtso diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index d0f22d3a3bb4..aafffecfb2ef 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -145,6 +145,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-odroid-m1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-photonicat.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-qnap-ts233.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-qnap-ts433.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-qnap-ts433-pcb-12-10.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-radxa-e25.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-rock-3a.dtb @@ -245,6 +246,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3399-rockpro64-v2-s= creen.dtb rk3399-rockpro64-v2-screen-dtbs :=3D rk3399-rockpro64-v2.dtb \ rk3399-rockpro64-screen.dtbo =20 +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-qnap-ts433-pcb-12-10.dtb +rk3568-qnap-ts433-pcb-12-10-dtbs :=3D rk3568-qnap-ts433.dtb \ + rk3568-qnap-ts433-pcb-12-10.dtbo + dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-wolfvision-pf5-vz-2-uhd.dtb rk3568-wolfvision-pf5-vz-2-uhd-dtbs :=3D rk3568-wolfvision-pf5.dtb \ rk3568-wolfvision-pf5-display-vz.dtbo \ diff --git a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433-pcb-12-10.dtso = b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433-pcb-12-10.dtso new file mode 100644 index 000000000000..ce0fdc9f2989 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433-pcb-12-10.dtso @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Device tree overlay for TS433 board PCBs-12-10 revision. + * + * Copyright (C) 2025 Heiko Stuebner + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + /* + * The default hardware-state of this gpio causes the drive + * to be already running when entering the kernel. + * regulator-boot-on is needed to prevent one additional + * power-cycle on the drive. + * + * With regulator-boot-on we get the expected 1 cycle + * per boot, without it we end up with 2 cycles as seen + * via smartctl. + */ + hdd1_pwr: regulator-hdd1-power { + compatible =3D "regulator-fixed"; + gpio =3D <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hdd1_power_pin>; + regulator-name =3D "hdd1-power"; + regulator-boot-on; + vin-supply =3D <&dc_12v>; + }; + + hdd2_pwr: regulator-hdd2-power { + compatible =3D "regulator-fixed"; + gpio =3D <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hdd2_power_pin>; + regulator-name =3D "hdd2-power"; + regulator-boot-on; + vin-supply =3D <&dc_12v>; + }; + + /* + * HDD3+4 are connected to ports of the PCIe SATA controller. + * Currently there is no way to attach those, so keep them + * always on. + */ + hdd3_pwr: regulator-hdd3-power { + compatible =3D "regulator-fixed"; + gpio =3D <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hdd3_power_pin>; + regulator-name =3D "hdd3-power"; + regulator-always-on; + regulator-boot-on; + vin-supply =3D <&dc_12v>; + }; + + hdd4_pwr: regulator-hdd4-power { + compatible =3D "regulator-fixed"; + gpio =3D <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hdd4_power_pin>; + regulator-name =3D "hdd4-power"; + regulator-always-on; + regulator-boot-on; + vin-supply =3D <&dc_12v>; + }; +}; + +&gpio2 { + hdd1-present-hog { + gpios =3D ; + gpio-hog; + input; + line-name =3D "hdd1-present"; + }; + + hdd2-present-hog { + gpios =3D ; + gpio-hog; + input; + line-name =3D "hdd2-present"; + }; + + hdd3-present-hog { + gpios =3D ; + gpio-hog; + input; + line-name =3D "hdd3-present"; + }; + + hdd4-present-hog { + gpios =3D ; + gpio-hog; + input; + line-name =3D "hdd4-present"; + }; +}; + +&pinctrl { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hdd1_present_pin &hdd2_present_pin &hdd3_present_pin + &hdd4_present_pin>; + + hdd-power { + hdd1_power_pin: hdd1-power-pin { + rockchip,pins =3D <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + hdd2_power_pin: hdd2-power-pin { + rockchip,pins =3D <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + hdd3_power_pin: hdd3-power-pin { + rockchip,pins =3D <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + hdd4_power_pin: hdd4-power-pin { + rockchip,pins =3D <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdd-present { + hdd1_present_pin: hdd1-present-pin { + rockchip,pins =3D <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + hdd2_present_pin: hdd2-present-pin { + rockchip,pins =3D <2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + hdd3_present_pin: hdd3-present-pin { + rockchip,pins =3D <2 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + hdd4_present_pin: hdd4-present-pin { + rockchip,pins =3D <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&sata1_port0 { + target-supply =3D <&hdd2_pwr>; +}; + +&sata2_port0 { + target-supply =3D <&hdd1_pwr>; +}; --=20 2.47.2 From nobody Sat Feb 7 08:23:42 2026 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34E67285CBA for ; Sun, 1 Feb 2026 19:18:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769973498; cv=none; b=tvDbFY1t/QpE4pUvg4d3AZncRrmxipEkvYtz7AdET8Ngk6cuAZekM3Ldn0GMREOlyK9mH1aLvUU+5qZv0TTK8+PdNr5P4PN2yKqeez87KNzgEdXa8uz3hPkmfQ7zRC2dOJLP9t+l4fVaw5xoBXnJ7ZTf4OEKCUdR7Crq4C1tdg0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769973498; c=relaxed/simple; bh=/quIDIhvYT0xd93TRjDfaE966sZlzlQ2TLXwBsanY3o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CBuxqoS0hkMRr3P9qlHDjsf+t6lPK09S8kObKXFRuGrQSluox+hPpYBk9WhWVAagVvcQ04eIIMHWZZKgcYcsIShcYj3DiYux2Ns1wGIOqkP67c4KjQd1wc3MdyPNNY6yslNx2GyM9095Jt8fVC8uhuAq4h4TzhDP7ZEq8L36meY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=DQRjQcSA; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="DQRjQcSA" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type; bh=hOlTR5Vmhuawmy3xBlNsvMhKofkPnUj5h5KWQYe85lE=; b=DQRjQcSA6GbaVcVDiMp5HWzFPZ g/712uKRX512vYclwmigRxaGnElz9CUo01UMeAJYhSxBRjBxdoT3kDKSKnSq4XTQF3pyZIqVxTfg+ KO0DXQ84+HPhZHH/jq24hgxwhwYZb57FD5b4CLBlpGnd40wzGeW1Qbr0VZNLEkw8MMuN136vDVu5h 46iEWxfMsQ41dGWTJ2ECPvfixCwbAlqLIMGjaRQ6mYmHzRZGbXKwAdBngB1hKXZ+HfEyYFOxz+n5m w41ct8yiyOU6JtOdeht5kspNcQ7OcGgUb7YN/9Lg3G7XUHZQzot/nB0irWwzEcTc8wfAeCF/4+NqY wMjHVjMw==; Received: from [88.128.88.21] (helo=phil.t-mobile.de) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1vmcxT-005wWz-Ha; Sun, 01 Feb 2026 20:18:08 +0100 From: Heiko Stuebner To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/4] arm64: dts: rockchip: add overlay for qnap-ts233 device revision Date: Sun, 1 Feb 2026 20:18:03 +0100 Message-ID: <20260201191804.41421-4-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20260201191804.41421-1-heiko@sntech.de> References: <20260201191804.41421-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" TS233 devices received a board revision adding gpios for per hard-disk presence-detection and power-control. These boards have a PCB-id of at least 12 (mainboard) and 11 (backplane), which can be read from an EEPROM. The presence detection is not really necessary and there are also no existing bindings for doing something with it. So add them as gpio hogs to at least document them and allow their state to be read from debugfs. The power-control is modelled as regulators, with the hdd1+hdd2 variants connected to the RK3568's SATA controllers as target-supplies. Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 5 + .../rockchip/rk3568-qnap-ts233-pcb-12-11.dtso | 93 +++++++++++++++++++ 2 files changed, 98 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233-pcb-12-1= 1.dtso diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index aafffecfb2ef..c5086aa9c427 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -144,6 +144,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-nanopi-r5s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-odroid-m1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-photonicat.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-qnap-ts233.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-qnap-ts233-pcb-12-11.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-qnap-ts433.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-qnap-ts433-pcb-12-10.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-radxa-e25.dtb @@ -246,6 +247,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3399-rockpro64-v2-s= creen.dtb rk3399-rockpro64-v2-screen-dtbs :=3D rk3399-rockpro64-v2.dtb \ rk3399-rockpro64-screen.dtbo =20 +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-qnap-ts233-pcb-12-11.dtb +rk3568-qnap-ts233-pcb-12-11-dtbs :=3D rk3568-qnap-ts233.dtb \ + rk3568-qnap-ts233-pcb-12-11.dtbo + dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-qnap-ts433-pcb-12-10.dtb rk3568-qnap-ts433-pcb-12-10-dtbs :=3D rk3568-qnap-ts433.dtb \ rk3568-qnap-ts433-pcb-12-10.dtbo diff --git a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233-pcb-12-11.dtso = b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233-pcb-12-11.dtso new file mode 100644 index 000000000000..c7987171644c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233-pcb-12-11.dtso @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Device tree overlay for TS233 board PCBs-12-11 revision. + * + * Copyright (C) 2025 Heiko Stuebner + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + /* + * The default hardware-state of this gpio causes the drive + * to be already running when entering the kernel. + * regulator-boot-on is needed to prevent one additional + * power-cycle on the drive. + * + * With regulator-boot-on we get the expected 1 cycle + * per boot, without it we end up with 2 cycles as seen + * via smartctl. + */ + hdd1_pwr: regulator-hdd1-power { + compatible =3D "regulator-fixed"; + gpio =3D <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hdd1_power_pin>; + regulator-name =3D "hdd1-power"; + regulator-boot-on; + vin-supply =3D <&dc_12v>; + }; + + hdd2_pwr: regulator-hdd2-power { + compatible =3D "regulator-fixed"; + gpio =3D <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hdd2_power_pin>; + regulator-name =3D "hdd2-power"; + regulator-boot-on; + vin-supply =3D <&dc_12v>; + }; +}; + +&gpio2 { + hdd1-present-hog { + gpios =3D ; + gpio-hog; + input; + line-name =3D "hdd1-present"; + }; + + hdd2-present-hog { + gpios =3D ; + gpio-hog; + input; + line-name =3D "hdd2-present"; + }; +}; + +&pinctrl { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hdd1_present_pin &hdd2_present_pin>; + + hdd-power { + hdd1_power_pin: hdd1-power-pin { + rockchip,pins =3D <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + hdd2_power_pin: hdd2-power-pin { + rockchip,pins =3D <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdd-present { + hdd1_present_pin: hdd1-present-pin { + rockchip,pins =3D <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + hdd2_present_pin: hdd2-present-pin { + rockchip,pins =3D <2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&sata1_port0 { + target-supply =3D <&hdd2_pwr>; +}; + +&sata2_port0 { + target-supply =3D <&hdd1_pwr>; +}; --=20 2.47.2 From nobody Sat Feb 7 08:23:42 2026 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 356DF299A8A for ; Sun, 1 Feb 2026 19:18:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769973499; cv=none; b=ifPTG4dIopEua0rJWfW0JNvTjSpL9gOJSGWQ4rwp9eeHFCOFgNbH8rSjdJe6kksulUewj1bNpZfdo4Rtrd1fgqL+p003dnoK9LO+1lr5RCk05YOSoTg4DD1lIR4wszWJENS4RJc26AWmnjFdc6GZhLSS4OQJBhAEL7UaAG3oGJo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769973499; c=relaxed/simple; bh=LvGRC7O5TfBjmVUEsJSSf8SoSMiI8a6vitQ6z4iszr8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dmG8HxphTgaPZHssMpuzkFe4j7PTuIlNbR9w4PiFJZ+M8cs1AQjgiU1/aDlJf1KRHzFPZn16u3smwGiQ9+DPzz8g1RzdCipj8Ao3GblKb2PMUf5icBIVVh7OuohzUhKPRIotEVDOVmm9Q+HUlIOuK+9U9iEIU3A9YK0l+B1NN+c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=Qdj8sKOm; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="Qdj8sKOm" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type; bh=sBJoony19TmpMSQvar+sI3waiK1pCWowuANcsLeM5/E=; b=Qdj8sKOmWmhQqqVq4YbQ4GirLn 75JKvvVZMcgpV0EGpluBTR3WkbdT2pdu9UAdNPwW/GoAHAqfGwc7XSkbMBLReNPoAa4cX7YUakXII tIsPd/uRWrlM3n2cTNifRnrFZdijh4oofsZ1NuessFBEC2LGJ0bf7oPvP98jvieDlTKkoOnUeNl2D UC0lyIy+j0omh2fkLSkBpbsDLRuU/7b7QGbnzU8db8nX0UtQBMsRrduBkWPWOkdlZ/ioizLTfMEC0 FXvP7SXXSLb7JiC95B/Op6OHwkqEYQJ2Vk40CQvW1eK9DY5m/hyRX+M3fEujAOB4iJY+qrOUuy1Xc ulvnND3A==; Received: from [88.128.88.21] (helo=phil.t-mobile.de) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1vmcxT-005wWz-Oj; Sun, 01 Feb 2026 20:18:08 +0100 From: Heiko Stuebner To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/4] arm64: dts: rockchip: add overlay for qnap-ts133 device revision Date: Sun, 1 Feb 2026 20:18:04 +0100 Message-ID: <20260201191804.41421-5-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20260201191804.41421-1-heiko@sntech.de> References: <20260201191804.41421-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" TS433 devices received a board revision adding gpios for per hard-disk presence-detection and power-control. These boards have a PCB-id of at least 13 which can be read from an EEPROM. The presence detection is not really necessary and there are also no existing bindings for doing something with it. So add them as gpio hog to at least document them and allow its state to be read from debugfs. The power-control is modelled as regulator, with connected to the RK3568's SATA controller as target-supply. Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 5 ++ .../rockchip/rk3566-qnap-ts133-pcb-13.dtso | 64 +++++++++++++++++++ 2 files changed, 69 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-qnap-ts133-pcb-13.d= tso diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index c5086aa9c427..40c5a75a2511 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -115,6 +115,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-powkiddy-rgb30.= dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-powkiddy-rk2023.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-powkiddy-x55.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-qnap-ts133.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-qnap-ts133-pcb-13.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-quartz64-a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-quartz64-b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-radxa-cm3-io.dtb @@ -247,6 +248,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3399-rockpro64-v2-s= creen.dtb rk3399-rockpro64-v2-screen-dtbs :=3D rk3399-rockpro64-v2.dtb \ rk3399-rockpro64-screen.dtbo =20 +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-qnap-ts133-pcb-13.dtb +rk3566-qnap-ts133-pcb-13-dtbs :=3D rk3566-qnap-ts133.dtb \ + rk3566-qnap-ts133-pcb-13.dtbo + dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-qnap-ts233-pcb-12-11.dtb rk3568-qnap-ts233-pcb-12-11-dtbs :=3D rk3568-qnap-ts233.dtb \ rk3568-qnap-ts233-pcb-12-11.dtbo diff --git a/arch/arm64/boot/dts/rockchip/rk3566-qnap-ts133-pcb-13.dtso b/a= rch/arm64/boot/dts/rockchip/rk3566-qnap-ts133-pcb-13.dtso new file mode 100644 index 000000000000..f9a8194f5753 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-qnap-ts133-pcb-13.dtso @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Device tree overlay for TS133 board PCB-13 revision. + * + * Copyright (C) 2025 Heiko Stuebner + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + /* + * The default hardware-state of this gpio causes the drive + * to be already running when entering the kernel. + * regulator-boot-on is needed to prevent one additional + * power-cycle on the drive. + * + * With regulator-boot-on we get the expected 1 cycle + * per boot, without it we end up with 2 cycles as seen + * via smartctl. + */ + hdd1_pwr: regulator-hdd1-power { + compatible =3D "regulator-fixed"; + gpio =3D <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hdd1_power_pin>; + regulator-name =3D "hdd1-power"; + regulator-boot-on; + vin-supply =3D <&dc_12v>; + }; +}; + +&gpio2 { + hdd1-present-hog { + gpios =3D ; + gpio-hog; + input; + line-name =3D "hdd1-present"; + }; +}; + +&pinctrl { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hdd1_present_pin>; + + hdd-power { + hdd1_power_pin: hdd1-power-pin { + rockchip,pins =3D <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdd-present { + hdd1_present_pin: hdd1-present-pin { + rockchip,pins =3D <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&sata2_port0 { + target-supply =3D <&hdd1_pwr>; +}; --=20 2.47.2