From nobody Tue Feb 10 12:57:27 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6DE223D2B4; Sun, 1 Feb 2026 08:15:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769933729; cv=none; b=dnv0QJo5pMWIxkuuvmD/lDpz4ff3CMLk3A/1xrc6ytprAe+AkNKLmKxQCFZlr+rBYl/iC3j+P1CIvq2AFVMnwKTHIUKlwNzC+pTtWB0XSE9EW52NbQ48KN0nBglN/AlHVM+p9kRCo/UHW2EcOgyP3a8a4z9TrkLDsgE8FMFw3Z0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769933729; c=relaxed/simple; bh=FzBTD+S7513EuFmRGeBcFGjeVmO7k9yNQXrJVkyx/3g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=f4ZoESI5dBE2Zu95rdNZMKVdgtXWDflXvZG1SmQonXA7fS3LuBybxZ3RjuH9os0xGiEZnbCKHuIcPqVDZr3ZPEce9idOIlmGdEwoZSOiJBkP422J06H4cDg0kM7bDcQvSFaNQ2DkW4zAKvP41lJbjPFjAqqappTOK0xbdJFKXhc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=Jxs4GulN; arc=none smtp.client-ip=117.135.210.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="Jxs4GulN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=PS OwGDUdVdduIta+j2KKb1RKHKHSYr2bnlnBAZBE19k=; b=Jxs4GulNiuuEZxf5uL mQ1t6YRz/A3fJAjuZFtb9JXef29b5e2s5oSd2CYQzJuN1zdh7PbizWtj8ivsdlz+ mfWzqAjyZGJ1ojhCiUGNiTn9F1LKOAQ2STGELgY1IDSZqHyIaiAKB+8wc7ongEM0 lnNfFaVB45IIUaKbSRO55TUPo= Received: from ProDesk-480.. (unknown []) by gzga-smtp-mtada-g0-2 (Coremail) with SMTP id _____wD3Hz40C39pmxGTKQ--.55310S4; Sun, 01 Feb 2026 16:13:48 +0800 (CST) From: Andy Yan To: dmitry.baryshkov@oss.qualcomm.com, heiko@sntech.de Cc: alchark@gmail.com, andrzej.hajda@intel.com, conor+dt@kernel.org, cristian.ciocaltea@collabora.com, airlied@gmail.com, jernej.skrabec@gmail.com, jonas@kwiboo.se, kever.yang@rock-chips.com, krzk+dt@kernel.org, Laurent.pinchart@ideasonboard.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, neil.armstrong@linaro.org, nicolas.frattaroli@collabora.com, robh@kernel.org, rfoss@kernel.org, hjc@rock-chips.com, sebastian.reichel@collabora.com, simona@ffwll.ch, tzimmermann@suse.de, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Andy Yan Subject: [PATCH v2 2/5] drm/bridge: synopsys: dw-dp: Set pixel mode by platform data Date: Sun, 1 Feb 2026 16:13:28 +0800 Message-ID: <20260201081338.407999-3-andyshrk@163.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260201081338.407999-1-andyshrk@163.com> References: <20260201081338.407999-1-andyshrk@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wD3Hz40C39pmxGTKQ--.55310S4 X-Coremail-Antispam: 1Uf129KBjvJXoWxuF4UXFyDtF47tr1xJF4Utwb_yoWrAw4rpF WxJFW5KrWkKF4Y9a48ArWkCFn0yw1q9ayxJa1xGw4Ik34fKFn5Xr9Ivr15Wrn7XF9xur13 CrsrJrW8ZF1jkrUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07jmrWwUUUUU= X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/xtbC7RwMaml-CzxsDAAA3W Content-Type: text/plain; charset="utf-8" From: Andy Yan In the implementation and integration of the SoC, the DW DisplayPort hardware block can be configured to work in single, dual, quad pixel mode on differnt platforms, so make the pixel mode set by plat_data to support the upcoming rk3576 variant. Signed-off-by: Andy Yan Reviewed-by: Sebastian Reichel Tested-by: Sebastian Reichel --- Changes in v2: - Commit message improve: The pixel mode is determined during the IC integration stage drivers/gpu/drm/bridge/synopsys/dw-dp.c | 8 +------- drivers/gpu/drm/rockchip/dw_dp-rockchip.c | 19 +++++++++++++++---- include/drm/bridge/dw_dp.h | 7 +++++++ 3 files changed, 23 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-dp.c b/drivers/gpu/drm/brid= ge/synopsys/dw-dp.c index 82aaf74e1bc0..eccf6299bdb7 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-dp.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-dp.c @@ -352,12 +352,6 @@ enum { DW_DP_YCBCR420_16BIT, }; =20 -enum { - DW_DP_MP_SINGLE_PIXEL, - DW_DP_MP_DUAL_PIXEL, - DW_DP_MP_QUAD_PIXEL, -}; - enum { DW_DP_SDP_VERTICAL_INTERVAL =3D BIT(0), DW_DP_SDP_HORIZONTAL_INTERVAL =3D BIT(1), @@ -1984,7 +1978,7 @@ struct dw_dp *dw_dp_bind(struct device *dev, struct d= rm_encoder *encoder, return ERR_CAST(dp); =20 dp->dev =3D dev; - dp->pixel_mode =3D DW_DP_MP_QUAD_PIXEL; + dp->pixel_mode =3D plat_data->pixel_mode; =20 dp->plat_data.max_link_rate =3D plat_data->max_link_rate; bridge =3D &dp->bridge; diff --git a/drivers/gpu/drm/rockchip/dw_dp-rockchip.c b/drivers/gpu/drm/ro= ckchip/dw_dp-rockchip.c index 25ab4e46301e..89d614d53596 100644 --- a/drivers/gpu/drm/rockchip/dw_dp-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_dp-rockchip.c @@ -75,7 +75,7 @@ static const struct drm_encoder_helper_funcs dw_dp_encode= r_helper_funcs =3D { static int dw_dp_rockchip_bind(struct device *dev, struct device *master, = void *data) { struct platform_device *pdev =3D to_platform_device(dev); - struct dw_dp_plat_data plat_data; + const struct dw_dp_plat_data *plat_data; struct drm_device *drm_dev =3D data; struct rockchip_dw_dp *dp; struct drm_encoder *encoder; @@ -89,7 +89,10 @@ static int dw_dp_rockchip_bind(struct device *dev, struc= t device *master, void * dp->dev =3D dev; platform_set_drvdata(pdev, dp); =20 - plat_data.max_link_rate =3D 810000; + plat_data =3D of_device_get_match_data(dev); + if (!plat_data) + return -ENODEV; + encoder =3D &dp->encoder.encoder; encoder->possible_crtcs =3D drm_of_find_possible_crtcs(drm_dev, dev->of_n= ode); rockchip_drm_encoder_set_crtc_endpoint_id(&dp->encoder, dev->of_node, 0, = 0); @@ -99,7 +102,7 @@ static int dw_dp_rockchip_bind(struct device *dev, struc= t device *master, void * return ret; drm_encoder_helper_add(encoder, &dw_dp_encoder_helper_funcs); =20 - dp->base =3D dw_dp_bind(dev, encoder, &plat_data); + dp->base =3D dw_dp_bind(dev, encoder, plat_data); if (IS_ERR(dp->base)) { ret =3D PTR_ERR(dp->base); return ret; @@ -134,8 +137,16 @@ static void dw_dp_remove(struct platform_device *pdev) component_del(dp->dev, &dw_dp_rockchip_component_ops); } =20 +static const struct dw_dp_plat_data rk3588_dp_plat_data =3D { + .max_link_rate =3D 810000, + .pixel_mode =3D DW_DP_MP_QUAD_PIXEL, +}; + static const struct of_device_id dw_dp_of_match[] =3D { - { .compatible =3D "rockchip,rk3588-dp", }, + { + .compatible =3D "rockchip,rk3588-dp", + .data =3D &rk3588_dp_plat_data, + }, {} }; MODULE_DEVICE_TABLE(of, dw_dp_of_match); diff --git a/include/drm/bridge/dw_dp.h b/include/drm/bridge/dw_dp.h index d05df49fd884..25363541e69d 100644 --- a/include/drm/bridge/dw_dp.h +++ b/include/drm/bridge/dw_dp.h @@ -11,8 +11,15 @@ struct drm_encoder; struct dw_dp; =20 +enum { + DW_DP_MP_SINGLE_PIXEL, + DW_DP_MP_DUAL_PIXEL, + DW_DP_MP_QUAD_PIXEL, +}; + struct dw_dp_plat_data { u32 max_link_rate; + u8 pixel_mode; }; =20 struct dw_dp *dw_dp_bind(struct device *dev, struct drm_encoder *encoder, --=20 2.43.0