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Sun, 1 Feb 2026 06:35:03 -0800 From: Edward Srouji Date: Sun, 1 Feb 2026 16:34:06 +0200 Subject: [PATCH rdma-next v3 3/3] RDMA/mlx5: Implement DMABUF export ops Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260201-dmabuf-export-v3-3-da238b614fe3@nvidia.com> References: <20260201-dmabuf-export-v3-0-da238b614fe3@nvidia.com> In-Reply-To: <20260201-dmabuf-export-v3-0-da238b614fe3@nvidia.com> To: Jason Gunthorpe , Leon Romanovsky , "Sumit Semwal" , =?utf-8?q?Christian_K=C3=B6nig?= CC: , , , , , Yishai Hadas , "Edward Srouji" X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1769956492; l=3906; i=edwards@nvidia.com; s=20251029; h=from:subject:message-id; bh=hrI5fWihP4FczMXXbh00GHcjyD2++jtKryVnX4Jyft4=; b=vdLJOY5jw3ITJG9c/JjQ1/0LF/XJdq1Q0EkPwU+TptD4zzP7IOJMhEvdyACZ/FCu3JwaYggt/ NpJY/1MhBOPCmwtMaMlahk6icMGm5zsWBxr3Frmhc2HCEies2lh5jLi X-Developer-Key: i=edwards@nvidia.com; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 0+kHjo5gv891JuMXnKTsNxp3fwyX/3m7ODA8376tip/IRzZeV2g9+9bMaCWaU3pqSzyu4uZM+nok4/g/bAnE9D+/lJiinqizy877kygvf4bohIxfcqryN1j+k5VMg7bUqV2kt7oSiGQkkAr43v8yYG+LKg8Hxo/9xvIuN4/xMcqMNrPQ5hMrjPnW5OFzJNHHajsOjFs5fe9DgpeBx0Vud4hn1wptpB+bGIHfquAfFPK5KPgt0ANEaOnP/1HJIPEtPwdqJs1j2CIEJjhuombZ70EtpfrM0cAZrIsLbxjNugbHnWgqlOxBhnXAzZZ7l+9Hp/sx2dWk1NKC0747LDK6IeQEfByIKb1H9mr+1jpboBr5MdUr/ixha4j+j9QcluoBPLxb88V9wFpfCKsWFTaeUNk+qPuSXElbgexZx2JZWwkxlS5dCmM9ZWm7e2zel8ww X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Feb 2026 14:35:24.5831 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dba21f91-ed40-4db8-c324-08de619f22f9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B070.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8277 From: Yishai Hadas Enable p2pdma on the mlx5 PCI device to allow DMABUF-based peer-to-peer DMA mappings. Add implementation of the mmap_get_pfns and pgoff_to_mmap_entry device operations required for DMABUF support in the mlx5 RDMA driver. The pgoff_to_mmap_entry operation converts a page offset to the corresponding rdma_user_mmap_entry by extracting the command and index from the offset and looking it up in the ucontext's mmap_xa. The mmap_get_pfns operation retrieves the physical address and length from the mmap entry and obtains the p2pdma provider for the underlying PCI device, which is needed for peer-to-peer DMA operations with DMABUFs. Signed-off-by: Yishai Hadas Signed-off-by: Edward Srouji --- drivers/infiniband/hw/mlx5/main.c | 72 +++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 72 insertions(+) diff --git a/drivers/infiniband/hw/mlx5/main.c b/drivers/infiniband/hw/mlx5= /main.c index e81080622283..f97c86c96d83 100644 --- a/drivers/infiniband/hw/mlx5/main.c +++ b/drivers/infiniband/hw/mlx5/main.c @@ -2446,6 +2446,70 @@ static int mlx5_ib_mmap_clock_info_page(struct mlx5_= ib_dev *dev, virt_to_page(dev->mdev->clock_info)); } =20 +static int phys_addr_to_bar(struct pci_dev *pdev, phys_addr_t pa) +{ + resource_size_t start, end; + int bar; + + for (bar =3D 0; bar < PCI_STD_NUM_BARS; bar++) { + /* Skip BARs not present or not memory-mapped */ + if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) + continue; + + start =3D pci_resource_start(pdev, bar); + end =3D pci_resource_end(pdev, bar); + + if (!start || !end) + continue; + + if (pa >=3D start && pa <=3D end) + return bar; + } + + return -1; +} + +static int mlx5_ib_mmap_get_pfns(struct rdma_user_mmap_entry *entry, + struct dma_buf_phys_vec *phys_vec, + struct p2pdma_provider **provider) +{ + struct mlx5_user_mmap_entry *mentry =3D to_mmmap(entry); + struct pci_dev *pdev =3D to_mdev(entry->ucontext->device)->mdev->pdev; + int bar; + + phys_vec->paddr =3D mentry->address; + phys_vec->len =3D entry->npages * PAGE_SIZE; + + bar =3D phys_addr_to_bar(pdev, phys_vec->paddr); + if (bar < 0) + return -EINVAL; + + *provider =3D pcim_p2pdma_provider(pdev, bar); + /* If the kernel was not compiled with CONFIG_PCI_P2PDMA the + * functionality is not supported. + */ + if (!*provider) + return -EOPNOTSUPP; + + return 0; +} + +static struct rdma_user_mmap_entry * +mlx5_ib_pgoff_to_mmap_entry(struct ib_ucontext *ucontext, off_t pg_off) +{ + unsigned long entry_pgoff; + unsigned long idx; + u8 command; + + pg_off =3D pg_off >> PAGE_SHIFT; + command =3D get_command(pg_off); + idx =3D get_extended_index(pg_off); + + entry_pgoff =3D command << 16 | idx; + + return rdma_user_mmap_entry_get_pgoff(ucontext, entry_pgoff); +} + static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry) { struct mlx5_user_mmap_entry *mentry =3D to_mmmap(entry); @@ -4360,7 +4424,13 @@ static int mlx5_ib_stage_init_init(struct mlx5_ib_de= v *dev) if (err) goto err_mp; =20 + err =3D pcim_p2pdma_init(mdev->pdev); + if (err && err !=3D -EOPNOTSUPP) + goto err_dd; + return 0; +err_dd: + mlx5_ib_data_direct_cleanup(dev); err_mp: mlx5_ib_cleanup_multiport_master(dev); err: @@ -4412,11 +4482,13 @@ static const struct ib_device_ops mlx5_ib_dev_ops = =3D { .map_mr_sg_pi =3D mlx5_ib_map_mr_sg_pi, .mmap =3D mlx5_ib_mmap, .mmap_free =3D mlx5_ib_mmap_free, + .mmap_get_pfns =3D mlx5_ib_mmap_get_pfns, .modify_cq =3D mlx5_ib_modify_cq, .modify_device =3D mlx5_ib_modify_device, .modify_port =3D mlx5_ib_modify_port, .modify_qp =3D mlx5_ib_modify_qp, .modify_srq =3D mlx5_ib_modify_srq, + .pgoff_to_mmap_entry =3D mlx5_ib_pgoff_to_mmap_entry, .pre_destroy_cq =3D mlx5_ib_pre_destroy_cq, .poll_cq =3D mlx5_ib_poll_cq, .post_destroy_cq =3D mlx5_ib_post_destroy_cq, --=20 2.47.1