From nobody Sat Feb 7 17:20:42 2026 Received: from out30-119.freemail.mail.aliyun.com (out30-119.freemail.mail.aliyun.com [115.124.30.119]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B1332DC76D for ; Sat, 31 Jan 2026 11:24:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.119 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769858693; cv=none; b=k9m7KZdxqfJJ0Lx7DEXM6HwxTKVJbG3P9Vx0OzbwqSTDM/t2vA81Gj3gZ2iNNa6NzlLOkeDTq+qAmYkcdRqRtfePqRnBMTDEAphho9CxuxjAH+1Qad/OBm5so1NOGbrWex85VHGARkND7FD+yOsZx0l676VQMrMlqc/2yKuO5Rc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769858693; c=relaxed/simple; bh=+81Lc4RbdNd3RizchaG1jL/RkliJOg1BMv5we/HBY4s=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=CeryFOBDXB0sqacodk8ubf50frxPdmdJwFJMI7usoKhvUhRKgnTvWWAM3ebr9ZtBFF0HWb/400OMinRouvDGJRrLpHuQqBoNjnkQb+BzFbLvRKEcQDOxAglgP2q9ZqAd2GCnL27XfuRMElz5qhlLZ0nIgQaVyvpDTD+8jONyKjc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=IuaQGfPG; arc=none smtp.client-ip=115.124.30.119 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="IuaQGfPG" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1769858688; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=akXybSjiEsQDFdR5RqRjQbmk8U+vkxwa3dzuvwZ5qzU=; b=IuaQGfPGpUs4yQSQk8hnGWE1ggw/hjtS24MXKA7CHwrwTHsn8JGqQxftrP94lUcySqM7mN7Ar6FxAJqmgrHbdfwPx6Byzcyj2RnZf6jfLAk0s+H8qWR+I9B04lI6MuXgoRx7AdPB7kjBx0UyBCsXmbv15iTezuWctLH77Uv3fnM= Received: from DESKTOP-S9E58SO.localdomain(mailfrom:cp0613@linux.alibaba.com fp:SMTPD_---0WyDU-mf_1769858683 cluster:ay36) by smtp.aliyun-inc.com; Sat, 31 Jan 2026 19:24:47 +0800 From: cp0613@linux.alibaba.com To: atish.patra@linux.dev, anup@brainfault.org, alex@ghiti.fr, pjw@kernel.org, guoren@kernel.org Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Chen Pei Subject: [PATCH] drivers/perf: riscv: Keep the fixed counter counting Date: Sat, 31 Jan 2026 19:24:40 +0800 Message-ID: <20260131112440.2915-1-cp0613@linux.alibaba.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen Pei The RISC-V SBI PMU driver disables all PMU counters during initialization via pmu_sbi_stop_all. For fixed counters CYCLE, TIME and INSTRET, this is unnecessary for the following two reasons: 1. Some kernel driver code may directly read CYCLE and INSTRET to perform simple performance analysis. 2. In legacy mode, user space directly reads CYCLE and INSTRET. (echo 2 > /proc/sys/kernel/perf_user_access) Therefore, We keep counting CYCLE, TIME and INSTRET. Signed-off-by: Chen Pei --- drivers/perf/riscv_pmu_sbi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 7dd282da67ce..93aaab324443 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -899,6 +899,9 @@ static int pmu_sbi_get_ctrinfo(int nctr, unsigned long = *mask) =20 static inline void pmu_sbi_stop_all(struct riscv_pmu *pmu) { + /* We keep counting CYCLE, TIME and INSTRET. */ + pmu->cmask &=3D ~0x7; + /* * No need to check the error because we are disabling all the counters * which may include counters that are not enabled yet. --=20 2.50.1