From nobody Tue Feb 10 10:55:16 2026 Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 81E6D2D2496; Sat, 31 Jan 2026 09:46:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.84 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769852772; cv=none; b=R/2JaUu/JAjj09ZnaHnBGc1+oUV4zEzcyDrEJAqCPDr4si6DeOrQhn7GXW5482BSTkBHWxH1do3hAjQ3bMSrgPZL1zEmJ8Dv1Tj3MH+YzfthtKS3BTaeihbm7hQaF1pkpUMIwkkrJ44s79VrKQtC5EolT6m2Arwrpgxk5Ygme+I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769852772; c=relaxed/simple; bh=shMbLGZHM/sh1xXyGXCdDY0fKKks/y6FdTRXE2Z2aPI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IHUYKwmpdDvZ86jtx1ZUfZqRRI5vrQNsKkD7wkSGCQ76dxllk2tBkCrLLtEep1Hl25kDa8Nr7xkFWaJssTVXv0tTP5UbsRR9BT9ri+5bNe5mB+yWjkPrjzsudiPZzQm64LP+s3Ct9Na6cRkCqA6l2DmaukSD6YBRBHaFV7Y5+GM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.84 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from edelgard.fodlan.icenowy.me (unknown [112.94.102.235]) by APP-05 (Coremail) with SMTP id zQCowAC3Sw9Rz31p9UgiBw--.57463S4; Sat, 31 Jan 2026 17:46:02 +0800 (CST) From: Icenowy Zheng To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Huacai Chen , Jiaxun Yang Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, Icenowy Zheng Subject: [PATCH 2/8] dt-bindings: interrupt-controller: add LS7A PCH LPC Date: Sat, 31 Jan 2026 17:45:41 +0800 Message-ID: <20260131094547.455916-3-zhengxingda@iscas.ac.cn> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260131094547.455916-1-zhengxingda@iscas.ac.cn> References: <20260131094547.455916-1-zhengxingda@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: zQCowAC3Sw9Rz31p9UgiBw--.57463S4 X-Coremail-Antispam: 1UD129KBjvJXoW7tr15XrW7Ar47Wr17Kw4rXwb_yoW8ZFykpF 45C3ZxWr48tF13C3yFga40kF13Zr98ArnxCws7tw47Gr9Fga4UX3yakF95X3WfGr9rXa47 ZFyF93W8KwnrJF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmj14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jryl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_GcCE3s1l84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s0DM2AI xVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20x vE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xv r2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2IY04 v7MxkF7I0En4kS14v26r1q6r43MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j 6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7 AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE 2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcV C2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2Kfnx nUUI43ZEXa7VUbH5lUUUUUU== X-CM-SenderInfo: x2kh0wp0lqwv3d6l2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" Loongson 7A series PCH contains an LPC controller with an interrupt controller. Add the device tree binding for the interrupt controller. Signed-off-by: Icenowy Zheng --- .../loongson,pch-lpc.yaml | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= loongson,pch-lpc.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongso= n,pch-lpc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loo= ngson,pch-lpc.yaml new file mode 100644 index 0000000000000..c00fbf31f47f0 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-l= pc.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-lpc.y= aml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson PCH LPC Controller + +maintainers: + - Jiaxun Yang + +description: + This interrupt controller is found in the Loongson LS7A family of PCH for + accepting interrupts sent by LPC-connected peripherals and signalling PIC + via a single interrupt line when interrupts are available. + +properties: + compatible: + const: loongson,pch-lpc-1.0 + + reg: + maxItems: 1 + + interrupt-controller: true + + interrupts: + maxItems: 1 + + '#interrupt-cells': + const: 2 + +required: + - compatible + - reg + - interrupt-controller + - interrupts + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + #include + lpc: interrupt-controller@10002000 { + compatible =3D "loongson,pch-lpc-1.0"; + reg =3D <0x10002000 0x400>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&pic>; + interrupts =3D <19 IRQ_TYPE_LEVEL_HIGH>; + }; +... --=20 2.52.0