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(unknown [210.73.43.101]) by APP-05 (Coremail) with SMTP id zQCowAA3zRB1T31p+GgaBw--.52843S2; Sat, 31 Jan 2026 08:40:22 +0800 (CST) From: Jiakai Xu To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: Andrew Jones , Alexandre Ghiti , Albert Ou , Palmer Dabbelt , Paul Walmsley , Atish Patra , Anup Patel , Jiakai Xu , Jiakai Xu Subject: [PATCH v4] RISC-V: KVM: Validate SBI STA shmem alignment in kvm_sbi_ext_sta_set_reg Date: Sat, 31 Jan 2026 00:40:19 +0000 Message-Id: <20260131004019.1486274-1-xujiakai2025@iscas.ac.cn> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: zQCowAA3zRB1T31p+GgaBw--.52843S2 X-Coremail-Antispam: 1UD129KBjvJXoWxXF4xXFyfKw4fZrW5Cry7trb_yoWrJryrpF 4Ikw15ArWxtFZ7A39rZr4vgr1j93ykKr1UtF9xu34rZF4ktFyYyrna93y7ZFy5JFykZFyS yr10vF1Duw45taUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUB214x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j 6F4UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVWxJr 0_GcWlnxkEFVAIw20F6cxK64vIFxWle2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xv F2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r 4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I 648v4I1lFIxGxcIEc7CjxVA2Y2ka0xkIwI1lc7CjxVAaw2AFwI0_Jw0_GFyl42xK82IYc2 Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s02 6x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0x vE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF0xvE 42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6x kF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjfUOmhFUUUUU X-CM-SenderInfo: 50xmxthndljiysv6x2xfdvhtffof0/1tbiDAYECWl8yMbIFwAAsD Content-Type: text/plain; charset="utf-8" The RISC-V SBI Steal-Time Accounting (STA) extension requires the shared memory physical address to be 64-byte aligned, and the shared memory size to be at least 64 bytes. KVM exposes the SBI STA shared memory configuration to userspace via KVM_SET_ONE_REG. However, the current implementation of kvm_sbi_ext_sta_set_reg() does not validate the alignment of the configured shared memory address. As a result, userspace can install a misaligned shared memory address that violates the SBI specification. Such an invalid configuration may later reach runtime code paths that assume a valid and properly aligned shared memory region. In particular, KVM_RUN can trigger the following WARN_ON in kvm_riscv_vcpu_record_steal_time(): WARNING: arch/riscv/kvm/vcpu_sbi_sta.c:49 at kvm_riscv_vcpu_record_steal_time WARN_ON paths are not expected to be reachable during normal runtime execution, and may result in a kernel panic when panic_on_warn is enabled. Fix this by validating the shared memory alignment at the KVM_SET_ONE_REG boundary and rejecting misaligned configurations with -EINVAL. The validation is performed on a temporary computed address and only committed to vcpu->arch.sta.shmem once it is known to be valid,=20 similar to the existing logic in kvm_sbi_sta_steal_time_set_shmem() and kvm_sbi_ext_sta_handler(). With this change, invalid userspace state is rejected early and cannot reach runtime code paths that rely on the SBI specification invariants. A reproducer triggering the WARN_ON and the complete kernel log are available at: https://github.com/j1akai/temp/tree/main/20260124 Fixes: f61ce890b1f074 ("RISC-V: KVM: Add support for SBI STA registers") Signed-off-by: Jiakai Xu Signed-off-by: Jiakai Xu --- V3 -> V4: Declared new_shmem at the top of kvm_sbi_ext_sta_set_reg(). Initialized new_shmem to 0 instead of vcpu->arch.sta.shmem. Added blank lines per review feedback. V2 -> V3: Added parentheses to function name in subject. V1 -> V2: Added Fixes tag. --- arch/riscv/kvm/vcpu_sbi_sta.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/arch/riscv/kvm/vcpu_sbi_sta.c b/arch/riscv/kvm/vcpu_sbi_sta.c index afa0545c3bcfc..bb13aa8eab7ee 100644 --- a/arch/riscv/kvm/vcpu_sbi_sta.c +++ b/arch/riscv/kvm/vcpu_sbi_sta.c @@ -181,6 +181,7 @@ static int kvm_sbi_ext_sta_set_reg(struct kvm_vcpu *vcp= u, unsigned long reg_num, unsigned long reg_size, const void *reg_val) { unsigned long value; + gpa_t new_shmem =3D 0; =20 if (reg_size !=3D sizeof(unsigned long)) return -EINVAL; @@ -191,18 +192,18 @@ static int kvm_sbi_ext_sta_set_reg(struct kvm_vcpu *v= cpu, unsigned long reg_num, if (IS_ENABLED(CONFIG_32BIT)) { gpa_t hi =3D upper_32_bits(vcpu->arch.sta.shmem); =20 - vcpu->arch.sta.shmem =3D value; - vcpu->arch.sta.shmem |=3D hi << 32; + new_shmem =3D value; + new_shmem |=3D hi << 32; } else { - vcpu->arch.sta.shmem =3D value; + new_shmem =3D value; } break; case KVM_REG_RISCV_SBI_STA_REG(shmem_hi): if (IS_ENABLED(CONFIG_32BIT)) { gpa_t lo =3D lower_32_bits(vcpu->arch.sta.shmem); =20 - vcpu->arch.sta.shmem =3D ((gpa_t)value << 32); - vcpu->arch.sta.shmem |=3D lo; + new_shmem =3D ((gpa_t)value << 32); + new_shmem |=3D lo; } else if (value !=3D 0) { return -EINVAL; } @@ -211,6 +212,11 @@ static int kvm_sbi_ext_sta_set_reg(struct kvm_vcpu *vc= pu, unsigned long reg_num, return -ENOENT; } =20 + if (new_shmem && !IS_ALIGNED(new_shmem, 64)) + return -EINVAL; + + vcpu->arch.sta.shmem =3D new_shmem; + return 0; } =20 --=20 2.34.1